From 57f5168408a539ca89c2f8892783bb8861fc012d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 May 2023 00:04:12 -0700 Subject: [PATCH] Set number of idbits correctly for fpga ddr --- fpga/src/main/scala/arty100t/Harness.scala | 2 +- fpga/src/main/scala/vc707/TestHarness.scala | 2 +- fpga/src/main/scala/vcu118/TestHarness.scala | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 94ba6b45..94dcb458 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -40,7 +40,7 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay] val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( name = "chip_ddr", - sourceId = IdRange(0, 64) + sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits) ))))) val ddrBlockDuringReset = LazyModule(new TLBlockDuringReset(4)) ddrOverlay.overlayOutput.ddr := ddrBlockDuringReset.node := ddrClient diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 1293d26a..2b4b5047 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -78,7 +78,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( name = "chip_ddr", - sourceId = IdRange(0, 64) + sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits) ))))) ddrNode := ddrClient diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 07a5f8b4..ac9f9d05 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -82,7 +82,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S // connect 1 mem. channel to the FPGA DDR val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( name = "chip_ddr", - sourceId = IdRange(0, 64) + sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits) ))))) ddrNode := ddrClient