From ff583e9e1f5c136d65f510c35584fe2ffff46815 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 20 May 2020 15:44:07 -0700 Subject: [PATCH 001/457] first attempt decoupling --- .../src/main/scala/ConfigFragments.scala | 23 +++++++++--- .../src/main/scala/CoreRegistrar.scala | 37 +++++++++++++++++++ .../chipyard/src/main/scala/Subsystem.scala | 33 ++++++++++------- .../chipyard/src/main/scala/TestSuites.scala | 11 +++--- .../scala/stage/phases/AddDefaultTests.scala | 4 +- 5 files changed, 82 insertions(+), 26 deletions(-) create mode 100644 generators/chipyard/src/main/scala/CoreRegistrar.scala diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 72eaa414..3db4f326 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -3,7 +3,7 @@ package chipyard.config import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.config.{Field, Parameters, Config, View} import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams @@ -13,7 +13,6 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import freechips.rocketchip.util.{AsyncResetReg} import boom.common.{BoomTilesKey} -import ariane.{ArianeTilesKey} import testchipip._ import hwacha.{Hwacha} @@ -23,6 +22,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} +import chipyard.{CoreRegistrar, CoreRegisterEntryBase} /** * TODO: Why do we need this? @@ -147,8 +147,21 @@ class WithControlCore extends Config((site, here, up) => { case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) +trait TraceIOMatch { + this: CoreRegisterEntryBase => + val matchTile: (View, View, View) => PartialFunction[Field[Seq[TileParams]],Any] = ((site, here, up) => { + // TODO: XXX What's the "tile" here? + case tilesKey => up(tilesKey) map (tile => tile.copy(trace = true)) + }) +} + class WithTraceIO extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) - case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) - case TracePortKey => Some(TracePortParams()) + val coreMatch = (coreList: List[CoreRegisterEntryBase]) => coreList match { + case coreEntry :: tail => coreEntry.matchTile(site, here, up) orElse coreMatch(tail) + case Nil => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) + } + } + coreMatch(CoreRegistrar.cores) }) diff --git a/generators/chipyard/src/main/scala/CoreRegistrar.scala b/generators/chipyard/src/main/scala/CoreRegistrar.scala new file mode 100644 index 00000000..a0b1625c --- /dev/null +++ b/generators/chipyard/src/main/scala/CoreRegistrar.scala @@ -0,0 +1,37 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Parameters, Config, Field} +import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams} +import freechips.rocketchip.devices.tilelink.{BootROMParams} +import freechips.rocketchip.diplomacy.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing} +import freechips.rocketchip.rocket._ +import freechips.rocketchip.tile._ + +import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} + +import chipyard.config.TraceIOMatch + +// Third-party core entries +sealed trait CoreRegisterEntryBase { + type Tile + type TitleParams + def tilesKey: Field[Seq[TitleParams]] + def crossingKey: Field[Seq[RocketCrossingParams]] +} + +class CoreRegisterEntry[TileT <: BaseTile, TileParamsT <: CoreParams](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]]) + extends CoreRegisterEntryBase with TraceIOMatch { + type Tile = TileT + type TileParams = TileParamsT + def tilesKey = tk + def crossingKey = ck +} + +object CoreRegistrar { + val cores: List[CoreRegisterEntryBase] = List( + // ADD YOUR CORE DEFINITION HERE + new CoreRegisterEntry[ArianeTile, ArianeTileParams](ArianeTilesKey, ArianeCrossingKey) + ) +} \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 99c31472..fcb58fc4 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -22,7 +22,6 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} -import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} import testchipip.{DromajoHelper} @@ -36,14 +35,17 @@ trait HasChipyardTiles extends HasTiles protected val rocketTileParams = p(RocketTilesKey) protected val boomTileParams = p(BoomTilesKey) - protected val arianeTileParams = p(ArianeTilesKey) + protected val coreTileParams = CoreRegistrar.cores map (coreType => p(coreType.tilesKey)) // crossing can either be per tile or global (aka only 1 crossing specified) private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) - private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size) + private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map ((coreType, tileParams) => + perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size)) - val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings) + // TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later + // revision, or I have to use reflection to get that parameter? + val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams) zip (rocketCrossings ++ boomCrossings ++ coreCrossings) // Make a tile and wire its nodes into the system, // according to the specified type of clock crossing. @@ -55,17 +57,22 @@ trait HasChipyardTiles extends HasTiles val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { case (param, crossing) => { - val tile = param match { - case r: RocketTileParams => { - LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - } - case b: BoomTileParams => { - LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - } - case a: ArianeTileParams => { - LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) + val tileMatch = coreAndtileParamsList => { + case (coreType, tileParams) :: tail => (param => { + case a: coreType.TileParams => { + LazyModule(new coreType.Tile(a, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode)) + } + }) orElse tileMatch(tail) + case Nil => param => { + case r: RocketTileParams => { + LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) + } + case b: BoomTileParams => { + LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) + } } } + val tile = tileMatch(CoreRegistrar.cores zip coreTileParams) connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) connectInterrupts(tile, debugOpt, clintOpt, plicOpt) diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 9fdef05a..f90e3d23 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -3,12 +3,11 @@ package chipyard import scala.collection.mutable.{LinkedHashSet} import freechips.rocketchip.subsystem.{RocketTilesKey} -import freechips.rocketchip.tile.{XLen} -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.tile.{XLen, CoreParams} +import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} import boom.common.{BoomTilesKey} -import ariane.{ArianeTilesKey} /** * A set of pre-chosen regression tests @@ -144,11 +143,11 @@ class TestSuiteHelper } /** - * Add Ariane tests (asm, bmark, regression) + * Add third-party core (including Ariane) tests (asm, bmark, regression) */ - def addArianeTestSuites(implicit p: Parameters) = { + def addThirdPartyTestSuites[TileParams <: CoreParams](tilesKey: Field[Seq[TileParams]])(implicit p: Parameters) = { val xlen = p(XLen) - p(ArianeTilesKey).find(_.hartId == 0).map { tileParams => + p(tilesKey).find(_.hartId == 0).map { tileParams => val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index fce5d432..3d367ffa 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -17,7 +17,7 @@ import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} import freechips.rocketchip.util.HasRocketChipStageUtils -import chipyard.TestSuiteHelper +import chipyard.{TestSuiteHelper, CoreRegistrar} class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase @@ -32,7 +32,7 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS val suiteHelper = new TestSuiteHelper suiteHelper.addRocketTestSuites suiteHelper.addBoomTestSuites - suiteHelper.addArianeTestSuites + CoreRegistrar.cores map suiteHelper.addThirdPartyTestSuites(_.tilesKey) // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From adb85c98caed9190abae7a927ee68fb61e5b4a33 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 21 May 2020 12:35:26 -0700 Subject: [PATCH 002/457] Some Revisions --- .../src/main/scala/ConfigFragments.scala | 21 +++++-------- .../src/main/scala/CoreRegistrar.scala | 31 ++++++++++++------- .../chipyard/src/main/scala/Subsystem.scala | 30 ++++++++---------- 3 files changed, 39 insertions(+), 43 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 3db4f326..6eca517f 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -147,21 +147,14 @@ class WithControlCore extends Config((site, here, up) => { case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) -trait TraceIOMatch { - this: CoreRegisterEntryBase => - val matchTile: (View, View, View) => PartialFunction[Field[Seq[TileParams]],Any] = ((site, here, up) => { - // TODO: XXX What's the "tile" here? - case tilesKey => up(tilesKey) map (tile => tile.copy(trace = true)) - }) -} - class WithTraceIO extends Config((site, here, up) => { - val coreMatch = (coreList: List[CoreRegisterEntryBase]) => coreList match { - case coreEntry :: tail => coreEntry.matchTile(site, here, up) orElse coreMatch(tail) - case Nil => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) - case TracePortKey => Some(TracePortParams()) + val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] = + coreList => coreList match { + case coreEntry :: tail => coreEntry.enableTileTrace(site, here, up) orElse coreMatch(tail) + case Nil => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) + } } - } coreMatch(CoreRegistrar.cores) }) diff --git a/generators/chipyard/src/main/scala/CoreRegistrar.scala b/generators/chipyard/src/main/scala/CoreRegistrar.scala index a0b1625c..b1503361 100644 --- a/generators/chipyard/src/main/scala/CoreRegistrar.scala +++ b/generators/chipyard/src/main/scala/CoreRegistrar.scala @@ -2,36 +2,43 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Parameters, Config, Field} +import freechips.rocketchip.config.{Parameters, Config, Field, View} import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams} -import freechips.rocketchip.devices.tilelink.{BootROMParams} -import freechips.rocketchip.diplomacy.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing} +import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} -import chipyard.config.TraceIOMatch - // Third-party core entries sealed trait CoreRegisterEntryBase { - type Tile - type TitleParams - def tilesKey: Field[Seq[TitleParams]] + type TileParams <: CoreParams + def tilesKey: Field[Seq[TileParams]] def crossingKey: Field[Seq[RocketCrossingParams]] + def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] + def instantiateTile(param: TileParams, crossing: RocketCrossingParams, + logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] } -class CoreRegisterEntry[TileT <: BaseTile, TileParamsT <: CoreParams](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]]) - extends CoreRegisterEntryBase with TraceIOMatch { - type Tile = TileT +class CoreRegisterEntry[TileParamsT <: CoreParams, TileT <: BaseTile](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]], + tileInstantiator: (TileParamsT, RocketCrossingParams, LookupByHartIdImpl, LogicalTreeNode, Parameters) => TileT) extends CoreRegisterEntryBase { type TileParams = TileParamsT def tilesKey = tk def crossingKey = ck + def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] = { + case in if in == tilesKey => up(this.tilesKey) map (tile => tile.copy(trace = true)) + } + def instantiateTile(param: TileParams, crossing: RocketCrossingParams, + logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] = param match { + case a: TileParams => Some(tileInstantiator(a, crossing, PriorityMuxHartIdFromSeq(p(tilesKey)), logicalTreeNode, p)) + case _ => None + } } object CoreRegistrar { val cores: List[CoreRegisterEntryBase] = List( // ADD YOUR CORE DEFINITION HERE - new CoreRegisterEntry[ArianeTile, ArianeTileParams](ArianeTilesKey, ArianeCrossingKey) + new CoreRegisterEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey, ((a, b, c, d, p) => {new ArianeTile(a, b, c, d)})) ) } \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index fcb58fc4..7b554d2a 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -40,12 +40,13 @@ trait HasChipyardTiles extends HasTiles // crossing can either be per tile or global (aka only 1 crossing specified) private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) - private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map ((coreType, tileParams) => - perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size)) + private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map (_ match { + case (coreType, tileParams) => perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size) + }) // TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later // revision, or I have to use reflection to get that parameter? - val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams) zip (rocketCrossings ++ boomCrossings ++ coreCrossings) + val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams.flatten) zip (rocketCrossings ++ boomCrossings ++ coreCrossings.flatten) // Make a tile and wire its nodes into the system, // according to the specified type of clock crossing. @@ -57,22 +58,17 @@ trait HasChipyardTiles extends HasTiles val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { case (param, crossing) => { - val tileMatch = coreAndtileParamsList => { - case (coreType, tileParams) :: tail => (param => { - case a: coreType.TileParams => { - LazyModule(new coreType.Tile(a, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode)) - } - }) orElse tileMatch(tail) - case Nil => param => { - case r: RocketTileParams => { - LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - } - case b: BoomTileParams => { - LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - } + val tile = param match { + case r: RocketTileParams => { + LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) } + case b: BoomTileParams => { + LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) + } + case _ => LazyModule( + (CoreRegistrar.cores collect (core => core.instantiateTile(param, crossing, paramList, logicalTreeNode, p)).unlift()) (0) + ) } - val tile = tileMatch(CoreRegistrar.cores zip coreTileParams) connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) connectInterrupts(tile, debugOpt, clintOpt, plicOpt) From 15c1f5adba5d6c56748573beaa32432a437338d4 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 25 May 2020 10:47:58 -0700 Subject: [PATCH 003/457] Sync works to my laptop --- .../src/main/scala/ConfigFragments.scala | 7 +++++ .../src/main/scala/CoreRegistrar.scala | 30 +++++++++++++++++-- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 6eca517f..cdf84327 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -23,6 +23,7 @@ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} import chipyard.{CoreRegistrar, CoreRegisterEntryBase} +import chipyard.hlist /** * TODO: Why do we need this? @@ -147,6 +148,12 @@ class WithControlCore extends Config((site, here, up) => { case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) +class WithTraceIOHMap extends ConfigHMap { + override def apply[I](v: I) = (site, here, up) => { + + } +} + class WithTraceIO extends Config((site, here, up) => { val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] = coreList => coreList match { diff --git a/generators/chipyard/src/main/scala/CoreRegistrar.scala b/generators/chipyard/src/main/scala/CoreRegistrar.scala index b1503361..766172d1 100644 --- a/generators/chipyard/src/main/scala/CoreRegistrar.scala +++ b/generators/chipyard/src/main/scala/CoreRegistrar.scala @@ -1,5 +1,8 @@ package chipyard +import scala.reflect.ClassTag +import scala.reflect.runtime.universe._ + import chisel3._ import freechips.rocketchip.config.{Parameters, Config, Field, View} @@ -16,16 +19,27 @@ sealed trait CoreRegisterEntryBase { type TileParams <: CoreParams def tilesKey: Field[Seq[TileParams]] def crossingKey: Field[Seq[RocketCrossingParams]] + + def findTilesWithFilter(view: View, p: Any => View): PartialFunction[Any, Seq[AnyRef]] + def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] def instantiateTile(param: TileParams, crossing: RocketCrossingParams, logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] } -class CoreRegisterEntry[TileParamsT <: CoreParams, TileT <: BaseTile](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]], - tileInstantiator: (TileParamsT, RocketCrossingParams, LookupByHartIdImpl, LogicalTreeNode, Parameters) => TileT) extends CoreRegisterEntryBase { +class CoreRegisterEntry[TileParamsT <: CoreParams, TileT <: BaseTile]( + tk: Field[Seq[TileParamsT]], + ck: Field[Seq[RocketCrossingParams]], + tileInstantiator: (TileParamsT, RocketCrossingParams, LookupByHartIdImpl, LogicalTreeNode, Parameters) => TileT +) extends CoreRegisterEntryBase { type TileParams = TileParamsT def tilesKey = tk def crossingKey = ck + + def findTilesWithFilter(view: View, p: Any => View) = { + case key if (key == tk && p(tk)) => view(tk) + } + def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] = { case in if in == tilesKey => up(this.tilesKey) map (tile => tile.copy(trace = true)) } @@ -41,4 +55,14 @@ object CoreRegistrar { // ADD YOUR CORE DEFINITION HERE new CoreRegisterEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey, ((a, b, c, d, p) => {new ArianeTile(a, b, c, d)})) ) -} \ No newline at end of file +} + +// Core Generic Config - change properties in the given map +class GenericConfig(properties: Map[String, Any], filterFunc: Any => Bool = (_ => true)) { + val configFunc: (View, View, View) => PartialFunction[Any, Any] = ((site, here, up) => key => { + val tiles = CoreRegistrar.cores flatMap _.findTilesWithFilter(up, filterFunc).lift(key) + if (tiles.size == 0) None else Some(tiles map (tile => { + val method = ClassTag(tile.getClass).member(TermName(methodName)).asMethod + })).unlift + }).unlift +} From c0bafa306c694764d3593bab8d4717023c434821 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 25 May 2020 13:22:28 -0700 Subject: [PATCH 004/457] Config Done --- .../src/main/scala/ConfigFragments.scala | 22 ++---- .../chipyard/src/main/scala/CoreManager.scala | 76 +++++++++++++++++++ .../src/main/scala/CoreRegistrar.scala | 68 ----------------- .../chipyard/src/main/scala/TestSuites.scala | 2 +- 4 files changed, 82 insertions(+), 86 deletions(-) create mode 100644 generators/chipyard/src/main/scala/CoreManager.scala delete mode 100644 generators/chipyard/src/main/scala/CoreRegistrar.scala diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index cdf84327..e87b833a 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -148,20 +148,8 @@ class WithControlCore extends Config((site, here, up) => { case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) -class WithTraceIOHMap extends ConfigHMap { - override def apply[I](v: I) = (site, here, up) => { - - } -} - -class WithTraceIO extends Config((site, here, up) => { - val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] = - coreList => coreList match { - case coreEntry :: tail => coreEntry.enableTileTrace(site, here, up) orElse coreMatch(tail) - case Nil => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) - case TracePortKey => Some(TracePortParams()) - } - } - coreMatch(CoreRegistrar.cores) -}) +class WithTraceIO extends Config((site, here, up) => + GenericConfig(Map("trace" -> true)) (site, here, up) orElse { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) + }) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala new file mode 100644 index 00000000..72c5dc85 --- /dev/null +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -0,0 +1,76 @@ +package chipyard + +import scala.reflect.ClassTag +import scala.reflect.runtime.universe._ + +import chisel3._ + +import freechips.rocketchip.config.{Parameters, Config, Field, View} +import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams} +import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode +import freechips.rocketchip.rocket._ +import freechips.rocketchip.tile._ + +import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} + +// Third-party core entries +sealed trait CoreEntryBase { + def updateWithFilter(view: View, p: Any => View): (Map[String, Any] => PartialFunction[Any, Seq[AnyRef]]) + + def instantiateTile(param: TileParams, crossing: RocketCrossingParams, + logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] +} + +class CoreEntry[TileParamsT <: CoreParams, TileT <: BaseTile]( + tk: Field[Seq[TileParamsT]], + ck: Field[Seq[RocketCrossingParams]] +) extends CoreEntryBase { + private val mirror = runtimeMirror(getClass.getClassLoader) + private val paramClass = mirror.runtimeClass(typeOf[TileParamsT].typeSymbol.asClass) + private val paramNames = Map((paramClass.getDeclaredFields map _.getName).zipWithIndex) + private val paramCtr = paramClass.getConstructors.head + + private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) + private val tileCtr = paramClass.getConstructors.head + + // copy() function in + def copyTileParam(tileParam: AnyRef, properties: Map[String, Any]) = { + val values = foo.productIterator.toList + val indexedProperties = properties map (key => (paramNames(key), properties(key))) + val newValues = (0 until values.size) map + (i => if (indexedProperties contains i) indexedProperties(i) else values(i)) + paramCtr.newInstance(newValues:_*) + } + + def updateWithFilter(view: View, p: Any => View) = { + case key if (key == tk && p(tk)) => view(tk) map + (tile => properties => copyTileParam(tile, properties)) + } + + def instantiateTile(param: TileParams, crossing: RocketCrossingParams, + logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] = param match { + case a: TileParams => Some(tileCtr.newInstance(a, crossing, PriorityMuxHartIdFromSeq(p(tilesKey)), logicalTreeNode, p)) + case _ => None + } +} + +object CoreManager { + val cores: List[CoreEntryBase] = List( + // ADD YOUR CORE DEFINITION HERE + new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey) + ) +} + +// Core Generic Config - change properties in the given map +class GenericConfig(properties: Map[String, Any], filterFunc: Any => Bool) { + val configFunc: (View, View, View) => PartialFunction[Any, Any] = ((site, here, up) => key => { + val tiles = CoreManager.cores flatMap _.updateWithFilter(up, filterFunc).lift(key) + if (tiles.size == 0) None else Some(tiles map _(properties)) + }).unlift +} + +object GenericConfig { + def apply(properties: Map[String, Any], filterFunc: Any => Bool = (_ => true)) = + new GenericConfig(properties, filterFunc).configFunc +} diff --git a/generators/chipyard/src/main/scala/CoreRegistrar.scala b/generators/chipyard/src/main/scala/CoreRegistrar.scala deleted file mode 100644 index 766172d1..00000000 --- a/generators/chipyard/src/main/scala/CoreRegistrar.scala +++ /dev/null @@ -1,68 +0,0 @@ -package chipyard - -import scala.reflect.ClassTag -import scala.reflect.runtime.universe._ - -import chisel3._ - -import freechips.rocketchip.config.{Parameters, Config, Field, View} -import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams} -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile._ - -import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} - -// Third-party core entries -sealed trait CoreRegisterEntryBase { - type TileParams <: CoreParams - def tilesKey: Field[Seq[TileParams]] - def crossingKey: Field[Seq[RocketCrossingParams]] - - def findTilesWithFilter(view: View, p: Any => View): PartialFunction[Any, Seq[AnyRef]] - - def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] - def instantiateTile(param: TileParams, crossing: RocketCrossingParams, - logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] -} - -class CoreRegisterEntry[TileParamsT <: CoreParams, TileT <: BaseTile]( - tk: Field[Seq[TileParamsT]], - ck: Field[Seq[RocketCrossingParams]], - tileInstantiator: (TileParamsT, RocketCrossingParams, LookupByHartIdImpl, LogicalTreeNode, Parameters) => TileT -) extends CoreRegisterEntryBase { - type TileParams = TileParamsT - def tilesKey = tk - def crossingKey = ck - - def findTilesWithFilter(view: View, p: Any => View) = { - case key if (key == tk && p(tk)) => view(tk) - } - - def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] = { - case in if in == tilesKey => up(this.tilesKey) map (tile => tile.copy(trace = true)) - } - def instantiateTile(param: TileParams, crossing: RocketCrossingParams, - logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] = param match { - case a: TileParams => Some(tileInstantiator(a, crossing, PriorityMuxHartIdFromSeq(p(tilesKey)), logicalTreeNode, p)) - case _ => None - } -} - -object CoreRegistrar { - val cores: List[CoreRegisterEntryBase] = List( - // ADD YOUR CORE DEFINITION HERE - new CoreRegisterEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey, ((a, b, c, d, p) => {new ArianeTile(a, b, c, d)})) - ) -} - -// Core Generic Config - change properties in the given map -class GenericConfig(properties: Map[String, Any], filterFunc: Any => Bool = (_ => true)) { - val configFunc: (View, View, View) => PartialFunction[Any, Any] = ((site, here, up) => key => { - val tiles = CoreRegistrar.cores flatMap _.findTilesWithFilter(up, filterFunc).lift(key) - if (tiles.size == 0) None else Some(tiles map (tile => { - val method = ClassTag(tile.getClass).member(TermName(methodName)).asMethod - })).unlift - }).unlift -} diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index f90e3d23..a4944355 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -147,7 +147,7 @@ class TestSuiteHelper */ def addThirdPartyTestSuites[TileParams <: CoreParams](tilesKey: Field[Seq[TileParams]])(implicit p: Parameters) = { val xlen = p(XLen) - p(tilesKey).find(_.hartId == 0).map { tileParams => + p(tilesKey).asInstanceOf[Seq[CoreParams]].find(_.hartId == 0).map { tileParams => val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") From 2edfcb9022f9904e99820477423c9ba57ec4463c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 25 May 2020 13:58:04 -0700 Subject: [PATCH 005/457] Subsystem done --- .../chipyard/src/main/scala/CoreManager.scala | 32 +++++++++-------- .../chipyard/src/main/scala/Subsystem.scala | 34 ++++++++----------- 2 files changed, 32 insertions(+), 34 deletions(-) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index 72c5dc85..39c3a678 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -17,9 +17,8 @@ import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} // Third-party core entries sealed trait CoreEntryBase { def updateWithFilter(view: View, p: Any => View): (Map[String, Any] => PartialFunction[Any, Seq[AnyRef]]) - - def instantiateTile(param: TileParams, crossing: RocketCrossingParams, - logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] + def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => ClockCrossingType) + (implicit logicalTreeNode: LogicalTreeNode, p: Parameters): (CoreParams, ClockCrossingType, BaseTile) } class CoreEntry[TileParamsT <: CoreParams, TileT <: BaseTile]( @@ -48,20 +47,18 @@ class CoreEntry[TileParamsT <: CoreParams, TileT <: BaseTile]( (tile => properties => copyTileParam(tile, properties)) } - def instantiateTile(param: TileParams, crossing: RocketCrossingParams, - logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] = param match { - case a: TileParams => Some(tileCtr.newInstance(a, crossing, PriorityMuxHartIdFromSeq(p(tilesKey)), logicalTreeNode, p)) - case _ => None + def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => ClockCrossingType) + (implicit logicalTreeNode: LogicalTreeNode, p: Parameters) = { + val tileParams = p(tk) + val crossings = crossingLookup(p(ck), tileParams.size) + (tileParams zip crossings) map ((param, crossing) => ( + param, + crossing, + LazyModule(tileCtr(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode)) + )) } } -object CoreManager { - val cores: List[CoreEntryBase] = List( - // ADD YOUR CORE DEFINITION HERE - new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey) - ) -} - // Core Generic Config - change properties in the given map class GenericConfig(properties: Map[String, Any], filterFunc: Any => Bool) { val configFunc: (View, View, View) => PartialFunction[Any, Any] = ((site, here, up) => key => { @@ -74,3 +71,10 @@ object GenericConfig { def apply(properties: Map[String, Any], filterFunc: Any => Bool = (_ => true)) = new GenericConfig(properties, filterFunc).configFunc } + +object CoreManager { + val cores: List[CoreEntryBase] = List( + // ADD YOUR CORE DEFINITION HERE + new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey) + ) +} diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 7b554d2a..c7924c9a 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -35,18 +35,25 @@ trait HasChipyardTiles extends HasTiles protected val rocketTileParams = p(RocketTilesKey) protected val boomTileParams = p(BoomTilesKey) - protected val coreTileParams = CoreRegistrar.cores map (coreType => p(coreType.tilesKey)) // crossing can either be per tile or global (aka only 1 crossing specified) private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) - private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map (_ match { - case (coreType, tileParams) => perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size) - }) - // TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later + private val rocketTilesInfo = (rocketTileParams zip rocketCrossings) map ((param, crossing) => ( + param, + crossing, + LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) + )) + private val boomTilesInfo = (boomTileParams zip boomCrossings) map ((param, crossing) => ( + param, + crossing, + LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(boomCrossings), logicalTreeNode)) + )) + + // TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later // revision, or I have to use reflection to get that parameter? - val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams.flatten) zip (rocketCrossings ++ boomCrossings ++ coreCrossings.flatten) + val allTilesInfo = rocketTilesInfo ++ boomTilesInfo ++ (CoreManager.cores map _.instantiateTile(perTileOrGlobalSetting _)) // Make a tile and wire its nodes into the system, // according to the specified type of clock crossing. @@ -56,19 +63,7 @@ trait HasChipyardTiles extends HasTiles // There is something weird with registering tile-local interrupt controllers to the CLINT. // TODO: investigate why val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { - case (param, crossing) => { - - val tile = param match { - case r: RocketTileParams => { - LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - } - case b: BoomTileParams => { - LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - } - case _ => LazyModule( - (CoreRegistrar.cores collect (core => core.instantiateTile(param, crossing, paramList, logicalTreeNode, p)).unlift()) (0) - ) - } + case (param, crossing, tile) => { connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) connectInterrupts(tile, debugOpt, clintOpt, plicOpt) @@ -77,7 +72,6 @@ trait HasChipyardTiles extends HasTiles } } - def coreMonitorBundles = tiles.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle From a120edd36431edf382a7a5f22728420357e9c8f9 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 25 May 2020 21:50:44 -0700 Subject: [PATCH 006/457] Pass Scala Compilation --- .../src/main/scala/ConfigFragments.scala | 3 +- .../chipyard/src/main/scala/CoreManager.scala | 57 ++++++++++--------- .../chipyard/src/main/scala/Subsystem.scala | 29 +++++----- .../chipyard/src/main/scala/TestSuites.scala | 6 +- .../scala/stage/phases/AddDefaultTests.scala | 4 +- 5 files changed, 53 insertions(+), 46 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index e87b833a..697dc4ec 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -22,8 +22,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} -import chipyard.{CoreRegistrar, CoreRegisterEntryBase} -import chipyard.hlist +import chipyard.GenericConfig /** * TODO: Why do we need this? diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index 39c3a678..d92f839c 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -7,7 +7,7 @@ import chisel3._ import freechips.rocketchip.config.{Parameters, Config, Field, View} import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams} -import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ @@ -16,59 +16,64 @@ import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} // Third-party core entries sealed trait CoreEntryBase { - def updateWithFilter(view: View, p: Any => View): (Map[String, Any] => PartialFunction[Any, Seq[AnyRef]]) - def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => ClockCrossingType) - (implicit logicalTreeNode: LogicalTreeNode, p: Parameters): (CoreParams, ClockCrossingType, BaseTile) + def tileParamsLookup(implicit p: Parameters): Seq[TileParams] + def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] + def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) + (implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, BaseTile)] } -class CoreEntry[TileParamsT <: CoreParams, TileT <: BaseTile]( +class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTile : TypeTag]( tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]] ) extends CoreEntryBase { private val mirror = runtimeMirror(getClass.getClassLoader) private val paramClass = mirror.runtimeClass(typeOf[TileParamsT].typeSymbol.asClass) - private val paramNames = Map((paramClass.getDeclaredFields map _.getName).zipWithIndex) + private val paramNames = (paramClass.getDeclaredFields map (f => f.getName)).zipWithIndex.toMap private val paramCtr = paramClass.getConstructors.head private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) private val tileCtr = paramClass.getConstructors.head // copy() function in - def copyTileParam(tileParam: AnyRef, properties: Map[String, Any]) = { - val values = foo.productIterator.toList - val indexedProperties = properties map (key => (paramNames(key), properties(key))) + def copyTileParam(tileParam: TileParamsT, properties: Map[String, Any]) = { + val values = tileParam.productIterator.toList + val indexedProperties = properties map { case (key, value) => (paramNames(key), value) } val newValues = (0 until values.size) map - (i => if (indexedProperties contains i) indexedProperties(i) else values(i)) + (i => (if (indexedProperties contains i) indexedProperties(i) else values(i)).asInstanceOf[AnyRef]) paramCtr.newInstance(newValues:_*) } - def updateWithFilter(view: View, p: Any => View) = { - case key if (key == tk && p(tk)) => view(tk) map - (tile => properties => copyTileParam(tile, properties)) + def tileParamsLookup(implicit p: Parameters) = p(tk) + + def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] = { + case key if (key == tk && p(tk)) => properties => view(tk) map + (tile => copyTileParam(tile, properties)) } - def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => ClockCrossingType) - (implicit logicalTreeNode: LogicalTreeNode, p: Parameters) = { + def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) + (implicit p: Parameters, valName: ValName) = { val tileParams = p(tk) val crossings = crossingLookup(p(ck), tileParams.size) - (tileParams zip crossings) map ((param, crossing) => ( - param, - crossing, - LazyModule(tileCtr(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode)) - )) + (tileParams zip crossings) map { + case (param, crossing) => ( + param, + crossing, + LazyModule(tileCtr.newInstance(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode).asInstanceOf[TileT]) + ) + } } } // Core Generic Config - change properties in the given map -class GenericConfig(properties: Map[String, Any], filterFunc: Any => Bool) { - val configFunc: (View, View, View) => PartialFunction[Any, Any] = ((site, here, up) => key => { - val tiles = CoreManager.cores flatMap _.updateWithFilter(up, filterFunc).lift(key) - if (tiles.size == 0) None else Some(tiles map _(properties)) - }).unlift +class GenericConfig(properties: Map[String, Any], filterFunc: Any => Boolean) { + val configFunc: (View, View, View) => PartialFunction[Any, Any] = (site, here, up) => scala.Function.unlift((key: Any) => { + val tiles = CoreManager.cores flatMap (core => core.updateWithFilter(up, filterFunc).lift(key)) + if (tiles.size == 0) None else Some(tiles map (tile => tile(properties))) + }) } object GenericConfig { - def apply(properties: Map[String, Any], filterFunc: Any => Bool = (_ => true)) = + def apply(properties: Map[String, Any], filterFunc: Any => Boolean = (_ => true)) = new GenericConfig(properties, filterFunc).configFunc } diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index c7924c9a..1b766099 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -40,20 +40,23 @@ trait HasChipyardTiles extends HasTiles private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) - private val rocketTilesInfo = (rocketTileParams zip rocketCrossings) map ((param, crossing) => ( - param, - crossing, - LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - )) - private val boomTilesInfo = (boomTileParams zip boomCrossings) map ((param, crossing) => ( - param, - crossing, - LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(boomCrossings), logicalTreeNode)) - )) + private val rocketTilesInfo = (rocketTileParams zip rocketCrossings) map { + case (param, crossing) => ( + param, + crossing, + LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) + ) + } + private val boomTilesInfo = (boomTileParams zip boomCrossings) map { + case (param, crossing) => ( + param, + crossing, + LazyModule(new BoomTile(param, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) + ) + } - // TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later - // revision, or I have to use reflection to get that parameter? - val allTilesInfo = rocketTilesInfo ++ boomTilesInfo ++ (CoreManager.cores map _.instantiateTile(perTileOrGlobalSetting _)) + val allTilesInfo = rocketTilesInfo ++ boomTilesInfo ++ + (CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode))) // Make a tile and wire its nodes into the system, // according to the specified type of clock crossing. diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index a4944355..9041be61 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -3,7 +3,7 @@ package chipyard import scala.collection.mutable.{LinkedHashSet} import freechips.rocketchip.subsystem.{RocketTilesKey} -import freechips.rocketchip.tile.{XLen, CoreParams} +import freechips.rocketchip.tile.{XLen, TileParams} import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} @@ -145,9 +145,9 @@ class TestSuiteHelper /** * Add third-party core (including Ariane) tests (asm, bmark, regression) */ - def addThirdPartyTestSuites[TileParams <: CoreParams](tilesKey: Field[Seq[TileParams]])(implicit p: Parameters) = { + def addThirdPartyTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = { val xlen = p(XLen) - p(tilesKey).asInstanceOf[Seq[CoreParams]].find(_.hartId == 0).map { tileParams => + tiles.find(_.hartId == 0).map { tileParams => val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 3d367ffa..cbd2e1a7 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -17,7 +17,7 @@ import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} import freechips.rocketchip.util.HasRocketChipStageUtils -import chipyard.{TestSuiteHelper, CoreRegistrar} +import chipyard.{TestSuiteHelper, CoreManager} class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase @@ -32,7 +32,7 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS val suiteHelper = new TestSuiteHelper suiteHelper.addRocketTestSuites suiteHelper.addBoomTestSuites - CoreRegistrar.cores map suiteHelper.addThirdPartyTestSuites(_.tilesKey) + CoreManager.cores map (core => suiteHelper.addThirdPartyTestSuites(core.tileParamsLookup)) // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From 48ba92dff1069a1de8f57caca3330d3059a3e26c Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 28 May 2020 12:34:17 -0700 Subject: [PATCH 007/457] Disable all make suffix rules for improved EC2 performance --- common.mk | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common.mk b/common.mk index f07342de..8ef08f73 100644 --- a/common.mk +++ b/common.mk @@ -189,3 +189,10 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) + +######################################################################################### +# Implicit rule handling +######################################################################################### +# Disable all suffix rules to improve Make performance on systems running older +# versions of Make +.SUFFIXES: From 8f39791d940e748d0a25c06a957b0b9fd40e275c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 28 May 2020 22:46:13 -0700 Subject: [PATCH 008/457] Git ignores vscode and scala plugins --- .gitignore | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.gitignore b/.gitignore index 47cb4d87..eaddd6e1 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,10 @@ target *# *~ .idea +.bloop +.metals +project/metals.sbt +.vscode .DS_Store env.sh riscv-tools-install From 71bac7b7c9f28a47662c2334914faaf8606744a9 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 29 May 2020 20:23:53 -0700 Subject: [PATCH 009/457] Fixed runtime error --- generators/chipyard/src/main/scala/CoreManager.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index d92f839c..22212795 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -13,8 +13,9 @@ import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} +import chipsalliance.rocketchip.config.Parameters -// Third-party core entries +// Base trait for all third-party core entries sealed trait CoreEntryBase { def tileParamsLookup(implicit p: Parameters): Seq[TileParams] def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] @@ -22,6 +23,7 @@ sealed trait CoreEntryBase { (implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, BaseTile)] } +// Implementation of third-party core entries class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTile : TypeTag]( tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]] @@ -32,9 +34,9 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi private val paramCtr = paramClass.getConstructors.head private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) - private val tileCtr = paramClass.getConstructors.head + private val tileCtr = tileClass.getConstructors.head - // copy() function in + // Reflective version of copy() def copyTileParam(tileParam: TileParamsT, properties: Map[String, Any]) = { val values = tileParam.productIterator.toList val indexedProperties = properties map { case (key, value) => (paramNames(key), value) } @@ -58,7 +60,7 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi case (param, crossing) => ( param, crossing, - LazyModule(tileCtr.newInstance(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode).asInstanceOf[TileT]) + LazyModule(tileCtr.newInstance(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode, p.asInstanceOf[Parameters]).asInstanceOf[TileT]) ) } } From 3fcfc133b1a4e1840ca7f6cd08fd5eb43938aaab Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 31 May 2020 10:51:11 -0700 Subject: [PATCH 010/457] Add Rocket and Boom to CoreManager --- .../src/main/scala/ConfigFragments.scala | 6 +- .../chipyard/src/main/scala/CoreManager.scala | 7 +- .../chipyard/src/main/scala/Subsystem.scala | 24 +----- .../chipyard/src/main/scala/TestSuites.scala | 81 +------------------ .../scala/stage/phases/AddDefaultTests.scala | 5 +- 5 files changed, 12 insertions(+), 111 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 697dc4ec..dfe225e4 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -148,7 +148,9 @@ class WithControlCore extends Config((site, here, up) => { }) class WithTraceIO extends Config((site, here, up) => - GenericConfig(Map("trace" -> true)) (site, here, up) orElse { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + GenericConfig(Map("trace" -> true), { + case RocketTilesKey => false + case _ => true + }) (site, here, up) orElse { case TracePortKey => Some(TracePortParams()) }) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index 22212795..ec467d8f 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -6,12 +6,13 @@ import scala.reflect.runtime.universe._ import chisel3._ import freechips.rocketchip.config.{Parameters, Config, Field, View} -import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams} +import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams, RocketCrossingKey} import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ +import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} import chipsalliance.rocketchip.config.Parameters @@ -34,7 +35,7 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi private val paramCtr = paramClass.getConstructors.head private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) - private val tileCtr = tileClass.getConstructors.head + private val tileCtr = tileClass.getConstructors.filter(ctr => ctr.getParameterTypes()(4) == classOf[Parameters]).head // Reflective version of copy() def copyTileParam(tileParam: TileParamsT, properties: Map[String, Any]) = { @@ -82,6 +83,8 @@ object GenericConfig { object CoreManager { val cores: List[CoreEntryBase] = List( // ADD YOUR CORE DEFINITION HERE + new CoreEntry[RocketTileParams, RocketTile](RocketTilesKey, RocketCrossingKey), + new CoreEntry[BoomTileParams, BoomTile](BoomTilesKey, BoomCrossingKey), new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey) ) } diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 1b766099..889e5f6f 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -33,29 +33,7 @@ trait HasChipyardTiles extends HasTiles val module: HasChipyardTilesModuleImp - protected val rocketTileParams = p(RocketTilesKey) - protected val boomTileParams = p(BoomTilesKey) - - // crossing can either be per tile or global (aka only 1 crossing specified) - private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) - private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) - - private val rocketTilesInfo = (rocketTileParams zip rocketCrossings) map { - case (param, crossing) => ( - param, - crossing, - LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - ) - } - private val boomTilesInfo = (boomTileParams zip boomCrossings) map { - case (param, crossing) => ( - param, - crossing, - LazyModule(new BoomTile(param, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - ) - } - - val allTilesInfo = rocketTilesInfo ++ boomTilesInfo ++ + val allTilesInfo: Seq[(TileParams, RocketCrossingParams, BaseTile)] = (CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode))) // Make a tile and wire its nodes into the system, diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 9041be61..6fba4b2a 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -62,86 +62,6 @@ class TestSuiteHelper def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) } def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) } - /** - * Add BOOM tests (asm, bmark, regression) - */ - def addBoomTestSuites(implicit p: Parameters) = { - val xlen = p(XLen) - p(BoomTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) { - addSuites(env.map(rv32ud)) - } - } else if (cfg.fLen >= 64) { - addSuites(env.map(rv64ud)) - addSuites(env.map(rv64uf)) - addSuite(rv32udBenchmarks) - } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) { - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - } else { - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) - - addSuites(rvi.map(_("p"))) - addSuites(rvu.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) - } - } - - /** - * Add Rocket tests (asm, bmark, regression) - */ - def addRocketTestSuites(implicit p: Parameters) = { - val xlen = p(XLen) - p(RocketTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv32ud)) - } else { - addSuite(rv32udBenchmarks) - addSuites(env.map(rv64uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv64ud)) - } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - else - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) - - addSuites(rvi.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) - } - } - /** * Add third-party core (including Ariane) tests (asm, bmark, regression) */ @@ -175,6 +95,7 @@ class TestSuiteHelper else ((if (vm) rv32i else rv32pi), rv32u) addSuites(rvi.map(_("p"))) + addSuites(rvu.map(_("p"))) addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) addSuite(benchmarks) addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 464c8ff5..f8ae3177 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -33,11 +33,8 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS val suiteHelper = new TestSuiteHelper // Use Xlen as a proxy for detecting if we are a processor-like target // The underlying test suites expect this field to be defined - if (p.lift(XLen).nonEmpty) { - suiteHelper.addRocketTestSuites - suiteHelper.addBoomTestSuites + if (p.lift(XLen).nonEmpty) CoreManager.cores map (core => suiteHelper.addThirdPartyTestSuites(core.tileParamsLookup)) - } // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From 0743abd9db6446f5194c6dc5f4425a2d93794c80 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 31 May 2020 15:09:22 -0700 Subject: [PATCH 011/457] Add comments --- generators/chipyard/src/main/scala/CoreManager.scala | 11 +++++++++-- generators/chipyard/src/main/scala/Subsystem.scala | 3 ++- generators/chipyard/src/main/scala/TestSuites.scala | 4 ++-- .../src/main/scala/stage/phases/AddDefaultTests.scala | 4 ++-- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index ec467d8f..ecee820f 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -29,15 +29,17 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]] ) extends CoreEntryBase { + // Use reflection to get the parameter's constructor private val mirror = runtimeMirror(getClass.getClassLoader) private val paramClass = mirror.runtimeClass(typeOf[TileParamsT].typeSymbol.asClass) private val paramNames = (paramClass.getDeclaredFields map (f => f.getName)).zipWithIndex.toMap private val paramCtr = paramClass.getConstructors.head + // Use reflection to get the tile's constructor private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) private val tileCtr = tileClass.getConstructors.filter(ctr => ctr.getParameterTypes()(4) == classOf[Parameters]).head - // Reflective version of copy() + // Version of case class' copy() using reflection, where fields to be updated are passed by a map def copyTileParam(tileParam: TileParamsT, properties: Map[String, Any]) = { val values = tileParam.productIterator.toList val indexedProperties = properties map { case (key, value) => (paramNames(key), value) } @@ -46,13 +48,16 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi paramCtr.newInstance(newValues:_*) } + // Tile parameter lookup using correct type def tileParamsLookup(implicit p: Parameters) = p(tk) + // If this core meet the requirement given by p, update parameter fields in the map def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] = { case key if (key == tk && p(tk)) => properties => view(tk) map (tile => copyTileParam(tile, properties)) } + // Instantiate a tile and zip it with its parameter info, used by subsystem def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) (implicit p: Parameters, valName: ValName) = { val tileParams = p(tk) @@ -75,14 +80,16 @@ class GenericConfig(properties: Map[String, Any], filterFunc: Any => Boolean) { }) } +// Wrapper object of the class above object GenericConfig { def apply(properties: Map[String, Any], filterFunc: Any => Boolean = (_ => true)) = new GenericConfig(properties, filterFunc).configFunc } +// A list of all cores. object CoreManager { val cores: List[CoreEntryBase] = List( - // ADD YOUR CORE DEFINITION HERE + // TODO ADD YOUR CORE DEFINITION HERE new CoreEntry[RocketTileParams, RocketTile](RocketTilesKey, RocketCrossingKey), new CoreEntry[BoomTileParams, BoomTile](BoomTilesKey, BoomCrossingKey), new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 889e5f6f..6410ac4e 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -33,7 +33,8 @@ trait HasChipyardTiles extends HasTiles val module: HasChipyardTilesModuleImp - val allTilesInfo: Seq[(TileParams, RocketCrossingParams, BaseTile)] = + // Generate tiles info from the list of cores in CoreManager + val allTilesInfo: Seq[(TileParams, RocketCrossingParams, BaseTile)] = (CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode))) // Make a tile and wire its nodes into the system, diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 6fba4b2a..2261000f 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -63,9 +63,9 @@ class TestSuiteHelper def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) } /** - * Add third-party core (including Ariane) tests (asm, bmark, regression) + * Add generic tests (asm, bmark, regression) for all cores. */ - def addThirdPartyTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = { + def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = { val xlen = p(XLen) tiles.find(_.hartId == 0).map { tileParams => val coreParams = tileParams.core diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index f8ae3177..a36131b1 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -22,7 +22,7 @@ import chipyard.{TestSuiteHelper, CoreManager} class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase - // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). + // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). override val prerequisites = Seq( Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], Dependency[freechips.rocketchip.stage.phases.AddDefaultTests]) @@ -34,7 +34,7 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS // Use Xlen as a proxy for detecting if we are a processor-like target // The underlying test suites expect this field to be defined if (p.lift(XLen).nonEmpty) - CoreManager.cores map (core => suiteHelper.addThirdPartyTestSuites(core.tileParamsLookup)) + CoreManager.cores map (core => suiteHelper.addGenericTestSuites(core.tileParamsLookup)) // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From aa606e580a60515fdc375c30b9ace5b074efd8fc Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 1 Jun 2020 18:41:21 -0700 Subject: [PATCH 012/457] Change names --- .../src/main/scala/ConfigFragments.scala | 13 +++--- .../chipyard/src/main/scala/CoreManager.scala | 46 ++++++++++--------- 2 files changed, 30 insertions(+), 29 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index dfe225e4..cad47f72 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -22,7 +22,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} -import chipyard.GenericConfig +import chipyard.GenericCoreConfig /** * TODO: Why do we need this? @@ -147,10 +147,9 @@ class WithControlCore extends Config((site, here, up) => { case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) -class WithTraceIO extends Config((site, here, up) => - GenericConfig(Map("trace" -> true), { - case RocketTilesKey => false - case _ => true - }) (site, here, up) orElse { +class WithTraceIO extends GenericCoreConfig( + properties = Map("trace" -> true), + specialCase = (site, here, up) => { case TracePortKey => Some(TracePortParams()) - }) + } +) \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index ecee820f..2756a42b 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -26,65 +26,67 @@ sealed trait CoreEntryBase { // Implementation of third-party core entries class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTile : TypeTag]( - tk: Field[Seq[TileParamsT]], - ck: Field[Seq[RocketCrossingParams]] + tilesKey: Field[Seq[TileParamsT]], + crossingKey: Field[Seq[RocketCrossingParams]] ) extends CoreEntryBase { // Use reflection to get the parameter's constructor private val mirror = runtimeMirror(getClass.getClassLoader) private val paramClass = mirror.runtimeClass(typeOf[TileParamsT].typeSymbol.asClass) private val paramNames = (paramClass.getDeclaredFields map (f => f.getName)).zipWithIndex.toMap - private val paramCtr = paramClass.getConstructors.head + private val paramCtor = paramClass.getConstructors.head // Use reflection to get the tile's constructor private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) - private val tileCtr = tileClass.getConstructors.filter(ctr => ctr.getParameterTypes()(4) == classOf[Parameters]).head + private val tileCtor = tileClass.getConstructors.filter(ctor => ctor.getParameterTypes()(4) == classOf[Parameters]).head // Version of case class' copy() using reflection, where fields to be updated are passed by a map def copyTileParam(tileParam: TileParamsT, properties: Map[String, Any]) = { val values = tileParam.productIterator.toList - val indexedProperties = properties map { case (key, value) => (paramNames(key), value) } + //val filteredProperties = properties filter { case (key, value) => paramNames contains key } + val indexedProperties = /*filteredProperties*/ properties map { case (key, value) => (paramNames(key), value) } val newValues = (0 until values.size) map (i => (if (indexedProperties contains i) indexedProperties(i) else values(i)).asInstanceOf[AnyRef]) - paramCtr.newInstance(newValues:_*) + paramCtor.newInstance(newValues:_*) } // Tile parameter lookup using correct type - def tileParamsLookup(implicit p: Parameters) = p(tk) + def tileParamsLookup(implicit p: Parameters) = p(tilesKey) // If this core meet the requirement given by p, update parameter fields in the map def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] = { - case key if (key == tk && p(tk)) => properties => view(tk) map + case key if (key == tilesKey && p(tilesKey)) => properties => view(tilesKey) map (tile => copyTileParam(tile, properties)) } // Instantiate a tile and zip it with its parameter info, used by subsystem def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) (implicit p: Parameters, valName: ValName) = { - val tileParams = p(tk) - val crossings = crossingLookup(p(ck), tileParams.size) + val tileParams = p(tilesKey) + val crossings = crossingLookup(p(crossingKey), tileParams.size) (tileParams zip crossings) map { case (param, crossing) => ( param, crossing, - LazyModule(tileCtr.newInstance(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode, p.asInstanceOf[Parameters]).asInstanceOf[TileT]) + LazyModule(tileCtor.newInstance(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode, p.asInstanceOf[Parameters]).asInstanceOf[TileT]) ) } } } -// Core Generic Config - change properties in the given map -class GenericConfig(properties: Map[String, Any], filterFunc: Any => Boolean) { - val configFunc: (View, View, View) => PartialFunction[Any, Any] = (site, here, up) => scala.Function.unlift((key: Any) => { +// Generic Core Config - change properties in the given map +class GenericCoreConfig( + // Parameter properties to be changed and their new values. Any field not in a core's parameters will be ignored. + properties: Map[String, Any], + // Function for filtering the list of TilesKey. + filterFunc: Any => Boolean = (_ => true), + // Handling special cases where partial function input is not a TilesKey. + specialCase: (View, View, View) => PartialFunction[Any, Any] = ((_, _, _) => Map.empty) +) extends Config((site, here, up) => + scala.Function.unlift((key: Any) => { val tiles = CoreManager.cores flatMap (core => core.updateWithFilter(up, filterFunc).lift(key)) if (tiles.size == 0) None else Some(tiles map (tile => tile(properties))) - }) -} - -// Wrapper object of the class above -object GenericConfig { - def apply(properties: Map[String, Any], filterFunc: Any => Boolean = (_ => true)) = - new GenericConfig(properties, filterFunc).configFunc -} + }).orElse(specialCase(site, here, up)) +) // A list of all cores. object CoreManager { From f9faac32fc06b9c823bd7ee388b48f24a769fb53 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 3 Jun 2020 17:19:42 -0700 Subject: [PATCH 013/457] [skip ci] Update reference to 'REBAR' in script comment --- scripts/firesim-setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index 959777d7..bb14f39e 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash -# Sets up FireSim for use as a library within REBAR +# Sets up FireSim for use as a library within Chipyard set -e set -o pipefail From 02c8aac346df1f889fa7d4810a76b3db2daedd67 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 3 Jun 2020 20:22:41 -0700 Subject: [PATCH 014/457] Revised generic config --- .../src/main/scala/ConfigFragments.scala | 11 +- .../chipyard/src/main/scala/CoreManager.scala | 47 ++----- .../src/main/scala/GenericCoreConfig.scala | 133 ++++++++++++++++++ .../scala/stage/phases/AddDefaultTests.scala | 11 +- 4 files changed, 153 insertions(+), 49 deletions(-) create mode 100644 generators/chipyard/src/main/scala/GenericCoreConfig.scala diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index cad47f72..4d0e0725 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -59,14 +59,7 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) }) -class WithL2TLBs(entries: Int) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) -}) +class WithL2TLBs(entries: Int) extends GenericCoreConfig(Map("core" -> Map("nL2TLBEntries" -> entries))) class WithTracegenSystem extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) @@ -148,7 +141,7 @@ class WithControlCore extends Config((site, here, up) => { }) class WithTraceIO extends GenericCoreConfig( - properties = Map("trace" -> true), + newValues = Map("trace" -> true), specialCase = (site, here, up) => { case TracePortKey => Some(TracePortParams()) } diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index 2756a42b..57b63743 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -14,10 +14,10 @@ import freechips.rocketchip.tile._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} -import chipsalliance.rocketchip.config.Parameters // Base trait for all third-party core entries sealed trait CoreEntryBase { + val name: String def tileParamsLookup(implicit p: Parameters): Seq[TileParams] def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) @@ -26,36 +26,22 @@ sealed trait CoreEntryBase { // Implementation of third-party core entries class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTile : TypeTag]( + val name: String, tilesKey: Field[Seq[TileParamsT]], crossingKey: Field[Seq[RocketCrossingParams]] ) extends CoreEntryBase { - // Use reflection to get the parameter's constructor - private val mirror = runtimeMirror(getClass.getClassLoader) - private val paramClass = mirror.runtimeClass(typeOf[TileParamsT].typeSymbol.asClass) - private val paramNames = (paramClass.getDeclaredFields map (f => f.getName)).zipWithIndex.toMap - private val paramCtor = paramClass.getConstructors.head - // Use reflection to get the tile's constructor + private val mirror = runtimeMirror(getClass.getClassLoader) private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) private val tileCtor = tileClass.getConstructors.filter(ctor => ctor.getParameterTypes()(4) == classOf[Parameters]).head - // Version of case class' copy() using reflection, where fields to be updated are passed by a map - def copyTileParam(tileParam: TileParamsT, properties: Map[String, Any]) = { - val values = tileParam.productIterator.toList - //val filteredProperties = properties filter { case (key, value) => paramNames contains key } - val indexedProperties = /*filteredProperties*/ properties map { case (key, value) => (paramNames(key), value) } - val newValues = (0 until values.size) map - (i => (if (indexedProperties contains i) indexedProperties(i) else values(i)).asInstanceOf[AnyRef]) - paramCtor.newInstance(newValues:_*) - } - // Tile parameter lookup using correct type def tileParamsLookup(implicit p: Parameters) = p(tilesKey) // If this core meet the requirement given by p, update parameter fields in the map def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] = { - case key if (key == tilesKey && p(tilesKey)) => properties => view(tilesKey) map - (tile => copyTileParam(tile, properties)) + case key if (key == tilesKey && p(tilesKey)) => newValues => view(tilesKey) map + (tile => CopyParam(tile, newValues)) } // Instantiate a tile and zip it with its parameter info, used by subsystem @@ -73,27 +59,12 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi } } -// Generic Core Config - change properties in the given map -class GenericCoreConfig( - // Parameter properties to be changed and their new values. Any field not in a core's parameters will be ignored. - properties: Map[String, Any], - // Function for filtering the list of TilesKey. - filterFunc: Any => Boolean = (_ => true), - // Handling special cases where partial function input is not a TilesKey. - specialCase: (View, View, View) => PartialFunction[Any, Any] = ((_, _, _) => Map.empty) -) extends Config((site, here, up) => - scala.Function.unlift((key: Any) => { - val tiles = CoreManager.cores flatMap (core => core.updateWithFilter(up, filterFunc).lift(key)) - if (tiles.size == 0) None else Some(tiles map (tile => tile(properties))) - }).orElse(specialCase(site, here, up)) -) - // A list of all cores. object CoreManager { val cores: List[CoreEntryBase] = List( - // TODO ADD YOUR CORE DEFINITION HERE - new CoreEntry[RocketTileParams, RocketTile](RocketTilesKey, RocketCrossingKey), - new CoreEntry[BoomTileParams, BoomTile](BoomTilesKey, BoomCrossingKey), - new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey) + // TODO ADD YOUR CORE DEFINITION HERE; note that the + new CoreEntry[RocketTileParams, RocketTile]("Rocket", RocketTilesKey, RocketCrossingKey), + new CoreEntry[BoomTileParams, BoomTile]("Boom", BoomTilesKey, BoomCrossingKey), + new CoreEntry[ArianeTileParams, ArianeTile]("Ariane", ArianeTilesKey, ArianeCrossingKey) ) } diff --git a/generators/chipyard/src/main/scala/GenericCoreConfig.scala b/generators/chipyard/src/main/scala/GenericCoreConfig.scala new file mode 100644 index 00000000..ac099742 --- /dev/null +++ b/generators/chipyard/src/main/scala/GenericCoreConfig.scala @@ -0,0 +1,133 @@ +package chipyard + +import scala.reflect.ClassTag +import scala.reflect.runtime.universe._ + +import chisel3._ + +import freechips.rocketchip.config.{Parameters, Config, Field, View} +import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams, RocketCrossingKey} +import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName} +import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode +import freechips.rocketchip.rocket._ +import freechips.rocketchip.tile._ + +import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} +import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} + +// Extractor object accompanied class +// This is used to check the convertibility for those wrapped in Option, since Option's type is erased at runtime. +trait SubParameterBase { + def toProduct: Product + def cast(p: Any): Any +} +final class SubParameter[T <: Product](param: T) extends SubParameterBase { + def toProduct: Product = param + def cast(p: Any) = p.asInstanceOf[T] +} + +// Extractor object that help identify the parameter case classes. +// Add your customized nested parameter classes (or their commom base classes) here. +object CustomizedSubParameter { + def unapply(param: Product): Option[Product] = param match { + // ADD YOUR NESTED PARAMETER CLASS HERE, in the format shown below in SubParameter + case _ => None + } +} + +// Standard nested +object SubParameter { + def unapply(param: Product): Option[SubParameterBase] = param match { + case p: TileParams => Some(new SubParameter(p)) + case p: CoreParams => Some(new SubParameter(p)) + case p: ICacheParams => Some(new SubParameter(p)) + case p: DCacheParams => Some(new SubParameter(p)) + case p: MulDivParams => Some(new SubParameter(p)) + case p: FPUParams => Some(new SubParameter(p)) + case p: BTBParams => Some(new SubParameter(p)) + case p: BHTParams => Some(new SubParameter(p)) + case CustomizedSubParameter(p) => Some(new SubParameter(p)) + case _ => None + } +} + +// Dynamic update helper for Parameter class. +class CopyParam(paramExtracted: SubParameterBase) { + // Constructor for corresponding TileParams + private val param: Product = paramExtracted.toProduct + private val paramClass = param.getClass + private val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) + private val paramCtor = paramClass.getConstructors.head + + // Function to build value entry + private def buildEntry(value: Any): Any = value match { + case Some(v) => Some(buildEntry(v)) + case SubParameter(p) => new CopyParam(p) + case v => v + } + + // Value of the case class + private val entries = param.productIterator.toList map (v => buildEntry(v)) + + // Update one value entry + private def updateEntry(entry: Any, newValue: Any): Any = entry match { + case Some(e) => newValue match { + case Some(v) => Some(updateEntry(e, v)) + case None => None + } + case e: CopyParam => newValue match { + case newValues: Map[String, Any] => e.update(newValues) + case v => paramExtracted.cast(v) + } + // Use cast() to check the type of the new value. Here I assume that all entries in the parameters class are simple values + // (like Int, BigInt and String), which are all final. This may breaks if a polymorphic type is added (unless it's a case + // class and registered above). + case e => e.getClass.cast(newValue) + } + + // Update the entire parameter object. + def update(newValues: Map[String, Any]): Any = { + val filteredValues = newValues.filter({ case (key, value) => paramNames contains key }) + val newValueList = entries.zipWithIndex map { + case (value, i) if newValues contains paramNames(i) => updateEntry(value, filteredValues(paramNames(i))).asInstanceOf[AnyRef] + case (value, i) => (value match { + case Some(v) => v match { + case copyParam: CopyParam => Some(copyParam.param) + case _ => Some(v) + } + case copyParam: CopyParam => copyParam.param + case _ => value + }).asInstanceOf[AnyRef] + } + paramCtor.newInstance(newValueList:_*) + } + + // For debug purpose - print what's in the object + override def toString(): String = paramClass.getSimpleName + "(" + entries.toString + ")" +} + +object CopyParam { + def apply(param: Product, newValues: Map[String, Any]): Any = param match { + case SubParameter(p) => new CopyParam(p).update(newValues) + case _ => throw new Exception("param is not a known Parameter type: add your custom parameter class to GenericCoreConfig.scala to fix it") + } +} + +// Change parameters for all registered cores in CoreManager. +class GenericCoreConfig ( + // Key-value pairs to be updated (keys are the name of fields). Any field not in a core's parameters will be ignored. + // If a field is a case class containing parameters (or an Option of that), you can use another Map containing the key-value pairs to + // update that case class. Using a new case class instance as the value is also acceptable. + // If a field is an Option, you should wrap your new values with Some() or set it to None. This also applies when a new case + // class instance is used for an Option field. + newValues: Map[String, Any], + // Function for filtering the list of TilesKey. + filterFunc: Any => Boolean = (_ => true), + // Handling special cases where partial function input is not a TilesKey. + specialCase: (View, View, View) => PartialFunction[Any, Any] = ((_, _, _) => Map.empty) +) extends Config((site, here, up) => + scala.Function.unlift((key: Any) => { + val tiles = CoreManager.cores flatMap (core => core.updateWithFilter(up, filterFunc).lift(key)) + if (tiles.size == 0) None else Some(tiles(0)(newValues)) + }).orElse(specialCase(site, here, up)) +) \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index a36131b1..5855613e 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -33,8 +33,15 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS val suiteHelper = new TestSuiteHelper // Use Xlen as a proxy for detecting if we are a processor-like target // The underlying test suites expect this field to be defined - if (p.lift(XLen).nonEmpty) - CoreManager.cores map (core => suiteHelper.addGenericTestSuites(core.tileParamsLookup)) + if (p.lift(XLen).nonEmpty) { + val customizedSuite: Map[String, TestSuiteHelper => Unit] = Map( + // DEFINE CUSTOMIZED TEST HERE, using format ({Core name} -> _.{Test suite builder in TestSuiteHelper}) + ) + CoreManager.cores map (core => customizedSuite.get(core.name) match { + case Some(builder) => builder(suiteHelper) + case None => suiteHelper.addGenericTestSuites(core.tileParamsLookup) + }) + } // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From e021f161dca48ea7b8136208a6c7e1b5c5aff23a Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 3 Jun 2020 20:57:31 -0700 Subject: [PATCH 015/457] Remove Debug message --- generators/chipyard/src/main/scala/GenericCoreConfig.scala | 3 --- 1 file changed, 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/GenericCoreConfig.scala b/generators/chipyard/src/main/scala/GenericCoreConfig.scala index ac099742..63bc749f 100644 --- a/generators/chipyard/src/main/scala/GenericCoreConfig.scala +++ b/generators/chipyard/src/main/scala/GenericCoreConfig.scala @@ -101,9 +101,6 @@ class CopyParam(paramExtracted: SubParameterBase) { } paramCtor.newInstance(newValueList:_*) } - - // For debug purpose - print what's in the object - override def toString(): String = paramClass.getSimpleName + "(" + entries.toString + ")" } object CopyParam { From 0f116cb7174bd7baab083975527289c5aa7fed4a Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 4 Jun 2020 00:17:05 -0700 Subject: [PATCH 016/457] Tile construction delayed --- generators/chipyard/src/main/scala/CoreManager.scala | 10 ++++++++-- generators/chipyard/src/main/scala/Subsystem.scala | 9 +++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index 57b63743..9dc55eff 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -21,7 +21,7 @@ sealed trait CoreEntryBase { def tileParamsLookup(implicit p: Parameters): Seq[TileParams] def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) - (implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, BaseTile)] + (implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, () => BaseTile)] } // Implementation of third-party core entries @@ -53,7 +53,13 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi case (param, crossing) => ( param, crossing, - LazyModule(tileCtor.newInstance(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode, p.asInstanceOf[Parameters]).asInstanceOf[TileT]) + (() => LazyModule(tileCtor.newInstance( + param, + crossing, + PriorityMuxHartIdFromSeq(tileParams), + logicalTreeNode, + p.asInstanceOf[Parameters] + ).asInstanceOf[TileT])) ) } } diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 6410ac4e..fa5988e2 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -34,7 +34,9 @@ trait HasChipyardTiles extends HasTiles val module: HasChipyardTilesModuleImp // Generate tiles info from the list of cores in CoreManager - val allTilesInfo: Seq[(TileParams, RocketCrossingParams, BaseTile)] = + // Note: the 0-arity function is used to delay the construction of tiles to make sure that they are created + // in order + val allTilesInfo: Seq[(TileParams, RocketCrossingParams, () => BaseTile)] = (CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode))) // Make a tile and wire its nodes into the system, @@ -44,8 +46,11 @@ trait HasChipyardTiles extends HasTiles // This MUST be performed in order of hartid // There is something weird with registering tile-local interrupt controllers to the CLINT. // TODO: investigate why + require((allTilesInfo map (info => info._1.hartId)).max == allTilesInfo.size - 1) val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { - case (param, crossing, tile) => { + case (param, crossing, tileCtor) => { + val tile = tileCtor() + connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) connectInterrupts(tile, debugOpt, clintOpt, plicOpt) From 171b805d0e37b44a1da19d1c57bdb1f8189fed18 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 5 Jun 2020 16:50:14 -0700 Subject: [PATCH 017/457] Allow dramsim_ini folder to be set at the command line --- generators/testchipip | 2 +- .../utilities/src/main/resources/csrc/emulator.cc | 15 ++------------- sims/vcs/dramsim2_ini | 1 - sims/verilator/Makefile | 1 + sims/verilator/dramsim2_ini | 1 - variables.mk | 2 +- vlsi/Makefile | 2 -- 7 files changed, 5 insertions(+), 19 deletions(-) delete mode 120000 sims/vcs/dramsim2_ini delete mode 120000 sims/verilator/dramsim2_ini diff --git a/generators/testchipip b/generators/testchipip index 4b15061b..bb038fea 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 4b15061b6fe77f6793603f799751f1f988144ef7 +Subproject commit bb038feaa1db73bffb3fca55c6d24cb0109875bd diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 1a5a7ac3..0a3b46da 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -35,7 +35,6 @@ extern tsi_t* tsi; extern dtm_t* dtm; extern remote_bitbang_t * jtag; -extern int dramsim; static uint64_t trace_count = 0; bool verbose = false; @@ -51,11 +50,6 @@ double sc_time_stamp() return trace_count; } -extern "C" int vpi_get_vlog_info(void* arg) -{ - return 0; -} - static void usage(const char * program_name) { printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n", @@ -125,7 +119,6 @@ int main(int argc, char** argv) char ** htif_argv = NULL; int verilog_plusargs_legal = 1; - dramsim = 0; opterr = 1; while (1) { @@ -136,7 +129,6 @@ int main(int argc, char** argv) {"seed", required_argument, 0, 's' }, {"rbb-port", required_argument, 0, 'r' }, {"verbose", no_argument, 0, 'V' }, - {"dramsim", no_argument, 0, 'D' }, {"permissive", no_argument, 0, 'p' }, {"permissive-off", no_argument, 0, 'o' }, #if VM_TRACE @@ -147,9 +139,9 @@ int main(int argc, char** argv) }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:Dpo", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:po", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:VDpo", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:Vpo", long_options, &option_index); #endif if (c == -1) break; retry: @@ -162,7 +154,6 @@ int main(int argc, char** argv) case 's': random_seed = atoi(optarg); break; case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; - case 'D': dramsim = 1; break; case 'p': opterr = 0; break; case 'o': opterr = 1; break; #if VM_TRACE @@ -198,8 +189,6 @@ int main(int argc, char** argv) #endif else if (arg.substr(0, 12) == "+cycle-count") c = 'c'; - else if (arg == "+dramsim") - c = 'D'; else if (arg == "+permissive") c = 'p'; else if (arg == "+permissive-off") diff --git a/sims/vcs/dramsim2_ini b/sims/vcs/dramsim2_ini deleted file mode 120000 index 19d93477..00000000 --- a/sims/vcs/dramsim2_ini +++ /dev/null @@ -1 +0,0 @@ -../../generators/testchipip/src/main/resources/dramsim2_ini \ No newline at end of file diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 1b9276ac..98df1296 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -87,6 +87,7 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 VERILATOR_NONCC_OPTS = \ $(TIMESCALE_OPTS) \ --top-module $(VLOG_MODEL) \ + --vpi \ -Wno-fatal \ $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ --output-split 10000 \ diff --git a/sims/verilator/dramsim2_ini b/sims/verilator/dramsim2_ini deleted file mode 120000 index 19d93477..00000000 --- a/sims/verilator/dramsim2_ini +++ /dev/null @@ -1 +0,0 @@ -../../generators/testchipip/src/main/resources/dramsim2_ini \ No newline at end of file diff --git a/variables.mk b/variables.mk index 4d49d5fe..61d85e60 100644 --- a/variables.mk +++ b/variables.mk @@ -139,7 +139,7 @@ output_dir=$(sim_dir)/output/$(long_name) PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= -override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles) +override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose sim_out_name = $(subst $() $(),_,$(notdir $(basename $(BINARY))).$(long_name)) diff --git a/vlsi/Makefile b/vlsi/Makefile index b7e76c50..7fbfcc2c 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -99,8 +99,6 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) mkdir -p $(dir $@) - mkdir -p $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY)) - ln -sf $(base_dir)/generators/testchipip/src/main/resources/dramsim2_ini $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY))/dramsim2_ini echo "sim.inputs:" > $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ From cdddc5982a761acfe850773fea571cd70c3ed9af Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 5 Jun 2020 18:22:31 -0700 Subject: [PATCH 018/457] Bump sha3 for multi-sha fix (#597) --- generators/sha3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sha3 b/generators/sha3 index a94dcf3a..762d9d08 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit a94dcf3ae0a0440aade96bcdaa4da685352ae704 +Subproject commit 762d9d08f8ccd96ba7ab12ead6d38a6b57fa8710 From 98f6f9292eceede4c4e213991487275b58456560 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sat, 6 Jun 2020 16:22:59 -0700 Subject: [PATCH 019/457] Change Generic Config --- .../src/main/scala/ConfigFragments.scala | 21 +- .../chipyard/src/main/scala/CoreManager.scala | 12 +- .../src/main/scala/GenericCoreConfig.scala | 253 +++++++++++------- 3 files changed, 169 insertions(+), 117 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 4d0e0725..da1372db 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import freechips.rocketchip.util.{AsyncResetReg} import boom.common.{BoomTilesKey} +import ariane.ArianeTilesKey import testchipip._ import hwacha.{Hwacha} @@ -22,7 +23,8 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} -import chipyard.GenericCoreConfig +import chipyard.TilesKey +import chipyard.TileSeq._ /** * TODO: Why do we need this? @@ -59,7 +61,11 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) }) -class WithL2TLBs(entries: Int) extends GenericCoreConfig(Map("core" -> Map("nL2TLBEntries" -> entries))) +class WithL2TLBs(entries: Int) extends Config((site, here, up) => { + case TilesKey(tilesKey) => up(tilesKey) tileMap (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) +}) class WithTracegenSystem extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) @@ -140,9 +146,8 @@ class WithControlCore extends Config((site, here, up) => { case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) -class WithTraceIO extends GenericCoreConfig( - newValues = Map("trace" -> true), - specialCase = (site, here, up) => { - case TracePortKey => Some(TracePortParams()) - } -) \ No newline at end of file +class WithTraceIO extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) +}) \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index 9dc55eff..b5129217 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -18,8 +18,10 @@ import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} // Base trait for all third-party core entries sealed trait CoreEntryBase { val name: String + + def keyEqual(key: Any): Boolean def tileParamsLookup(implicit p: Parameters): Seq[TileParams] - def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] + def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) (implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, () => BaseTile)] } @@ -35,15 +37,11 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) private val tileCtor = tileClass.getConstructors.filter(ctor => ctor.getParameterTypes()(4) == classOf[Parameters]).head + def keyEqual(key: Any) = key == tilesKey + // Tile parameter lookup using correct type def tileParamsLookup(implicit p: Parameters) = p(tilesKey) - // If this core meet the requirement given by p, update parameter fields in the map - def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] = { - case key if (key == tilesKey && p(tilesKey)) => newValues => view(tilesKey) map - (tile => CopyParam(tile, newValues)) - } - // Instantiate a tile and zip it with its parameter info, used by subsystem def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) (implicit p: Parameters, valName: ValName) = { diff --git a/generators/chipyard/src/main/scala/GenericCoreConfig.scala b/generators/chipyard/src/main/scala/GenericCoreConfig.scala index 63bc749f..159b8b69 100644 --- a/generators/chipyard/src/main/scala/GenericCoreConfig.scala +++ b/generators/chipyard/src/main/scala/GenericCoreConfig.scala @@ -15,116 +15,165 @@ import freechips.rocketchip.tile._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} -// Extractor object accompanied class -// This is used to check the convertibility for those wrapped in Option, since Option's type is erased at runtime. -trait SubParameterBase { - def toProduct: Product - def cast(p: Any): Any -} -final class SubParameter[T <: Product](param: T) extends SubParameterBase { - def toProduct: Product = param - def cast(p: Any) = p.asInstanceOf[T] +// Case class to change common parameters visible in the base traits. Some fields in the base traits may not be configurable as a +// case class constructor parameter for some cores, and those field will be ignored when applied. +case class GenericCoreParams( + val bootFreqHz: BigInt, + val useVM: Boolean, + val useUser: Boolean, + val useSupervisor: Boolean, + val useDebug: Boolean, + val useAtomics: Boolean, + val useAtomicsOnlyForIO: Boolean, + val useCompressed: Boolean, + override val useVector: Boolean, + val useSCIE: Boolean, + val useRVE: Boolean, + val mulDiv: Option[MulDivParams], + val fpu: Option[FPUParams], + val fetchWidth: Int, + val decodeWidth: Int, + val retireWidth: Int, + val instBits: Int, + val nLocalInterrupts: Int, + val nPMPs: Int, + val pmpGranularity: Int, + val nBreakpoints: Int, + val useBPWatch: Boolean, + val nPerfCounters: Int, + val haveBasicCounters: Boolean, + val haveFSDirty: Boolean, + val misaWritable: Boolean, + val haveCFlush: Boolean, + val nL2TLBEntries: Int, + val mtvecInit: Option[BigInt], + val mtvecWritable: Boolean, + // The original object + val _origin: CoreParams +) extends CoreParams { + def this(coreParams: CoreParams) = this( + bootFreqHz = coreParams.bootFreqHz, + useVM = coreParams.useVM, + useUser = coreParams.useUser, + useSupervisor = coreParams.useSupervisor, + useDebug = coreParams.useDebug, + useAtomics = coreParams.useAtomics, + useAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO, + useCompressed = coreParams.useCompressed, + useVector = coreParams.useVector, + useSCIE = coreParams.useSCIE, + useRVE = coreParams.useRVE, + mulDiv = coreParams.mulDiv, + fpu = coreParams.fpu, + fetchWidth = coreParams.fetchWidth, + decodeWidth = coreParams.decodeWidth, + retireWidth = coreParams.retireWidth, + instBits = coreParams.instBits, + nLocalInterrupts = coreParams.nLocalInterrupts, + nPMPs = coreParams.nPMPs, + pmpGranularity = coreParams.pmpGranularity, + nBreakpoints = coreParams.nBreakpoints, + useBPWatch = coreParams.useBPWatch, + nPerfCounters = coreParams.nPerfCounters, + haveBasicCounters = coreParams.haveBasicCounters, + haveFSDirty = coreParams.haveFSDirty, + misaWritable = coreParams.misaWritable, + haveCFlush = coreParams.haveCFlush, + nL2TLBEntries = coreParams.nL2TLBEntries, + mtvecInit = coreParams.mtvecInit, + mtvecWritable = coreParams.mtvecWritable, + + _origin = coreParams + ) + + // Reflection Info of this class + val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init + + // Convert back to core-specific tile + def convert: CoreParams = { + // Reflection of target class + val paramClass = _origin.getClass + val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) + val paramCtor = paramClass.getConstructors.head + + // Build a list of parameter in the original parameter class + val nameDict = paramNames.zipWithIndex.toMap + val indexList = fieldNames map (n => nameDict.get(n)) + val fieldList = this.productIterator.toList.init + val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap + val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map + { case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] } + + paramCtor.newInstance(newValues:_*).asInstanceOf[CoreParams] + } + + // Implement abstract function as placeholder + def lrscCycles: Int = _origin.lrscCycles } -// Extractor object that help identify the parameter case classes. -// Add your customized nested parameter classes (or their commom base classes) here. -object CustomizedSubParameter { - def unapply(param: Product): Option[Product] = param match { - // ADD YOUR NESTED PARAMETER CLASS HERE, in the format shown below in SubParameter - case _ => None +case class GenericTileParams( + val core: GenericCoreParams, + val icache: Option[ICacheParams], + val dcache: Option[DCacheParams], + val btb: Option[BTBParams], + val hartId: Int, + val beuAddr: Option[BigInt], + val blockerCtrlAddr: Option[BigInt], + val name: Option[String], + // The original object + val _origin: TileParams +) extends TileParams { + // Copy constructor to build the params + def this(tileParams: TileParams) = this( + core = new GenericCoreParams(tileParams.core), + icache = tileParams.icache, + dcache = tileParams.dcache, + btb = tileParams.btb, + hartId = tileParams.hartId, + beuAddr = tileParams.beuAddr, + blockerCtrlAddr = tileParams.blockerCtrlAddr, + name = tileParams.name, + + _origin = tileParams + ) + + // Reflection Info of this class + val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init + + // Convert back to core-specific tile + def convert: TileParams = { + // Reflection of target class + val paramClass = _origin.getClass + val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) + val paramCtor = paramClass.getConstructors.head + + // Build a list of parameter in the original parameter class + val nameDict = paramNames.zipWithIndex.toMap + val indexList = fieldNames map (n => nameDict.get(n)) + val fieldList = this.productIterator.toList.updated(0, core.convert).init + val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap + val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map + { case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] } + + paramCtor.newInstance(newValues:_*).asInstanceOf[TileParams] } } -// Standard nested -object SubParameter { - def unapply(param: Product): Option[SubParameterBase] = param match { - case p: TileParams => Some(new SubParameter(p)) - case p: CoreParams => Some(new SubParameter(p)) - case p: ICacheParams => Some(new SubParameter(p)) - case p: DCacheParams => Some(new SubParameter(p)) - case p: MulDivParams => Some(new SubParameter(p)) - case p: FPUParams => Some(new SubParameter(p)) - case p: BTBParams => Some(new SubParameter(p)) - case p: BHTParams => Some(new SubParameter(p)) - case CustomizedSubParameter(p) => Some(new SubParameter(p)) - case _ => None - } +// Extractor to capture TilesKey +object TilesKey { + def unapply(key: Any): Option[Field[Seq[_]]] = + if ((CoreManager.cores filter (core => core.keyEqual(key))).size != 0) Some(key.asInstanceOf[Field[Seq[_]]]) else None } -// Dynamic update helper for Parameter class. -class CopyParam(paramExtracted: SubParameterBase) { - // Constructor for corresponding TileParams - private val param: Product = paramExtracted.toProduct - private val paramClass = param.getClass - private val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) - private val paramCtor = paramClass.getConstructors.head +class TileSeq(list: Seq[Any]) { + def tileMap(f: GenericTileParams => GenericTileParams): Seq[TileParams] = { + // If this is not an unpacked tile key, simply throw a type exception + // Static type checking is not possible when this class is used with TilesKey extractor + val tileList = list.asInstanceOf[Seq[TileParams]] - // Function to build value entry - private def buildEntry(value: Any): Any = value match { - case Some(v) => Some(buildEntry(v)) - case SubParameter(p) => new CopyParam(p) - case v => v - } - - // Value of the case class - private val entries = param.productIterator.toList map (v => buildEntry(v)) - - // Update one value entry - private def updateEntry(entry: Any, newValue: Any): Any = entry match { - case Some(e) => newValue match { - case Some(v) => Some(updateEntry(e, v)) - case None => None - } - case e: CopyParam => newValue match { - case newValues: Map[String, Any] => e.update(newValues) - case v => paramExtracted.cast(v) - } - // Use cast() to check the type of the new value. Here I assume that all entries in the parameters class are simple values - // (like Int, BigInt and String), which are all final. This may breaks if a polymorphic type is added (unless it's a case - // class and registered above). - case e => e.getClass.cast(newValue) - } - - // Update the entire parameter object. - def update(newValues: Map[String, Any]): Any = { - val filteredValues = newValues.filter({ case (key, value) => paramNames contains key }) - val newValueList = entries.zipWithIndex map { - case (value, i) if newValues contains paramNames(i) => updateEntry(value, filteredValues(paramNames(i))).asInstanceOf[AnyRef] - case (value, i) => (value match { - case Some(v) => v match { - case copyParam: CopyParam => Some(copyParam.param) - case _ => Some(v) - } - case copyParam: CopyParam => copyParam.param - case _ => value - }).asInstanceOf[AnyRef] - } - paramCtor.newInstance(newValueList:_*) + tileList map (tileParams => f(new GenericTileParams(tileParams)).convert) } } - -object CopyParam { - def apply(param: Product, newValues: Map[String, Any]): Any = param match { - case SubParameter(p) => new CopyParam(p).update(newValues) - case _ => throw new Exception("param is not a known Parameter type: add your custom parameter class to GenericCoreConfig.scala to fix it") - } +object TileSeq { + implicit def convertSeq(s: Seq[Any]) = new TileSeq(s) } - -// Change parameters for all registered cores in CoreManager. -class GenericCoreConfig ( - // Key-value pairs to be updated (keys are the name of fields). Any field not in a core's parameters will be ignored. - // If a field is a case class containing parameters (or an Option of that), you can use another Map containing the key-value pairs to - // update that case class. Using a new case class instance as the value is also acceptable. - // If a field is an Option, you should wrap your new values with Some() or set it to None. This also applies when a new case - // class instance is used for an Option field. - newValues: Map[String, Any], - // Function for filtering the list of TilesKey. - filterFunc: Any => Boolean = (_ => true), - // Handling special cases where partial function input is not a TilesKey. - specialCase: (View, View, View) => PartialFunction[Any, Any] = ((_, _, _) => Map.empty) -) extends Config((site, here, up) => - scala.Function.unlift((key: Any) => { - val tiles = CoreManager.cores flatMap (core => core.updateWithFilter(up, filterFunc).lift(key)) - if (tiles.size == 0) None else Some(tiles(0)(newValues)) - }).orElse(specialCase(site, here, up)) -) \ No newline at end of file From 0863e8d1ce81647cefb73212cc4c363df3cbc85f Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 8 Jun 2020 11:02:27 -0700 Subject: [PATCH 020/457] Enable hammer simulations to run in parallel Bumps hammer and its plugins Updates to makefile for running simulations without BINARY Enables make power-par to automatically connect from sim-par --- vlsi/Makefile | 4 ++++ vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 7fbfcc2c..42af7ba2 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -129,7 +129,9 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file echo ' - "'$$x'"' >> $@; \ done echo " execution_flags_meta: 'append'" >> $@ +ifneq ($(BINARY), ) echo " benchmarks: ['$(BINARY)']" >> $@ +endif echo " tb_dut: 'testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) @@ -158,12 +160,14 @@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_fi echo "power.inputs:" > $@ echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ +ifneq ($(BINARY), ) echo " saifs: [" >> $@ echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@ echo " ]" >> $@ echo " waveforms: [" >> $@ #echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@ echo " ]" >> $@ +endif echo " start_times: ['0ns']" >> $@ echo " end_times: [" >> $@ echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ diff --git a/vlsi/hammer b/vlsi/hammer index 9d83bbad..a05f97b1 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 9d83bbadc0caaa7f81b4929c4e32333fc5a8d900 +Subproject commit a05f97b1f75ba924df117dfc34a11b1ada9406c1 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index f644138b..7ad99d44 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit f644138bab11075f267a3f1d72108da13c8a05ab +Subproject commit 7ad99d445f3121662aee6531950f6a9ac2da2256 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index ef163445..78dac526 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit ef163445eec6362fa6a9bf6be0bd18a5d36c707e +Subproject commit 78dac526c0864ee826b989619e27036175b5edee From 629ca805e41ea19b9fd2dae9c89863bea1a97aeb Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 10 Jun 2020 13:46:43 -0700 Subject: [PATCH 021/457] Bump hammer branches to master after merge --- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vlsi/hammer b/vlsi/hammer index a05f97b1..bd94e1ed 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit a05f97b1f75ba924df117dfc34a11b1ada9406c1 +Subproject commit bd94e1ed7a5f70fe85ea833cb89836efefe53dc7 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 7ad99d44..d905828d 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 7ad99d445f3121662aee6531950f6a9ac2da2256 +Subproject commit d905828d68aeb4ff5619418807a8aa6d7376d796 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index 78dac526..e5ec0da8 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit 78dac526c0864ee826b989619e27036175b5edee +Subproject commit e5ec0da8ad471b075de62989001b282e537416d0 From 623bafacd5731b84e49d87a400499db38ab2bf66 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 Jun 2020 14:46:53 -0700 Subject: [PATCH 022/457] Warn if RISCV unset (#601) --- .circleci/do-rtl-build.sh | 7 ++++++- common.mk | 8 ++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 54996f54..a7c8ad50 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -53,15 +53,20 @@ else fi # enter the verilator directory and build the specific config on remote server -run "make -C $REMOTE_SIM_DIR clean" run "export RISCV=\"$TOOLS_DIR\"; \ export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -C $REMOTE_SIM_DIR clean; \ make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" +# copy back the final build + + +run "rm -rf $REMOTE_CHIPYARD_DIR/project" + # copy back the final build mkdir -p $LOCAL_CHIPYARD_DIR copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR diff --git a/common.mk b/common.mk index f07342de..4b5b00f2 100644 --- a/common.mk +++ b/common.mk @@ -3,6 +3,14 @@ ######################################################################################### SHELL=/bin/bash + +ifndef RISCV +$(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file) +else +$(info Running with RISCV=$(RISCV)) +endif + + ######################################################################################### # extra make variables/rules from subprojects # From 4bfd89be6b7aa93d418219f2f766cab2aea2db24 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 11 Jun 2020 11:18:34 -0700 Subject: [PATCH 023/457] Use an accurate name for the ci skip list --- .githooks/ignore-certain-dirs-commit-msg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.githooks/ignore-certain-dirs-commit-msg b/.githooks/ignore-certain-dirs-commit-msg index 3ab0e7b4..8756b916 100644 --- a/.githooks/ignore-certain-dirs-commit-msg +++ b/.githooks/ignore-certain-dirs-commit-msg @@ -8,9 +8,9 @@ fi changes=( `git diff --name-only --cached` ) # Load the patterns we want to skip into an array -mapfile -t blacklist < .ciignore +mapfile -t blocklist < .ciignore -for i in "${blacklist[@]}" +for i in "${blocklist[@]}" do # Remove the current pattern from the list of changes changes=( ${changes[@]/$i/} ) From 71f340a0af50ccc3fa0aedbd522b5e3bf3e6d2c9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 12 Jun 2020 10:08:55 -0700 Subject: [PATCH 024/457] Use output_dir for run-binary logs and waveforms (#596) * Dump run-binary files in output/$(long_name) instead of current directory * Remove run-none rules, these were equivalent to run-binary BINARY=none --- .circleci/run-tests.sh | 4 ++-- common.mk | 26 +++++++------------------- sims/vcs/Makefile | 4 ---- sims/verilator/Makefile | 6 ------ variables.mk | 2 +- 5 files changed, 10 insertions(+), 32 deletions(-) diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 4f4779fd..08b95e68 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -93,10 +93,10 @@ case $1 in make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary ;; icenet) - make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} + make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR ${mapping[$1]} ;; testchipip) - make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} + make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR ${mapping[$1]} ;; *) echo "No set of tests for $1. Did you spell it right?" diff --git a/common.mk b/common.mk index 4b5b00f2..5b502cb1 100644 --- a/common.mk +++ b/common.mk @@ -137,34 +137,30 @@ verilog: $(sim_vsrcs) # helper rules to run simulations ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast -run-binary: $(sim) +run-binary: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### -run-binary-fast: $(sim) +run-binary-fast: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast -run-none: $(output_dir)/none.out - -run-none-fast: $(output_dir)/none.run - -run-none-debug: $(output_dir)/none.vpd - ######################################################################################### # run assembly/benchmarks rules ######################################################################################### -$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% - mkdir -p $(output_dir) +$(output_dir): + mkdir -p $@ + +$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% $(output_dir) ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) @@ -173,14 +169,6 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) $(output_dir)/%.out: $(output_dir)/% $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) -$(output_dir)/none.run: $(sim) - mkdir -p $(output_dir) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $(output_dir)/none.log) - ######################################################################################### # include build/project specific makefrags made from the generator ######################################################################################### diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 83884937..df2dbbe6 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -62,10 +62,6 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) -$(output_dir)/none.vpd: $(sim_debug) - mkdir -p $(output_dir) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) - ######################################################################################### # general cleanup rule ######################################################################################### diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 98df1296..667c856c 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -147,12 +147,6 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) vcd2vpd $@.vcd $@ > /dev/null & (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) -$(output_dir)/none.vpd: $(sim_debug) - mkdir -p $(output_dir) - rm -f $@.vcd && mkfifo $@.vcd - vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) - ######################################################################################### # general cleanup rule ######################################################################################### diff --git a/variables.mk b/variables.mk index 61d85e60..1a3623a2 100644 --- a/variables.mk +++ b/variables.mk @@ -141,7 +141,7 @@ PERMISSIVE_OFF=+permissive-off BINARY ?= override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose -sim_out_name = $(subst $() $(),_,$(notdir $(basename $(BINARY))).$(long_name)) +sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) ######################################################################################### # build output directory for compilation From 119a44b1219a6930bcf895d91cd9b7f7d0867f7f Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sat, 13 Jun 2020 01:36:14 -0700 Subject: [PATCH 025/457] Use config to manage core registration and custom tests --- .../src/main/scala/ConfigFragments.scala | 9 +- .../chipyard/src/main/scala/CoreManager.scala | 53 +++++++++- ...reConfig.scala => GenericCoreParams.scala} | 97 +++++++------------ .../chipyard/src/main/scala/Subsystem.scala | 2 +- .../chipyard/src/main/scala/TestSuites.scala | 15 +++ .../scala/stage/phases/AddDefaultTests.scala | 16 ++- 6 files changed, 111 insertions(+), 81 deletions(-) rename generators/chipyard/src/main/scala/{GenericCoreConfig.scala => GenericCoreParams.scala} (69%) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index da1372db..8336bdc5 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -23,8 +23,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} -import chipyard.TilesKey -import chipyard.TileSeq._ +import chipyard.{GenericTilesKey, GenericTileConfig} /** * TODO: Why do we need this? @@ -61,8 +60,8 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) }) -class WithL2TLBs(entries: Int) extends Config((site, here, up) => { - case TilesKey(tilesKey) => up(tilesKey) tileMap (tile => tile.copy( +class WithL2TLBs(entries: Int) extends GenericTileConfig((site, here, up) => { + case GenericTilesKey(key) => up(GenericTilesKey(key)) map (tile => tile.copy( core = tile.core.copy(nL2TLBEntries = entries) )) }) @@ -150,4 +149,4 @@ class WithTraceIO extends Config((site, here, up) => { case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) case TracePortKey => Some(TracePortParams()) -}) \ No newline at end of file +}) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala index b5129217..d013cc7c 100644 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ b/generators/chipyard/src/main/scala/CoreManager.scala @@ -15,6 +15,21 @@ import freechips.rocketchip.tile._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} +case object CoreEntryKey extends Field[Seq[CoreEntryBase]](Nil) + +// If this key is encountered by a GenericTilesKey extractor, throw immediately +// Inside the body of GenericTileConfig, suppressed will be set to true to prevent the extractor from throwing +case class GenericTilesKeyChecker(suppressed: Boolean) extends Field[Int](0) +case class GenericTilesKeyImp(key: Field[Seq[TileParams]]) extends Field[Seq[GenericTileParams]](Nil) +object GenericTilesKey { + def apply(key: Field[Seq[TileParams]]) = GenericTilesKeyImp(key) + def unapply(key: Any): Option[Field[Seq[TileParams]]] = key match { + case GenericTilesKeyChecker(suppressed) if !suppressed => throw new Exception("GenericTilesKey must be in GenericTilesConfig") + case GenericTilesKeyImp(key) => Some(key) + case _ => None + } +} + // Base trait for all third-party core entries sealed trait CoreEntryBase { val name: String @@ -45,6 +60,11 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi // Instantiate a tile and zip it with its parameter info, used by subsystem def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) (implicit p: Parameters, valName: ValName) = { + // Sanity check of GenericTilesKey outside of GenericTileConfig + // People would shoot themselves in the foot easily with this design, so a sanity check is necessary + // Simply trigger the exception by looking up the checker key + p(GenericTilesKeyChecker(false)) + val tileParams = p(tilesKey) val crossings = crossingLookup(p(crossingKey), tileParams.size) (tileParams zip crossings) map { @@ -63,12 +83,41 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi } } +// Config fragment to register a core +class RegisterCore[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTile : TypeTag]( + name: String, + tilesKey: Field[Seq[TileParamsT]], + crossingKey: Field[Seq[RocketCrossingParams]] +) extends Config((site, here, up) => { + case CoreEntryKey => new CoreEntry[TileParamsT, TileT](name, tilesKey, crossingKey) +: up(CoreEntryKey) +}) + +// The config used along with GenericTilesKey. +// It change a lookup for registered tile parameter into a lookup with GenericTilesKey in the function body temporarily. +class GenericTileConfig(f: (View, View, View) => PartialFunction[Any, Any]) extends Config( + new Config((site, here, up) => { + case GenericTilesKeyChecker(_) => up(GenericTilesKeyChecker(true)) + case key if CoreManager.keyMatch(up, key) => up(GenericTilesKey(key.asInstanceOf[Field[Seq[TileParams]]])) map (t => t.convert) + }) ++ + new Config(f) ++ + new Config((site, here, up) => { + case GenericTilesKeyChecker(_) => up(GenericTilesKeyChecker(false)) + case GenericTilesKey(key) => up(key) map (t => new GenericTileParams(t)) + }) +) + // A list of all cores. object CoreManager { - val cores: List[CoreEntryBase] = List( - // TODO ADD YOUR CORE DEFINITION HERE; note that the + // Built-in cores. + val base_cores: List[CoreEntryBase] = List( new CoreEntry[RocketTileParams, RocketTile]("Rocket", RocketTilesKey, RocketCrossingKey), new CoreEntry[BoomTileParams, BoomTile]("Boom", BoomTilesKey, BoomCrossingKey), new CoreEntry[ArianeTileParams, ArianeTile]("Ariane", ArianeTilesKey, ArianeCrossingKey) ) + + // Look up all cores that are registered in the current config view. + def cores(view: View): Seq[CoreEntryBase] = view(CoreEntryKey) ++ base_cores + + // Check if the key is among the currently registered cores. + def keyMatch(view: View, key: Any) = (cores(view) filter (c => c.keyEqual(key))).size != 0 } diff --git a/generators/chipyard/src/main/scala/GenericCoreConfig.scala b/generators/chipyard/src/main/scala/GenericCoreParams.scala similarity index 69% rename from generators/chipyard/src/main/scala/GenericCoreConfig.scala rename to generators/chipyard/src/main/scala/GenericCoreParams.scala index 159b8b69..28db42b1 100644 --- a/generators/chipyard/src/main/scala/GenericCoreConfig.scala +++ b/generators/chipyard/src/main/scala/GenericCoreParams.scala @@ -15,6 +15,36 @@ import freechips.rocketchip.tile._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} +// Trait for generic case class of base trait for copying +trait ConcreteBaseTrait[Base] { + this: Product => + val _origin: Base + + // Convert back to core-specific tile + def convert: Base = { + // Reflection Info of this class + val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init + + // Reflection of target class + val paramClass = _origin.getClass + val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) + val paramCtor = paramClass.getConstructors.head + + // Build a list of parameter in the original parameter class + val nameDict = paramNames.zipWithIndex.toMap + val indexList = fieldNames map (n => nameDict.get(n)) + val fieldList = this.productIterator.toList map { + case c: ConcreteBaseTrait[_] => c.convert + case v => v + } + val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap + val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map + { case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] } + + paramCtor.newInstance(newValues:_*).asInstanceOf[Base] + } +} + // Case class to change common parameters visible in the base traits. Some fields in the base traits may not be configurable as a // case class constructor parameter for some cores, and those field will be ignored when applied. case class GenericCoreParams( @@ -50,7 +80,7 @@ case class GenericCoreParams( val mtvecWritable: Boolean, // The original object val _origin: CoreParams -) extends CoreParams { +) extends CoreParams with ConcreteBaseTrait[CoreParams] { def this(coreParams: CoreParams) = this( bootFreqHz = coreParams.bootFreqHz, useVM = coreParams.useVM, @@ -86,27 +116,6 @@ case class GenericCoreParams( _origin = coreParams ) - // Reflection Info of this class - val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init - - // Convert back to core-specific tile - def convert: CoreParams = { - // Reflection of target class - val paramClass = _origin.getClass - val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) - val paramCtor = paramClass.getConstructors.head - - // Build a list of parameter in the original parameter class - val nameDict = paramNames.zipWithIndex.toMap - val indexList = fieldNames map (n => nameDict.get(n)) - val fieldList = this.productIterator.toList.init - val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap - val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map - { case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] } - - paramCtor.newInstance(newValues:_*).asInstanceOf[CoreParams] - } - // Implement abstract function as placeholder def lrscCycles: Int = _origin.lrscCycles } @@ -121,8 +130,8 @@ case class GenericTileParams( val blockerCtrlAddr: Option[BigInt], val name: Option[String], // The original object - val _origin: TileParams -) extends TileParams { + val _origin: TileParams, +) extends TileParams with ConcreteBaseTrait[TileParams] { // Copy constructor to build the params def this(tileParams: TileParams) = this( core = new GenericCoreParams(tileParams.core), @@ -136,44 +145,4 @@ case class GenericTileParams( _origin = tileParams ) - - // Reflection Info of this class - val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init - - // Convert back to core-specific tile - def convert: TileParams = { - // Reflection of target class - val paramClass = _origin.getClass - val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) - val paramCtor = paramClass.getConstructors.head - - // Build a list of parameter in the original parameter class - val nameDict = paramNames.zipWithIndex.toMap - val indexList = fieldNames map (n => nameDict.get(n)) - val fieldList = this.productIterator.toList.updated(0, core.convert).init - val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap - val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map - { case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] } - - paramCtor.newInstance(newValues:_*).asInstanceOf[TileParams] - } -} - -// Extractor to capture TilesKey -object TilesKey { - def unapply(key: Any): Option[Field[Seq[_]]] = - if ((CoreManager.cores filter (core => core.keyEqual(key))).size != 0) Some(key.asInstanceOf[Field[Seq[_]]]) else None -} - -class TileSeq(list: Seq[Any]) { - def tileMap(f: GenericTileParams => GenericTileParams): Seq[TileParams] = { - // If this is not an unpacked tile key, simply throw a type exception - // Static type checking is not possible when this class is used with TilesKey extractor - val tileList = list.asInstanceOf[Seq[TileParams]] - - tileList map (tileParams => f(new GenericTileParams(tileParams)).convert) - } -} -object TileSeq { - implicit def convertSeq(s: Seq[Any]) = new TileSeq(s) } diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index fa5988e2..4ac92c4e 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -37,7 +37,7 @@ trait HasChipyardTiles extends HasTiles // Note: the 0-arity function is used to delay the construction of tiles to make sure that they are created // in order val allTilesInfo: Seq[(TileParams, RocketCrossingParams, () => BaseTile)] = - (CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode))) + (CoreManager.cores(p) flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode))) // Make a tile and wire its nodes into the system, // according to the specified type of clock crossing. diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 2261000f..5a929010 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -2,6 +2,7 @@ package chipyard import scala.collection.mutable.{LinkedHashSet} +import freechips.rocketchip.config.{Parameters, Config, Field, View} import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.tile.{XLen, TileParams} import freechips.rocketchip.config.{Parameters, Field} @@ -102,3 +103,17 @@ class TestSuiteHelper } } } + +/** + * Config key of custom test suite. + */ +case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => Unit]((tiles, helper, p) => helper.addGenericTestSuites(tiles)(p)) + +/** + * Config fragment to add custom test suite factory function. + * + * @param suiteFactory Test suite factory function. It takes a list of TileParams to be instantiated and the test suite helper. + */ +class WithTestSuite(suiteFactory: (Seq[TileParams], TestSuiteHelper, Parameters) => Unit) extends Config((site, here, up) => { + case TestSuitesKey => suiteFactory +}) diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 5855613e..b170706e 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -19,6 +19,7 @@ import freechips.rocketchip.util.HasRocketChipStageUtils import freechips.rocketchip.tile.XLen import chipyard.{TestSuiteHelper, CoreManager} +import chipyard.TestSuitesKey class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase @@ -33,15 +34,12 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS val suiteHelper = new TestSuiteHelper // Use Xlen as a proxy for detecting if we are a processor-like target // The underlying test suites expect this field to be defined - if (p.lift(XLen).nonEmpty) { - val customizedSuite: Map[String, TestSuiteHelper => Unit] = Map( - // DEFINE CUSTOMIZED TEST HERE, using format ({Core name} -> _.{Test suite builder in TestSuiteHelper}) - ) - CoreManager.cores map (core => customizedSuite.get(core.name) match { - case Some(builder) => builder(suiteHelper) - case None => suiteHelper.addGenericTestSuites(core.tileParamsLookup) - }) - } + if (p.lift(XLen).nonEmpty) + // If a custom test suite is set up, use the custom test suite + if (p.lift(TestSuitesKey).nonEmpty) + CoreManager.cores(p) map (core => p(TestSuitesKey).apply(core.tileParamsLookup, suiteHelper, p)) + else + CoreManager.cores(p) map (core => suiteHelper.addGenericTestSuites(core.tileParamsLookup)) // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From 5acf583d88088f3d36f9c2ec7fc903ac1c095749 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Thu, 18 Jun 2020 13:55:33 -0700 Subject: [PATCH 026/457] OpenROAD synthesis complete with fake rams on nangate45 --- vlsi/.gitignore | 3 +- vlsi/Makefile | 20 +++-- vlsi/example-nangate45.yml | 144 ++++++++++++++++++++++++++++++++++++ vlsi/example-vlsi-nangate45 | 29 ++++++++ vlsi/hammer | 2 +- 5 files changed, 188 insertions(+), 10 deletions(-) create mode 100644 vlsi/example-nangate45.yml create mode 100755 vlsi/example-vlsi-nangate45 diff --git a/vlsi/.gitignore b/vlsi/.gitignore index 4cbcfe8f..abe3347f 100644 --- a/vlsi/.gitignore +++ b/vlsi/.gitignore @@ -3,4 +3,5 @@ __pycache__ hammer*.log build src/test/output-*.json -generated-src \ No newline at end of file +generated-src +output.json diff --git a/vlsi/Makefile b/vlsi/Makefile index 42af7ba2..912eecdd 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -19,18 +19,22 @@ include $(base_dir)/variables.mk ######################################################################################### sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 -tech_dir ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) +tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ + $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ + $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -ifeq ($(tech_name),asap7) - MACROCOMPILER_MODE ?= --mode synflops -else - MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) -endif +MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ + --mode synflops,\ + -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) ENV_YML ?= $(vlsi_dir)/env.yml -INPUT_CONFS ?= example.yml -HAMMER_EXEC ?= ./example-vlsi +INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ + example-nangate45.yml,\ + example.yml) +HAMMER_EXEC ?= $(if $(filter $(tech_name),nangate45),\ + example-vlsi-nangate45,\ + example-vlsi) VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml new file mode 100644 index 00000000..de4d912f --- /dev/null +++ b/vlsi/example-nangate45.yml @@ -0,0 +1,144 @@ +# Technology Setup +# Technology used is nanagate45 +vlsi.core.technology: nangate45 +# Specify dir with ASAP7 tarball +technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" + +vlsi.core.max_threads: 12 + +# General Hammer Inputs + +# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info +vlsi.inputs.power_spec_mode: "auto" +vlsi.inputs.power_spec_type: "cpf" + +# Specify clock signals +vlsi.inputs.clocks: [ + {name: "clock", period: "5ns", uncertainty: "0.5ns"} +] + +# Generate Make include to aid in flow +vlsi.core.build_system: make + +# Power Straps +#par.power_straps_mode: generate +#par.generate_power_straps_method: by_tracks +#par.blockage_spacing: 2.0 +#par.generate_power_straps_options: +# by_tracks: +# strap_layers: +# - metal3 +# - metal4 +# - metal5 +# - metal6 +# - metal7 +# - metal8 +# pin_layers: +# - metal7 +# - metal8 +# track_width: 7 # minimum allowed for M2 & M3 +# track_spacing: 0 +# track_spacing_M3: 1 # to avoid M2 shorts at higher density +# track_start: 10 +# power_utilization: 0.05 +# power_utilization_M8: 1.0 +# power_utilization_M9: 1.0 + +# Placement Constraints +# For ASAP7, all numbers must be 4x larger than final GDS +vlsi.inputs.placement_constraints: + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + width: 1387.38 + height: 1199.1 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 +# - path: "Sha3AccelwBB/dco" +# type: hardmacro +# x: 108 +# y: 108 +# width: 128 +# height: 128 +# orientation: r0 +# top_layer: M9 +# - path: "Sha3AccelwBB/place_obs_bottom" +# type: obstruction +# obs_types: ["place"] +# x: 0 +# y: 0 +# width: 300 +# height: 1.08 # 1 core site tall, necessary to avoid shorts + +# Pin placement constraints +#vlsi.inputs.pin_mode: generated +#vlsi.inputs.pin.generate_mode: semi_auto +#vlsi.inputs.pin.assignments: [ +# {pins: "*", layers: ["metal7", "metal8"]} +#] + +# Paths to extra libraries +#vlsi.technology.extra_libraries_meta: ["append", "deepsubst"] +#vlsi.technology.extra_libraries: +# - library: +# nldm liberty file_deepsubst_meta: "local" +# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib" +# lef file_deepsubst_meta: "local" +# lef file: "extra_libraries/example/ExampleDCO.lef" +# gds file_deepsubst_meta: "local" +# gds file: "extra_libraries/example/ExampleDCO.gds" +# corner: +# nmos: "slow" +# pmos: "slow" +# temperature: "100 C" +# supplies: +# VDD: "0.63 V" +# GND: "0 V" +# - library: +# nldm liberty file_deepsubst_meta: "local" +# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib" +# lef file_deepsubst_meta: "local" +# lef file: "extra_libraries/example/ExampleDCO.lef" +# gds file_deepsubst_meta: "local" +# gds file: "extra_libraries/example/ExampleDCO.gds" +# corner: +# nmos: "fast" +# pmos: "fast" +# temperature: "0 C" +# supplies: +# VDD: "0.77 V" +# GND: "0 V" + +# Because the DCO is a dummy layout, we treat it as a physical-only cell +#par.inputs.physical_only_cells_mode: append +#par.inputs.physical_only_cells_list: +# - ExampleDCO + +# SRAM Compiler compiler options +vlsi.core.sram_generator_tool: "sram_compiler" +## You should specify a location for the SRAM generator in the tech plugin +vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/nangate45"] +vlsi.core.sram_generator_tool_path_meta: "append" + +# Tool options. Replace with your tool plugin of choice. +# yosys options +vlsi.core.synthesis_tool: "yosys" +vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"] +vlsi.core.synthesis_tool_path_meta: "append" + +# Innovus options +#vlsi.core.par_tool: "innovus" +#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] +#vlsi.core.par_tool_path_meta: "append" +#par.innovus.version: "181" +#par.innovus.design_flow_effort: "standard" +#par.inputs.gds_merge: true +## Calibre options +#vlsi.core.drc_tool: "calibre" +#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] +#vlsi.core.lvs_tool: "calibre" +#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] diff --git a/vlsi/example-vlsi-nangate45 b/vlsi/example-vlsi-nangate45 new file mode 100755 index 00000000..39b9a493 --- /dev/null +++ b/vlsi/example-vlsi-nangate45 @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +import os + +import hammer_vlsi +from hammer_vlsi import CLIDriver, HammerToolHookAction + +from typing import Dict, Callable, Optional, List + +def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: + x.append("") + return True + +def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: + x.append("") + return True + +class ExampleDriver(CLIDriver): + def get_extra_par_hooks(self) -> List[HammerToolHookAction]: + extra_hooks = [ + # make_pre_insertion_hook will execute the custom hook before the specified step + hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), + + # make_replacement_hook will replace the specified step with a custom hook + hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + ] + return extra_hooks + +if __name__ == '__main__': + ExampleDriver().main() diff --git a/vlsi/hammer b/vlsi/hammer index bd94e1ed..657feaed 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit bd94e1ed7a5f70fe85ea833cb89836efefe53dc7 +Subproject commit 657feaed58014f4ef5b76acaa1e0cc559f182bda From d245df91338c2dfcba34fdb6c8d5cecdc8415c82 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 18 Jun 2020 10:48:32 -0700 Subject: [PATCH 027/457] Bump Rocketchip to June 2020 for Tile changes --- generators/ariane | 2 +- generators/boom | 2 +- .../src/main/scala/ConfigFragments.scala | 86 +++----- .../chipyard/src/main/scala/DigitalTop.scala | 4 +- .../chipyard/src/main/scala/IOBinders.scala | 4 +- .../chipyard/src/main/scala/Subsystem.scala | 87 ++------ .../chipyard/src/main/scala/System.scala | 6 +- .../chipyard/src/main/scala/TestSuites.scala | 192 ++++++++++-------- .../src/main/scala/config/BoomConfigs.scala | 45 +--- .../src/main/scala/config/HeteroConfigs.scala | 70 +------ .../main/scala/config/TracegenConfigs.scala | 10 +- .../main/scala/config/TutorialConfigs.scala | 9 +- .../src/main/scala/BridgeBinders.scala | 11 +- .../src/main/scala/FireSimMulticlockPOC.scala | 20 +- .../src/main/scala/TargetConfigs.scala | 10 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 183 ++++++++++------- .../tracegen/src/main/scala/System.scala | 50 ++--- generators/tracegen/src/main/scala/Tile.scala | 114 +++++------ tools/dsptools | 2 +- 21 files changed, 375 insertions(+), 536 deletions(-) diff --git a/generators/ariane b/generators/ariane index 651134f3..0ed91074 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 651134f3c43ff8c0fa55a0f65faeb12b9500fcfa +Subproject commit 0ed9107485281545bf5abf2a042dface55e740bf diff --git a/generators/boom b/generators/boom index d77c2c3f..0b60c278 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit d77c2c3ff648bd5b18a932aa9f6b64dead7e3476 +Subproject commit 0b60c27879f8aa309537d5a535ea2c42e3dabefe diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 72eaa414..ad33fa47 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -4,20 +4,23 @@ import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Field, Parameters, Config} -import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{Debug} -import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC, RocketTileParams, MaxHartIdBits} +import freechips.rocketchip.groundtest.{GroundTestSubsystem} +import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} import freechips.rocketchip.util.{AsyncResetReg} -import boom.common.{BoomTilesKey} -import ariane.{ArianeTilesKey} import testchipip._ +import tracegen.{TraceGenSystem} import hwacha.{Hwacha} +import boom.common.{BoomTileAttachParams} +import ariane.{ArianeTileAttachParams} + import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ @@ -60,26 +63,17 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => }) class WithL2TLBs(entries: Int) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case other => other + } }) class WithTracegenSystem extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) -}) - -class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => - r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length)) - } - case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => - b.copy(hartId = i + (if(rocketFirst) up(RocketTilesKey, site).length else 0)) - } - case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) + case BuildSystem => (p: Parameters) => LazyModule(new TraceGenSystem()(p)) }) /** @@ -107,7 +101,6 @@ class WithMultiRoCC extends Config((site, here, up) => { */ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { case MultiRoCCKey => { - require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) up(MultiRoCCKey, site) ++ harts.distinct.map{ i => (i -> Seq((p: Parameters) => { LazyModule(new Hwacha()(p)).suggestName("hwacha") @@ -117,38 +110,23 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { }) -/** - * Config fragment to add a small Rocket core to the system as a "control" core. - * Used as an example of a PMU core. - */ -class WithControlCore extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site) :+ - RocketTileParams( - core = RocketCoreParams( - useVM = false, - fpu = None, - mulDiv = Some(MulDivParams(mulUnroll = 8))), - btb = None, - dcache = Some(DCacheParams( - rowBits = site(SystemBusKey).beatBits, - nSets = 64, - nWays = 1, - nTLBEntries = 4, - nMSHRs = 0, - blockBytes = site(CacheBlockBytes))), - icache = Some(ICacheParams( - rowBits = site(SystemBusKey).beatBits, - nSets = 64, - nWays = 1, - nTLBEntries = 4, - blockBytes = site(CacheBlockBytes))), - hartId = up(RocketTilesKey, site).size + up(BoomTilesKey, site).size - ) - case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) -}) - class WithTraceIO extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) - case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + trace = true)) + case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + trace = true)) + case other => other + } case TracePortKey => Some(TracePortParams()) }) + +class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case other => other + } +}) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index ae363539..81d0003d 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.devices.tilelink._ // ------------------------------------ // DOC include start: DigitalTop -class DigitalTop(implicit p: Parameters) extends System +class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -30,7 +30,7 @@ class DigitalTop(implicit p: Parameters) extends System override lazy val module = new DigitalTopModule(this) } -class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l) +class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 94fb50f4..7d1ae8fa 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters} import freechips.rocketchip.util._ +import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ @@ -20,7 +21,6 @@ import barstools.iocell.chisel._ import testchipip._ import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey} -import tracegen.{HasTraceGenTilesModuleImp} import scala.reflect.{ClassTag} @@ -389,7 +389,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: HasTraceGenTilesModuleImp) => { + (system: GroundTestSubsystemModuleImp[GroundTestSubsystem]) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 99c31472..baed154b 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -21,93 +21,36 @@ import freechips.rocketchip.util._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.amba.axi4._ -import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} -import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} +import boom.common.{BoomTile} + import testchipip.{DromajoHelper} -trait HasChipyardTiles extends HasTiles - with CanHavePeripheryPLIC - with CanHavePeripheryCLINT - with HasPeripheryDebug -{ this: BaseSubsystem => - - val module: HasChipyardTilesModuleImp - - protected val rocketTileParams = p(RocketTilesKey) - protected val boomTileParams = p(BoomTilesKey) - protected val arianeTileParams = p(ArianeTilesKey) - - // crossing can either be per tile or global (aka only 1 crossing specified) - private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) - private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) - private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size) - - val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings) - - // Make a tile and wire its nodes into the system, - // according to the specified type of clock crossing. - // Note that we also inject new nodes into the tile itself, - // also based on the crossing type. - // This MUST be performed in order of hartid - // There is something weird with registering tile-local interrupt controllers to the CLINT. - // TODO: investigate why - val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { - case (param, crossing) => { - - val tile = param match { - case r: RocketTileParams => { - LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - } - case b: BoomTileParams => { - LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - } - case a: ArianeTileParams => { - LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) - } - } - connectMasterPortsToSBus(tile, crossing) - connectSlavePortsToCBus(tile, crossing) - connectInterrupts(tile, debugOpt, clintOpt, plicOpt) - - tile - } - } - - +class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem + with HasTiles +{ def coreMonitorBundles = tiles.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle }.toList + override lazy val module = new ChipyardSubsystemModuleImp(this) } -trait HasChipyardTilesModuleImp extends HasTilesModuleImp - with HasPeripheryDebugModuleImp -{ - val outer: HasChipyardTiles -} - -class Subsystem(implicit p: Parameters) extends BaseSubsystem - with HasChipyardTiles -{ - override lazy val module = new SubsystemModuleImp(this) - - def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil -} - -class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) +class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) with HasResetVectorWire - with HasChipyardTilesModuleImp + with HasTilesModuleImp { - tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => - wire.hartid := i.U + + for (i <- 0 until outer.tiles.size) { + val wire = tile_inputs(i) + wire.hartid := outer.hartIdList(i).U wire.reset_vector := global_reset_vector } - // create file with boom params + // create file with core params ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) - // Generate C header with relevant information for Dromajo // This is included in the `dromajo_params.h` header file - DromajoHelper.addArtefacts + DromajoHelper.addArtefacts() } + diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 222ff77c..b0ae8a44 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -21,20 +21,20 @@ import freechips.rocketchip.util.{DontTouch} /** * Base top with periphery devices and ports, and a BOOM + Rocket subsystem */ -class System(implicit p: Parameters) extends Subsystem +class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port with HasPeripheryBootROM { - override lazy val module = new SystemModule(this) + override lazy val module = new ChipyardSystemModule(this) } /** * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem */ -class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer) +class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) with HasRTCModuleImp with HasExtInterruptsModuleImp with HasPeripheryBootROMModuleImp diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 9fdef05a..6edf4b03 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -2,13 +2,13 @@ package chipyard import scala.collection.mutable.{LinkedHashSet} -import freechips.rocketchip.subsystem.{RocketTilesKey} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} -import boom.common.{BoomTilesKey} -import ariane.{ArianeTilesKey} +import boom.common.{BoomTileAttachParams} +import ariane.{ArianeTileAttachParams} /** * A set of pre-chosen regression tests @@ -68,39 +68,43 @@ class TestSuiteHelper */ def addBoomTestSuites(implicit p: Parameters) = { val xlen = p(XLen) - p(BoomTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) { - addSuites(env.map(rv32ud)) + p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map { + case tp: BoomTileAttachParams => { + val tileParams = tp.tileParams + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) { + addSuites(env.map(rv32ud)) + } + } else if (cfg.fLen >= 64) { + addSuites(env.map(rv64ud)) + addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) } - } else if (cfg.fLen >= 64) { - addSuites(env.map(rv64ud)) - addSuites(env.map(rv64uf)) - addSuite(rv32udBenchmarks) } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) { - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - } else { - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) { + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + } else { + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } } - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) - addSuites(rvi.map(_("p"))) - addSuites(rvu.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites(rvu.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + case _ => } } @@ -109,37 +113,41 @@ class TestSuiteHelper */ def addRocketTestSuites(implicit p: Parameters) = { val xlen = p(XLen) - p(RocketTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv32ud)) - } else { - addSuite(rv32udBenchmarks) - addSuites(env.map(rv64uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv64ud)) + p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map { + case tp: RocketTileAttachParams => { + val tileParams = tp.tileParams + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv32ud)) + } else { + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv64ud)) + } } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - else - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) - addSuites(rvi.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + case _ => } } @@ -148,37 +156,41 @@ class TestSuiteHelper */ def addArianeTestSuites(implicit p: Parameters) = { val xlen = p(XLen) - p(ArianeTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv32ud)) - } else { - addSuite(rv32udBenchmarks) - addSuites(env.map(rv64uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv64ud)) + p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map { + case tp: ArianeTileAttachParams => { + val tileParams = tp.tileParams + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv32ud)) + } else { + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv64ud)) + } } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - else - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) - addSuites(rvi.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + case _ => } } } diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index e8358e95..7b66e3b3 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -20,8 +20,7 @@ class SmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new boom.common.WithSmallBooms ++ // small boom config - new boom.common.WithNBoomCores(1) ++ // single-core boom + new boom.common.WithNSmallBooms(1) ++ // small boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system @@ -39,8 +38,7 @@ class MediumBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithMediumBooms ++ // medium boom config - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNMediumBooms(1) ++ // medium boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -58,8 +56,7 @@ class LargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithLargeBooms ++ // large boom config - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ // large boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -77,8 +74,7 @@ class MegaBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithMegaBooms ++ // mega boom config - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNMegaBooms(1) ++ // mega boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -96,29 +92,7 @@ class DualSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - -class SmallRV32BoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithoutBoomFPU ++ // no fp - new boom.common.WithBoomRV32 ++ // rv32 (32bit) - new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNSmallBooms(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -137,8 +111,7 @@ class HwachaLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -158,8 +131,7 @@ class LoopbackNICLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -179,8 +151,7 @@ class DromajoBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNSmallBooms(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index 4388ca2b..a7d1c133 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -16,9 +16,7 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithRenumberHarts ++ // avoid hartid overlap - new boom.common.WithLargeBooms ++ // 3-wide boom - new boom.common.WithNBoomCores(1) ++ // single-core boom + new boom.common.WithNLargeBooms(1) ++ // single-core boom new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache @@ -39,9 +37,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ @@ -50,28 +46,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha - -class DualLargeBoomAndRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - // DOC include start: DualBoomAndRocketOneHwacha class LargeBoomAndHwachaRocketConfig extends Config( @@ -84,11 +58,9 @@ class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc - new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) + new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-1 (rocket) new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ @@ -99,30 +71,6 @@ class LargeBoomAndHwachaRocketConfig extends Config( // DOC include end: DualBoomAndRocketOneHwacha - -class LargeBoomAndRV32RocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - - // DOC include start: DualBoomAndRocket class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ @@ -134,9 +82,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new boom.common.WithNLargeBooms(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ @@ -155,11 +101,9 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ - new chipyard.config.WithControlCore ++ // add small control core to last hartid new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small control core + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 2a31293f..ec834f9f 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -7,7 +7,7 @@ class TraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -15,7 +15,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -23,7 +23,7 @@ class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ + new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -32,7 +32,7 @@ class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -41,7 +41,7 @@ class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index c11d103d..56e6362b 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -30,15 +30,13 @@ class TutorialStarterConfig extends Config( // of the Top new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM - new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op new chipyard.config.WithUART ++ // Add a UART // CUSTOMIZE THE CORE // Uncomment out one (or multiple) of the lines below, and choose // how many cores you want. - // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores - // new boom.common.WithSmallBooms ++ // Specify all BOOM cores should be Small-sized (NOTE: other options are Medium/Large/Mega) - // new boom.common.WithNBoomCores(1) ++ // Specify we want some number of BOOM cores + // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores + // new boom.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores // CUSTOMIZE the L2 // Uncomment this line, and specify a size if you want to have a L2 @@ -66,7 +64,6 @@ class TutorialMMIOConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ - new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ // Attach either a TileLink or AXI4 version of GCD @@ -94,7 +91,6 @@ class TutorialSha3Config extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ - new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo @@ -120,7 +116,6 @@ class TutorialSha3BlackBoxConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ - new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ // Uncomment these lines once SHA3 is integrated diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 772d0b8d..eeb19559 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -8,7 +8,7 @@ import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} @@ -21,13 +21,12 @@ import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} import midas.targetutils.{MemModelAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey -import tracegen.HasTraceGenTilesModuleImp +import tracegen.{TraceGenSystemModuleImp} import ariane.ArianeTile import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} -import chipyard.{HasChipyardTilesModuleImp} import testchipip.{CanHaveTraceIOModuleImp} object MainMemoryConsts { @@ -88,12 +87,12 @@ class WithDromajoBridge extends ComposeIOBinder({ class WithTraceGenBridge extends OverrideIOBinder({ - (system: HasTraceGenTilesModuleImp) => + (system: TraceGenSystemModuleImp) => GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (system: HasChipyardTilesModuleImp) => { + (system: HasTilesModuleImp) => { system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -110,7 +109,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ case _ => Nil } } - case a: ArianeTile => Nil + case _ => } Nil } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 1f1ae06a..bf0e0e26 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -9,11 +9,11 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossi import freechips.rocketchip.subsystem._ import freechips.rocketchip.util.{ResetCatchAndSync} -import boom.common.{BoomTilesKey, BoomCrossingKey} - import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} import firesim.configs._ +import boom.common.{WithRationalBoomTiles} + import chipyard.{BuildSystem, DigitalTop, DigitalTopModule} import chipyard.config.ConfigValName._ import chipyard.iobinders.{IOBinders} @@ -51,15 +51,13 @@ trait HasFireSimClockingImp extends HasAdditionalClocks { } // Config Fragment -class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) - case RocketCrossingKey => up(RocketCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } - case BoomCrossingKey => up(BoomCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } -}) +class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config( + new WithRationalRocketTiles ++ + new WithRationalBoomTiles ++ + new Config((site, here, up) => { + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) + }) +) class HalfRateUncore extends WithSingleRationalTileDomain(2,1) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 63b4d2fe..2828580a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -13,13 +13,11 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.LazyModule -import boom.common.BoomTilesKey import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} -import tracegen.TraceGenKey + import icenet._ -import ariane.ArianeTilesKey import testchipip.WithRingSystemBus import firesim.bridges._ @@ -44,12 +42,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) }) -class WithPerfCounters extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy(nPerfCounters = 29) - )) -}) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) diff --git a/generators/rocket-chip b/generators/rocket-chip index 1872f5d5..1cec6e69 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 1872f5d501221f13950aa2293939634a1e0d1735 +Subproject commit 1cec6e697ce9ea8ffa13a6d95e0734946db3adb1 diff --git a/generators/testchipip b/generators/testchipip index bb038fea..26891fac 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bb038feaa1db73bffb3fca55c6d24cb0109875bd +Subproject commit 26891fac1d40c31348b6e6f16d730de705707094 diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index c22b0e3d..01b23b24 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -3,87 +3,126 @@ package tracegen import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.groundtest.{TraceGenParams} -import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey} +import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.BaseConfig import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.tile.{MaxHartIdBits, XLen} import scala.math.{max, min} -class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val nSets = dcp.nSets - val nWays = dcp.nWays - val blockOffset = site(SystemBusKey).blockOffset - val nBeats = min(2, site(SystemBusKey).blockBeats) - val beatBytes = site(SystemBusKey).beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) +class WithTraceGen( + n: Int = 2, + overrideIdOffset: Option[Int] = None, + overrideMemOffset: Option[BigInt] = None)( + params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, + nReqs: Int = 8192 +) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) + params.zipWithIndex.map { case (dcp, i) => + TraceGenTileAttachParams( + tileParams = TraceGenParams( + hartId = i + idOffset, + dcache = Some(dcp), + wordBits = site(XLen), + addrBits = 48, + addrBag = { + val nSets = dcp.nSets + val nWays = dcp.nWays + val blockOffset = site(SystemBusKey).blockOffset + val nBeats = min(2, site(SystemBusKey).blockBeats) + val beatBytes = site(SystemBusKey).beatBytes + List.tabulate(2 * nWays) { i => + Seq.tabulate(nBeats) { j => + BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) + } + }.flatten + }, + maxRequests = nReqs, + memStart = memOffset, + numGens = params.size), + crossingParams = RocketCrossingParams() + ) + } ++ prev } - case MaxHartIdBits => log2Ceil(params.size + up(BoomTraceGenKey, site).length) max 1 }) -class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case BoomTraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val nSets = dcp.nSets - val nWays = dcp.nWays - val blockOffset = site(SystemBusKey).blockOffset - val nBeats = min(2, site(SystemBusKey).blockBeats) - val beatBytes = site(SystemBusKey).beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) +class WithBoomTraceGen( + n: Int = 2, + overrideIdOffset: Option[Int] = None, + overrideMemOffset: Option[BigInt] = None)( + params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) }, + nReqs: Int = 8192 +) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) + params.zipWithIndex.map { case (dcp, i) => + BoomTraceGenTileAttachParams( + tileParams = BoomTraceGenParams( + hartId = i + idOffset, + dcache = Some(dcp), + wordBits = site(XLen), + addrBits = 48, + addrBag = { + val nSets = dcp.nSets + val nWays = dcp.nWays + val blockOffset = site(SystemBusKey).blockOffset + val nBeats = site(SystemBusKey).blockBeats + List.tabulate(nWays) { i => + Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) } + }.flatten + }, + maxRequests = nReqs, + memStart = memOffset, + numGens = params.size), + crossingParams = RocketCrossingParams() + ) + } ++ prev } - case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1 }) -class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val sbp = site(SystemBusKey) - val l2p = site(InclusiveCacheKey) - val nSets = max(l2p.sets, dcp.nSets) - val nWays = max(l2p.ways, dcp.nWays) - val blockOffset = sbp.blockOffset - val nBeats = min(2, sbp.blockBeats) - val beatBytes = sbp.beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size) -}) +class WithL2TraceGen( + n: Int = 2, + overrideIdOffset: Option[Int] = None, + overrideMemOffset: Option[BigInt] = None)( + params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, + nReqs: Int = 8192 +) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) + params.zipWithIndex.map { case (dcp, i) => + TraceGenTileAttachParams( + tileParams = TraceGenParams( + hartId = i + idOffset, + dcache = Some(dcp), + wordBits = site(XLen), + addrBits = 48, + addrBag = { + val sbp = site(SystemBusKey) + val l2p = site(InclusiveCacheKey) + val nSets = max(l2p.sets, dcp.nSets) + val nWays = max(l2p.ways, dcp.nWays) + val blockOffset = sbp.blockOffset + val nBeats = min(2, sbp.blockBeats) + val beatBytes = sbp.beatBytes + List.tabulate(2 * nWays) { i => + Seq.tabulate(nBeats) { j => + BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) + } + }.flatten + }, + maxRequests = nReqs, + memStart = memOffset, + numGens = params.size), + crossingParams = RocketCrossingParams() + ) + } ++ prev + } +}) diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 1653ba79..d6b72d4a 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -3,48 +3,26 @@ package tracegen import chisel3._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} -import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams} +import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} +import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile} import freechips.rocketchip.subsystem._ -case object BoomTraceGenKey extends Field[Seq[TraceGenParams]](Nil) -case object TraceGenKey extends Field[Seq[TraceGenParams]](Nil) - -trait HasTraceGenTiles { this: BaseSubsystem => - val rocket_tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) => - LazyModule(new TraceGenTile(i, params, p)) - } - val boom_tiles = p(BoomTraceGenKey).zipWithIndex.map { case (params, i) => - LazyModule(new BoomTraceGenTile(i, params, p)) - } - - val tiles = rocket_tiles ++ boom_tiles - - tiles.foreach { t => - sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode } - } -} - -trait HasTraceGenTilesModuleImp extends LazyModuleImp { - val outer: HasTraceGenTiles - val success = IO(Output(Bool())) - - outer.tiles.zipWithIndex.map { case(t, i) => - t.module.constants.hartid := i.U - } - - val status = DebugCombiner( - outer.rocket_tiles.map(_.module.status) ++ - outer.boom_tiles.map(_.module.status) - ) - success := status.finished -} - class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem - with HasTraceGenTiles + with HasTiles with CanHaveMasterAXI4MemPort { + + def coreMonitorBundles = Nil override lazy val module = new TraceGenSystemModuleImp(this) } class TraceGenSystemModuleImp(outer: TraceGenSystem) extends BaseSubsystemModuleImp(outer) - with HasTraceGenTilesModuleImp +{ + val success = IO(Output(Bool())) + + outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U } + + val status = dontTouch(DebugCombiner(outer.tiles.collect { case t: GroundTestTile => t.module.status })) + success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR + +} diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index d395211f..329203e2 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -3,36 +3,17 @@ package tracegen import chisel3._ import chisel3.util._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing} -import freechips.rocketchip.groundtest.{TraceGenerator, TraceGenParams, DummyPTW, GroundTestStatus} -import freechips.rocketchip.rocket.{DCache, NonBlockingDCache, SimpleHellaCacheIF, HellaCacheExceptions, HellaCacheReq, HellaCacheIO} +import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing, ClockCrossingType} +import freechips.rocketchip.groundtest._ +import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.constants.{MemoryOpConstants} -import freechips.rocketchip.tile.{BaseTile, BaseTileModuleImp, HartsWontDeduplicate, TileKey} -import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode} import freechips.rocketchip.interrupts._ - +import freechips.rocketchip.subsystem._ import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} -class TraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters) - extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) { - val dcache = params.dcache.map { dc => LazyModule( - if (dc.nMSHRs == 0) new DCache(hartId, crossing) - else new NonBlockingDCache(hartId)) - }.get - - val intInwardNode: IntInwardNode = IntIdentityNode() - val intOutwardNode: IntOutwardNode = IntIdentityNode() - val slaveNode: TLInwardNode = TLIdentityNode() - val ceaseNode: IntOutwardNode = IntIdentityNode() - val haltNode: IntOutwardNode = IntIdentityNode() - val wfiNode: IntOutwardNode = IntIdentityNode() - - val masterNode = visibilityNode - masterNode := dcache.node - - override lazy val module = new TraceGenTileModuleImp(this) -} class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) with MemoryOpConstants { @@ -179,32 +160,58 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) } -class BoomTraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters) - extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) { +case class BoomTraceGenTileAttachParams( + tileParams: BoomTraceGenParams, + crossingParams: TileCrossingParamsLike +) extends CanAttachTile { + type TileType = BoomTraceGenTile + val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams) +} + + +case class BoomTraceGenParams( + wordBits: Int, + addrBits: Int, + addrBag: List[BigInt], + maxRequests: Int, + memStart: BigInt, + numGens: Int, + dcache: Option[DCacheParams] = Some(DCacheParams()), + hartId: Int = 0 +) extends InstantiableTileParams[BoomTraceGenTile] with GroundTestTileParams +{ + def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = { + new BoomTraceGenTile(this, crossing, lookup) + } + val beuAddr = None + val blockerCtrlAddr = None + val name = None + val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId) +} + +class BoomTraceGenTile private( + val params: BoomTraceGenParams, + crossing: ClockCrossingType, + lookup: LookupByHartIdImpl, + q: Parameters) extends GroundTestTile(params, crossing, lookup, q) +{ + def this(params: BoomTraceGenParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + this(params, crossing.crossingType, lookup, p) + val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false)))) val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params)) - val intInwardNode: IntInwardNode = IntIdentityNode() - val intOutwardNode: IntOutwardNode = IntIdentityNode() - val slaveNode: TLInwardNode = TLIdentityNode() - val ceaseNode: IntOutwardNode = IntIdentityNode() - val haltNode: IntOutwardNode = IntIdentityNode() - val wfiNode: IntOutwardNode = IntIdentityNode() - - val masterNode = visibilityNode - masterNode := dcache.node + val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) override lazy val module = new BoomTraceGenTileModuleImp(this) } class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) - extends BaseTileModuleImp(outer){ + extends GroundTestTileModuleImp(outer){ - val status = IO(new GroundTestStatus) - - val tracegen = Module(new TraceGenerator(outer.params)) + val tracegen = Module(new TraceGenerator(outer.params.traceParams)) tracegen.io.hartid := constants.hartid val ptw = Module(new DummyPTW(1)) @@ -219,31 +226,14 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) lsu.io.hellacache := DontCare lsu.io.hellacache.req.valid := false.B - status.finished := tracegen.io.finished - status.timeout.valid := tracegen.io.timeout - status.timeout.bits := 0.U - status.error.valid := false.B -} + outer.reportCease(Some(tracegen.io.finished)) + outer.reportHalt(Some(tracegen.io.timeout)) + outer.reportWFI(None) -class TraceGenTileModuleImp(outer: TraceGenTile) - extends BaseTileModuleImp(outer) { - val status = IO(new GroundTestStatus) - val halt_and_catch_fire = None - - val ptw = Module(new DummyPTW(1)) - ptw.io.requestors.head <> outer.dcache.module.io.ptw - - val tracegen = Module(new TraceGenerator(outer.params)) - tracegen.io.hartid := constants.hartid - - val dcacheIF = Module(new SimpleHellaCacheIF()) - dcacheIF.io.requestor <> tracegen.io.mem - outer.dcache.module.io.cpu <> dcacheIF.io.cache - - status.finished := tracegen.io.finished status.timeout.valid := tracegen.io.timeout status.timeout.bits := 0.U status.error.valid := false.B - assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out") + assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out") + } diff --git a/tools/dsptools b/tools/dsptools index 211166e6..e32ab8a0 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 211166e635861fb1937828aee38c166baf0840b5 +Subproject commit e32ab8a0c77d419b52376064534090ff2583929d From f87522bf0e47cf179e8920f44d239b96cf7b14aa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 18 Jun 2020 17:36:51 -0700 Subject: [PATCH 028/457] Fix AXI4 IOBinder for multi-channel systems --- generators/chipyard/src/main/scala/IOBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 7d1ae8fa..18da543e 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -185,9 +185,9 @@ object AddIOCells { } def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { - io.zip(node.in).map{ case (mem_axi4, (_, edge)) => { - val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some("iocell_mem_axi4")) - port.suggestName("mem_axi4") + io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { + val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}")) + port.suggestName(s"mem_axi4_${i}") (port, edge, ios) }} } From a9d349cb851713d41064ce1a889fc7836bc4c62a Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 18 Jun 2020 01:31:15 -0700 Subject: [PATCH 029/457] Emit htif node in device tree --- .../chipyard/src/main/scala/Subsystem.scala | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 99c31472..c22bbbee 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} @@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} -import testchipip.{DromajoHelper} +import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey} trait HasChipyardTiles extends HasTiles with CanHavePeripheryPLIC @@ -87,8 +87,29 @@ trait HasChipyardTilesModuleImp extends HasTilesModuleImp val outer: HasChipyardTiles } +trait CanHaveHTIF { this: BaseSubsystem => + // Advertise HTIF if system can communicate with fesvr + if (this match { + case _: CanHavePeripherySerial if p(SerialKey) => true + case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true + case _ => false + }) { + ResourceBinding { + val htif = new Device { + def describe(resources: ResourceBindings): Description = { + val compat = resources("compat").map(_.value) + Description("htif", Map( + "compatible" -> compat)) + } + } + Resource(htif, "compat").bind(ResourceString("ucb,htif0")) + } + } +} + class Subsystem(implicit p: Parameters) extends BaseSubsystem with HasChipyardTiles + with CanHaveHTIF { override lazy val module = new SubsystemModuleImp(this) From 254304428bfcce91dd9c396c9fdcb7c7a12c135f Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Fri, 19 Jun 2020 12:03:59 -0700 Subject: [PATCH 030/457] refactored openroad stuff into OpenROADTool base class. fixed PR suggestions --- vlsi/Makefile | 22 +++++++++++----------- vlsi/example-nangate45.yml | 3 ++- vlsi/hammer | 2 +- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 912eecdd..e969ba14 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -20,28 +20,28 @@ include $(base_dir)/variables.mk sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ - $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ - $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) + $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ + $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ - --mode synflops,\ - -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) + --mode synflops,\ + -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ - example-nangate45.yml,\ - example.yml) + example-nangate45.yml,\ + example.yml) HAMMER_EXEC ?= $(if $(filter $(tech_name),nangate45),\ - example-vlsi-nangate45,\ - example-vlsi) + example-vlsi-nangate45,\ + example-vlsi) VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build -ifneq ($(CUSTOM_VLOG), ) - OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) +ifneq ($(CUSTOM_VLOG),) + OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) else - OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) + OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) endif ######################################################################################### diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index de4d912f..b4c1288a 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -1,7 +1,8 @@ # Technology Setup -# Technology used is nanagate45 vlsi.core.technology: nangate45 + # Specify dir with ASAP7 tarball +# TODO: figure out how to remove this, or override it within OpenROADTool technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" vlsi.core.max_threads: 12 diff --git a/vlsi/hammer b/vlsi/hammer index 657feaed..c5a3cdf8 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 657feaed58014f4ef5b76acaa1e0cc559f182bda +Subproject commit c5a3cdf84987a46c91f3f879541060757bf225fb From c5c272b90dbc3532de5429056cd43c30dc28c25c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 19 Jun 2020 13:51:57 -0700 Subject: [PATCH 031/457] Custom core doc first draft --- docs/Customization/Custom-Core.rst | 286 ++++++++++++++++++++++ docs/Customization/Heterogeneous-SoCs.rst | 2 + docs/Customization/index.rst | 2 + 3 files changed, 290 insertions(+) create mode 100644 docs/Customization/Custom-Core.rst diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst new file mode 100644 index 00000000..bffdc236 --- /dev/null +++ b/docs/Customization/Custom-Core.rst @@ -0,0 +1,286 @@ +.. _custom_core: + +Adding a custom core +==================== + +You may want to add a custom RISC-V core to Chipyard generator. If the top module of your core is not in Chisel, +you will first need to create a Verilog blackbox for it. See ::ref:`_incorporating-verilog-blocks` for instructions. +Once you have a top module in Chisel, you are ready to create integrate it with Chipyard. + +.. note:: + + RoCC is not supported by custom core currently. Please use Rocket or Boom if you need to use RoCC. + +.. note:: + + Custom core doesn't support FireSim at this time. + +Parameter Case Classes +---------------------- + +Chipyard will generate a core for every ``TileParams`` object it discovered in the current config. +``TileParams`` is a trait containing the information needed to create a tile, and every custom core must implement +their own version of ``TileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``. + +``TileParams`` holds the parameters that are the same for every generated core, while ``CoreParams`` contains those +that can vary from cores to cores. They must be implemented as case classes with fields that can be overridden by +other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of +variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. + +Now you have your parameter classes, you will need config keys to hold them. There are two required keys: + +.. code-block:: scala + + case object MyTilesKey extends Field[Seq[MyTileParams]](Nil) + case object MyCrossingKey extends Field[Seq[RocketCrossingParams]](List(RocketCrossingParams())) + +``MyCrossingKey`` here is used to store information about the clock-crossing behavior of the core, and it is normally +set to its default values. + +``TileParams`` and ``CoreParams`` contains the following fields: + +.. code-block:: scala + + trait TileParams { + val core: CoreParams // Core parameters (see below) + val icache: Option[ICacheParams] // Not used if you use your own I1 cache + val dcache: Option[DCacheParams] // Not used if you use your own D1 cache + val btb: Option[BTBParams] // Not used if you use your own BTB / branch predictor + val hartId: Int // Hart ID: Must be unique within a design config + val beuAddr: Option[BigInt] + val blockerCtrlAddr: Option[BigInt] + val name: Option[String] // Name of the core + } + + trait CoreParams { + val bootFreqHz: BigInt // Frequency + val useVM: Boolean // Support virtual memory + val useUser: Boolean // Support user mode + val useSupervisor: Boolean // Support supervisor mode + val useDebug: Boolean // Support RISC-V debug specs + val useAtomics: Boolean // Support A extension + val useAtomicsOnlyForIO: Boolean // Support A extension for memory-mapped IO (may be true even if useAtomics is false) + val useCompressed: Boolean // Support C extension + val useVector: Boolean = false // Support V extension + val useSCIE: Boolean + val useRVE: Boolean + val mulDiv: Option[MulDivParams] // M extension and related setting (Only used by Rocket core, simply use its default value) + val fpu: Option[FPUParams] // F and D extensions and related setting (see below) + val fetchWidth: Int // Max # of insts fetched every cycle + val decodeWidth: Int // Max # of insts decoded every cycle + val retireWidth: Int // Max # of insts retired every cycle + val instBits: Int // Instruction bits (if 32 bit and 64 bit are both supported, use 64) + val nLocalInterrupts: Int // # of local interrupts (see SiFive interrupt cookbook) + val nPMPs: Int // # of Physical Memory Protection units + val pmpGranularity: Int // Size of the smallest unit of region for PMP unit (must be power of 2) + val nBreakpoints: Int // # of breakpoints supported (in RISC-V debug specs) + val useBPWatch: Boolean + val nPerfCounters: Int // # of supported performance counters + val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension + val haveFSDirty: Boolean + val misaWritable: Boolean // Support writable misa CSR (like variable instruction bits) + val haveCFlush: Boolean + val nL2TLBEntries: Int // # of L2 TLB entries + val mtvecInit: Option[BigInt] // mtvec CSR (of V extension) initial value + val mtvecWritable: Boolean // If mtvec CSR is writable + + // Normally, you don't need to change these values (except lrscCycles) + def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs + + def hasSupervisorMode: Boolean = useSupervisor || useVM + def instBytes: Int = instBits / 8 + def fetchBytes: Int = fetchWidth * instBytes + // This field is used only with the D1 cache of Rocket chip. Simply set it to the default value 80. + def lrscCycles: Int + + def dcacheReqTagBits: Int = 6 + + def minFLen: Int = 32 + def vLen: Int = 0 + def sLen: Int = 0 + def eLen(xLen: Int, fLen: Int): Int = xLen max fLen + def vMemDataBits: Int = 0 + } + + case class FPUParams( + minFLen: Int = 32, // Minimum floating point length (no need to change) + fLen: Int = 64, // Maximum floating point length, use 32 if only single precision is supported + divSqrt: Boolean = true, // Div/Sqrt operation supported + sfmaLatency: Int = 3, // + dfmaLatency: Int = 4 + ) + +Most of the fields here are originally designed for Rocket core and contains some architecture-specific details, but +many of them are general enough to be useful for other cores. It is strongly recommended to use these fields instead +of creating your own custom fields when applicable. + +Tile Class +---------- + +In Chipyard, all connections with other components on SoC are defined a core's `Tile` class, while the implementation +of the actual hardware are in the implementation class. This structure allows Chipyard to use the Diplomacy framework +to resolve paramters and connections before elaboration. + +All tile classes implement ``BaseTile`` and will normally implement ``SinksExternalInterrupts`` and ``SourcesExternalNotifications``, +which allow the tile to accept external interrupt. A typical tile has the following form: + +.. code-block:: scala + + class MyTile( + val myParams: MyTileParams, + crossing: ClockCrossingType, + lookup: LookupByHartIdImpl, + q: Parameters, + logicalTreeNode: LogicalTreeNode) + extends BaseTile(myParams, crossing, lookup, q) + with SinksExternalInterrupts + with SourcesExternalNotifications + { + + // Private constructor ensures altered LazyModule.p is used implicitly + def this(params: MyTileParams, crossing: RocketCrossingParams, lookup: LookupByHartIdImpl, logicalTreeNode: LogicalTreeNode)(implicit p: Parameters) = + this(params, crossing.crossingType, lookup, p, logicalTreeNode) + + // Require TileLink nodes + val intOutwardNode = IntIdentityNode() + val masterNode = visibilityNode + val slaveNode = TLIdentityNode() + + // Implementation class (See below) + override lazy val module = new MyTileModuleImp(this) + + // Required entry of CPU device in the device tree for interrupt purpose + val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("my-organization,my-cpu", "riscv")) { + override def parent = Some(ResourceAnchors.cpus) + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + Description(name, mapping ++ + cpuProperties ++ + nextLevelCacheProperty ++ + tileProperties) + } + } + + ResourceBinding { + Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) + } + + // (Connection to bus, interrupt, etc.) + } + +TileLink Connection +------------------- + +Chipyard use TileLink as its onboard bus protocol, and if your core doesn't use TileLink, you will need to convert them +in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus: + +.. code-block:: scala + + val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node + (tlMasterXbar.node // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar + := memoryTap + := TLBuffer() + := TLFIFOFixer(TLFIFOFixer.all) // fix FIFO ordering + := TLWidthWidget(beatBytes) // reduce size of TL + := AXI4ToTL() // convert to TL + := AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed + := AXI4Fragmenter() // deal with multi-beat xacts + := memAXI4Node) // The custom node, see below + +Remember, you may not need all of these intermediate widgets. See :::ref:`Diplomatic-Widgets` for the meaning of each intermediate +widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Also, Chipyard +support AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol. See the reference page for +more info. + +``memAXI4Node`` is an AXI4 master node and is defined as following in our example: + +.. code-block:: scala + + val memAXI4Node = AXI4MasterNode( + Seq(AXI4MasterPortParameters( + masters = Seq(AXI4MasterParameters( + name = portName, + id = IdRange(0, 1 << idBits)))))) + +where ``portName`` and ``idBits`` are the parameter provides by the tile. Make sure to read :::ref:`node-tyoes` to check out what +type of nodes Chipyard supports and their parameters! + +Also, by default, there are boundary buffers for both master and slave connections to the bus when they are leaving the tile, and you +can override the following two functions to control how to buffer the bus requests/responses: + +.. code-block:: scala + + protected def makeMasterBoundaryBuffers(implicit p: Parameters): TLBuffer + protected def makeSlaveBoundaryBuffers(implicit p: Parameters): TLBuffer + +Interrupt +--------- + +Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. +In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and +call ``decodeCoreInterrupts`` with the object as the argument. You can then read the interrupt bits from the object. +The definition of ``TileInterrupts`` is + +.. code-block:: scala + + class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { + val debug = Bool() // debug interrupt + val mtip = Bool() // Machine level timer interrupt + val msip = Bool() // Machine level software interrupt + val meip = Bool() // Machine level external interrupt + val seip = usingSupervisor.option(Bool()) // Valid only if supervisor mode is supported + val lip = Vec(coreParams.nLocalInterrupts, Bool()) // Local interrupts + } + +This function should be in the implementation class since it involves hardware generation. +Also, the tile can also notify other cores or devices for some events by calling following functions (in implementation class): + +.. code-block:: scala + + def reportHalt(could_halt: Option[Bool]) // Triggered when there is an unrecoverable hardware error (halt the machine) + def reportHalt(errors: Seq[CanHaveErrors]) // Varient for standard error bundle (used only by cache when there's an ECC error) + reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) + reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruciton is executed + +Implementation Class +-------------------- + +The implementation class is of the following form: + +.. code-block:: scala + + class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ + // annotate the parameters + Annotated.params(this, outer.tileParams) + + // TODO: Create the top module of the core and connect it with the ports in "outer" + } + +In the body of this class, you can look up any parameters by calling ``p({key})``, where ``{key}`` is the config key of +the value you want to look up. For a list of available keys, see the appendix below. + +If you create an AXI4 node (or equivalents), you will need to connect them to your core. + +Integrate the Core +------------------ + +To use your core in a set of config, you would need a config fragment that would create a ``TileParams`` object of your core in +the current config. An example of such config will be like this: + +.. code-block:: scala + + class WithNMyCores(n: Int) extends Config( + new RegisterCore(new CoreEntry[MyTileParams, MyTile]("MyCore", MyTilesKey, MyCrossingKey)) ++ + new Config((site, here, up) => { + case MyTilesKey => { + List.tabulate(n)(i => MyTileParams(hartId = i)) + } + }) + ) + +Where ``RegisterCore`` will register the core with chipyard so that it can be recognized by generic config. This is required for +all custom cores. You can also create other config fragments to change other parameters. + +Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions +in :::ref:`_custom_chisel` to add your project to the build system, then create a config by following the steps in :::ref:`_hetero_socs_`. +You can now run any desired workflow for the new config just as you do for the built-in cores. diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index c640e31c..204b3159 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -1,3 +1,5 @@ +.. _hetero_socs_: + Heterogeneous SoCs =============================== diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index 9421b79a..38fdf622 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -7,6 +7,8 @@ These guides will walk you through customization of your system-on-chip: - How to include your custom Chisel sources in the Chipyard build system +- Adding custom core + - Adding custom RoCC accelerators to an existing Chipyard core (BOOM or Rocket) - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs From 2bfc4f6dd443df68b40de5c694c31c9eb3e4e3dc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jun 2020 14:44:07 -0700 Subject: [PATCH 032/457] More fixes for RC bump --- generators/boom | 2 +- .../src/main/scala/config/TracegenConfigs.scala | 10 +++++----- generators/testchipip | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/generators/boom b/generators/boom index 0b60c278..96ac46f6 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 0b60c27879f8aa309537d5a535ea2c42e3dabefe +Subproject commit 96ac46f60261a98f1f1fa62fbd6a2fe9df5ba4bb diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index ec834f9f..e8aeeb29 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -9,7 +9,7 @@ class TraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -17,7 +17,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -26,7 +26,7 @@ class BoomTraceGenConfig extends Config( new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -35,7 +35,7 @@ class NonBlockingTraceGenL2Config extends Config( new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -45,4 +45,4 @@ class NonBlockingTraceGenL2RingConfig extends Config( new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) diff --git a/generators/testchipip b/generators/testchipip index 26891fac..29eb87c9 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 26891fac1d40c31348b6e6f16d730de705707094 +Subproject commit 29eb87c938a2106249b85e3b3dffd00046f5077c From c407e39cd8c9a4a8dd2e2f19138174cc4cd6dffb Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sat, 20 Jun 2020 01:04:56 -0700 Subject: [PATCH 033/457] Completed most documentation (without AXI4 bus) --- docs/Customization/Custom-Core.rst | 78 ++++++++++++++++++++++-------- 1 file changed, 57 insertions(+), 21 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index bffdc236..5a5cc627 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -11,10 +11,6 @@ Once you have a top module in Chisel, you are ready to create integrate it with RoCC is not supported by custom core currently. Please use Rocket or Boom if you need to use RoCC. -.. note:: - - Custom core doesn't support FireSim at this time. - Parameter Case Classes ---------------------- @@ -37,18 +33,19 @@ Now you have your parameter classes, you will need config keys to hold them. The ``MyCrossingKey`` here is used to store information about the clock-crossing behavior of the core, and it is normally set to its default values. -``TileParams`` and ``CoreParams`` contains the following fields: +``TileParams`` and ``CoreParams`` contains the following fields (you may ignore any fields marked "Rocket specific" and +use their default values, although it is recommended to use them if you need a custom field with similar purposes) : .. code-block:: scala trait TileParams { val core: CoreParams // Core parameters (see below) - val icache: Option[ICacheParams] // Not used if you use your own I1 cache - val dcache: Option[DCacheParams] // Not used if you use your own D1 cache - val btb: Option[BTBParams] // Not used if you use your own BTB / branch predictor + val icache: Option[ICacheParams] // Rocket specific: I1 cache option + val dcache: Option[DCacheParams] // Rocket specific: D1 cache option + val btb: Option[BTBParams] // Rocket specific: BTB / branch predictor option val hartId: Int // Hart ID: Must be unique within a design config - val beuAddr: Option[BigInt] - val blockerCtrlAddr: Option[BigInt] + val beuAddr: Option[BigInt] // Rocket specific: Bus Error Unit for Rocket Core + val blockerCtrlAddr: Option[BigInt] // Rocket specific: Bus Blocker for Rocket Core val name: Option[String] // Name of the core } @@ -62,9 +59,9 @@ set to its default values. val useAtomicsOnlyForIO: Boolean // Support A extension for memory-mapped IO (may be true even if useAtomics is false) val useCompressed: Boolean // Support C extension val useVector: Boolean = false // Support V extension - val useSCIE: Boolean - val useRVE: Boolean - val mulDiv: Option[MulDivParams] // M extension and related setting (Only used by Rocket core, simply use its default value) + val useSCIE: Boolean // Support custom instructions (in custom-0 and custom-1) + val useRVE: Boolean // Use E base ISA + val mulDiv: Option[MulDivParams] // *Rocket specific: M extension related setting (Use Some(MulDivParams()) to indicate M extension supported) val fpu: Option[FPUParams] // F and D extensions and related setting (see below) val fetchWidth: Int // Max # of insts fetched every cycle val decodeWidth: Int // Max # of insts decoded every cycle @@ -73,13 +70,13 @@ set to its default values. val nLocalInterrupts: Int // # of local interrupts (see SiFive interrupt cookbook) val nPMPs: Int // # of Physical Memory Protection units val pmpGranularity: Int // Size of the smallest unit of region for PMP unit (must be power of 2) - val nBreakpoints: Int // # of breakpoints supported (in RISC-V debug specs) - val useBPWatch: Boolean + val nBreakpoints: Int // # of hardware breakpoints supported (in RISC-V debug specs) + val useBPWatch: Boolean // Support hardware breakpoints val nPerfCounters: Int // # of supported performance counters val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension - val haveFSDirty: Boolean + val haveFSDirty: Boolean // If true, the core will set FS field in mstatus CSR to dirty when appropriate val misaWritable: Boolean // Support writable misa CSR (like variable instruction bits) - val haveCFlush: Boolean + val haveCFlush: Boolean // Rocket specific: enables Rocket's custom instruction extension to flush the cache val nL2TLBEntries: Int // # of L2 TLB entries val mtvecInit: Option[BigInt] // mtvec CSR (of V extension) initial value val mtvecWritable: Boolean // If mtvec CSR is writable @@ -90,7 +87,7 @@ set to its default values. def hasSupervisorMode: Boolean = useSupervisor || useVM def instBytes: Int = instBits / 8 def fetchBytes: Int = fetchWidth * instBytes - // This field is used only with the D1 cache of Rocket chip. Simply set it to the default value 80. + // Rocket specific: Longest possible latency of Rocket core D1 cache. Simply set it to the default value 80. def lrscCycles: Int def dcacheReqTagBits: Int = 6 @@ -106,8 +103,8 @@ set to its default values. minFLen: Int = 32, // Minimum floating point length (no need to change) fLen: Int = 64, // Maximum floating point length, use 32 if only single precision is supported divSqrt: Boolean = true, // Div/Sqrt operation supported - sfmaLatency: Int = 3, // - dfmaLatency: Int = 4 + sfmaLatency: Int = 3, // Rocket specific: Fused multiply-add pipeline latency (single precision) + dfmaLatency: Int = 4 // Rocket specific: Fused multiply-add pipeline latency (double precision) ) Most of the fields here are originally designed for Rocket core and contains some architecture-specific details, but @@ -213,6 +210,8 @@ can override the following two functions to control how to buffer the bus reques protected def makeMasterBoundaryBuffers(implicit p: Parameters): TLBuffer protected def makeSlaveBoundaryBuffers(implicit p: Parameters): TLBuffer +You can find more information on ``TLBuffer`` in :::ref:`Diplomatic-Widgets`. + Interrupt --------- @@ -240,7 +239,40 @@ Also, the tile can also notify other cores or devices for some events by calling def reportHalt(could_halt: Option[Bool]) // Triggered when there is an unrecoverable hardware error (halt the machine) def reportHalt(errors: Seq[CanHaveErrors]) // Varient for standard error bundle (used only by cache when there's an ECC error) reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) - reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruciton is executed + reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed + +Trace (Optional) +---------------- + +Chipyard provides a set of ports for instruction trace that conforms with related RISC-V standard. +If you are using FireSim, it is recommended to implement these trace ports to enable FireSim to read trace. + +There are one inbound node ``traceAuxSinkNode.bundle: TraceAux`` and two outbound nodes ``traceCoreSourceNode.bundle: TraceCoreInterface`` +and ``bpwatchSourceNode.bundle: Vec[BPWatch]``. Note that the length of ``bpwatchSourceNode`` is equal to the max number of +breakpoints (set by ``nBreakpoints`` in ``CoreParams``). Below is the definition of these types: + +.. code-block:: scala + + // Control signal from the external tracer + class TraceAux extends Bundle { + val enable = Bool() // Enable trace output + val stall = Bool() // If true, the core should stall + } + // Check RISC-V Processor Trace spec V1.0 for more information of this interface + class TraceCoreInterface (val params: TraceCoreParams) extends Bundle { + val group = Vec(params.nGroups, new TraceCoreGroup(params)) + val priv = UInt(4.W) + val tval = UInt(params.xlen.W) + val cause = UInt(params.xlen.W) + } + // Address Breakpoint and watchpoint info (n is the retire width) + class BPWatch (val n: Int) extends Bundle() { + val valid = Vec(n, Bool()) // Valid bit of the output + val rvalid = Vec(n, Bool()) // Break on read + val wvalid = Vec(n, Bool()) // Break on write + val ivalid = Vec(n, Bool()) // Break on execute + val action = UInt(3.W) // Exception code (3 usually) + } Implementation Class -------------------- @@ -261,6 +293,10 @@ the value you want to look up. For a list of available keys, see the appendix be If you create an AXI4 node (or equivalents), you will need to connect them to your core. +.. warning:: + + TODO: Documenting bus connection + Integrate the Core ------------------ From a1cc62b85aa4a53c5c69c1e9114ab0aafed8446f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jun 2020 19:18:33 -0700 Subject: [PATCH 034/457] Bump Rocket-chip again --- .../chipyard/src/main/scala/IOBinders.scala | 3 ++- generators/rocket-chip | 2 +- .../tracegen/src/main/scala/System.scala | 5 ++++- generators/tracegen/src/main/scala/Tile.scala | 22 ++++++++++++++----- 4 files changed, 24 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 18da543e..1a366d19 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -16,6 +16,7 @@ import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTest import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ +import tracegen.{TraceGenSystemModuleImp} import barstools.iocell.chisel._ @@ -389,7 +390,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: GroundTestSubsystemModuleImp[GroundTestSubsystem]) => { + (system: TraceGenSystemModuleImp) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } diff --git a/generators/rocket-chip b/generators/rocket-chip index 1cec6e69..653efa99 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 1cec6e697ce9ea8ffa13a6d95e0734946db3adb1 +Subproject commit 653efa99a27dc155bd4b4706a7e71c5c930f62b1 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index d6b72d4a..ca3572d7 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -22,7 +22,10 @@ class TraceGenSystemModuleImp(outer: TraceGenSystem) outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U } - val status = dontTouch(DebugCombiner(outer.tiles.collect { case t: GroundTestTile => t.module.status })) + val status = dontTouch(DebugCombiner(outer.tiles.collect { + case t: GroundTestTile => t.module.status + case t: BoomTraceGenTile => t.module.status + })) success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR } diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 329203e2..1ddf0d84 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -3,7 +3,7 @@ package tracegen import chisel3._ import chisel3.util._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing, ClockCrossingType} +import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType} import freechips.rocketchip.groundtest._ import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.constants.{MemoryOpConstants} @@ -178,11 +178,14 @@ case class BoomTraceGenParams( numGens: Int, dcache: Option[DCacheParams] = Some(DCacheParams()), hartId: Int = 0 -) extends InstantiableTileParams[BoomTraceGenTile] with GroundTestTileParams +) extends InstantiableTileParams[BoomTraceGenTile] { def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = { new BoomTraceGenTile(this, crossing, lookup) } + val core = RocketCoreParams(nPMPs = 0) //TODO remove this + val btb = None + val icache = Some(ICacheParams()) val beuAddr = None val blockerCtrlAddr = None val name = None @@ -193,23 +196,32 @@ class BoomTraceGenTile private( val params: BoomTraceGenParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, - q: Parameters) extends GroundTestTile(params, crossing, lookup, q) + q: Parameters) extends BaseTile(params, crossing, lookup, q) + with SinksExternalInterrupts + with SourcesExternalNotifications { def this(params: BoomTraceGenParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) + val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil) + val intOutwardNode: IntOutwardNode = IntIdentityNode() + val slaveNode: TLInwardNode = TLIdentityNode() + val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false)))) val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params)) - val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) + val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node override lazy val module = new BoomTraceGenTileModuleImp(this) } class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) - extends GroundTestTileModuleImp(outer){ + extends BaseTileModuleImp(outer){ + + val status = IO(new GroundTestStatus) + val halt_and_catch_fire = None val tracegen = Module(new TraceGenerator(outer.params.traceParams)) tracegen.io.hartid := constants.hartid From c617c4db24d6a58deb45399d1c655c57390170e6 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Sat, 20 Jun 2020 13:15:56 -0700 Subject: [PATCH 035/457] openroad floorplanning broken at TritonMacroPlace. needs debugging --- vlsi/Makefile | 6 +- vlsi/{example.yml => example-asap7.yml} | 0 vlsi/example-nangate45.yml | 129 +++++------------------- vlsi/example-vlsi | 16 ++- vlsi/example-vlsi-nangate45 | 29 ------ vlsi/hammer | 2 +- 6 files changed, 43 insertions(+), 139 deletions(-) rename vlsi/{example.yml => example-asap7.yml} (100%) delete mode 100755 vlsi/example-vlsi-nangate45 diff --git a/vlsi/Makefile b/vlsi/Makefile index e969ba14..a9e3d3a5 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -31,10 +31,8 @@ MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ example-nangate45.yml,\ - example.yml) -HAMMER_EXEC ?= $(if $(filter $(tech_name),nangate45),\ - example-vlsi-nangate45,\ - example-vlsi) + example-asap7.yml) +HAMMER_EXEC ?= example-vlsi VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build diff --git a/vlsi/example.yml b/vlsi/example-asap7.yml similarity index 100% rename from vlsi/example.yml rename to vlsi/example-asap7.yml diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index b4c1288a..7d43d068 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -1,15 +1,22 @@ +#---------------------- # Technology Setup +#---------------------- + vlsi.core.technology: nangate45 -# Specify dir with ASAP7 tarball +# the nangate45.tech.json can't reference the $OPENROAD environment variable, +# so we need to set the install dir here. # TODO: figure out how to remove this, or override it within OpenROADTool technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" vlsi.core.max_threads: 12 +#---------------------- # General Hammer Inputs +#---------------------- -# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info +# Hammer will auto-generate a CPF for simple power designs; +# see hammer/src/hammer-vlsi/defaults.yml for more info vlsi.inputs.power_spec_mode: "auto" vlsi.inputs.power_spec_type: "cpf" @@ -21,125 +28,45 @@ vlsi.inputs.clocks: [ # Generate Make include to aid in flow vlsi.core.build_system: make -# Power Straps -#par.power_straps_mode: generate -#par.generate_power_straps_method: by_tracks -#par.blockage_spacing: 2.0 -#par.generate_power_straps_options: -# by_tracks: -# strap_layers: -# - metal3 -# - metal4 -# - metal5 -# - metal6 -# - metal7 -# - metal8 -# pin_layers: -# - metal7 -# - metal8 -# track_width: 7 # minimum allowed for M2 & M3 -# track_spacing: 0 -# track_spacing_M3: 1 # to avoid M2 shorts at higher density -# track_start: 10 -# power_utilization: 0.05 -# power_utilization_M8: 1.0 -# power_utilization_M9: 1.0 - +#---------------------- # Placement Constraints -# For ASAP7, all numbers must be 4x larger than final GDS +#---------------------- + +# For nangate45, size should be multiple of (0.19,1.4) placement grid vlsi.inputs.placement_constraints: - path: "ChipTop" type: toplevel x: 0 y: 0 - width: 1387.38 - height: 1199.1 + width: 3334.72 + height: 2398.2 margins: left: 0 right: 0 top: 0 bottom: 0 -# - path: "Sha3AccelwBB/dco" -# type: hardmacro -# x: 108 -# y: 108 -# width: 128 -# height: 128 -# orientation: r0 -# top_layer: M9 -# - path: "Sha3AccelwBB/place_obs_bottom" -# type: obstruction -# obs_types: ["place"] -# x: 0 -# y: 0 -# width: 300 -# height: 1.08 # 1 core site tall, necessary to avoid shorts - -# Pin placement constraints -#vlsi.inputs.pin_mode: generated -#vlsi.inputs.pin.generate_mode: semi_auto -#vlsi.inputs.pin.assignments: [ -# {pins: "*", layers: ["metal7", "metal8"]} -#] - -# Paths to extra libraries -#vlsi.technology.extra_libraries_meta: ["append", "deepsubst"] -#vlsi.technology.extra_libraries: -# - library: -# nldm liberty file_deepsubst_meta: "local" -# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib" -# lef file_deepsubst_meta: "local" -# lef file: "extra_libraries/example/ExampleDCO.lef" -# gds file_deepsubst_meta: "local" -# gds file: "extra_libraries/example/ExampleDCO.gds" -# corner: -# nmos: "slow" -# pmos: "slow" -# temperature: "100 C" -# supplies: -# VDD: "0.63 V" -# GND: "0 V" -# - library: -# nldm liberty file_deepsubst_meta: "local" -# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib" -# lef file_deepsubst_meta: "local" -# lef file: "extra_libraries/example/ExampleDCO.lef" -# gds file_deepsubst_meta: "local" -# gds file: "extra_libraries/example/ExampleDCO.gds" -# corner: -# nmos: "fast" -# pmos: "fast" -# temperature: "0 C" -# supplies: -# VDD: "0.77 V" -# GND: "0 V" - -# Because the DCO is a dummy layout, we treat it as a physical-only cell -#par.inputs.physical_only_cells_mode: append -#par.inputs.physical_only_cells_list: -# - ExampleDCO # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "sram_compiler" ## You should specify a location for the SRAM generator in the tech plugin -vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/nangate45"] +vlsi.core.sram_generator_tool_path: [ + "hammer/src/hammer-vlsi/technology/nangate45"] vlsi.core.sram_generator_tool_path_meta: "append" +#---------------------- # Tool options. Replace with your tool plugin of choice. -# yosys options +#---------------------- + +# OpenROAD-yosys options vlsi.core.synthesis_tool: "yosys" vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"] vlsi.core.synthesis_tool_path_meta: "append" -# Innovus options -#vlsi.core.par_tool: "innovus" -#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] -#vlsi.core.par_tool_path_meta: "append" -#par.innovus.version: "181" -#par.innovus.design_flow_effort: "standard" -#par.inputs.gds_merge: true -## Calibre options -#vlsi.core.drc_tool: "calibre" +# OpenROAD-par options +vlsi.core.par_tool: "openroad" +vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"] +vlsi.core.par_tool_path_meta: "append" + +## OpenROAD-drc options (no lvs) +#vlsi.core.drc_tool: "openroad" #vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] -#vlsi.core.lvs_tool: "calibre" -#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index f853a1ed..550b56c5 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -1,4 +1,8 @@ #!/usr/bin/env python3 +# +# NOTE: this ExampleDriver works for asap7 and nangate45. the custom hooks are +# only used for asap7 though. + import os import hammer_vlsi @@ -7,21 +11,24 @@ from hammer_vlsi import CLIDriver, HammerToolHookAction from typing import Dict, Callable, Optional, List def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here ''') return True def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here ''') return True def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here set_db route_design_bottom_routing_layer 2 @@ -34,7 +41,8 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: Scale the final GDS by a factor of 4 hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script """ - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # Write script out to a temporary file and execute it set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" diff --git a/vlsi/example-vlsi-nangate45 b/vlsi/example-vlsi-nangate45 deleted file mode 100755 index 39b9a493..00000000 --- a/vlsi/example-vlsi-nangate45 +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env python3 -import os - -import hammer_vlsi -from hammer_vlsi import CLIDriver, HammerToolHookAction - -from typing import Dict, Callable, Optional, List - -def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: - x.append("") - return True - -def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: - x.append("") - return True - -class ExampleDriver(CLIDriver): - def get_extra_par_hooks(self) -> List[HammerToolHookAction]: - extra_hooks = [ - # make_pre_insertion_hook will execute the custom hook before the specified step - hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), - - # make_replacement_hook will replace the specified step with a custom hook - hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), - ] - return extra_hooks - -if __name__ == '__main__': - ExampleDriver().main() diff --git a/vlsi/hammer b/vlsi/hammer index c5a3cdf8..4d431566 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit c5a3cdf84987a46c91f3f879541060757bf225fb +Subproject commit 4d431566a87bac14454c969e7073a63b86e31161 From 486cc5fce14c69c07cc55145fafc5c4c7d1d7a8c Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 20 Jun 2020 13:57:11 -0700 Subject: [PATCH 036/457] [firechip] Add a small target that should fit on all hosts --- .../firechip/src/main/scala/TargetConfigs.scala | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 63b4d2fe..830188f3 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -125,6 +125,20 @@ class FireSimQuadRocketConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.QuadRocketConfig) +// Should fit on all supported hosts +class FireSimSmallSystemConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithBootROM ++ + new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ + new WithoutClockGating ++ + new WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ + new chipyard.RocketConfig) //***************************************************************** // Boom config, base off chipyard's LargeBoomConfig From 6b31afb1c3fffbc61a82e2ea8f95143e015a9f88 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 21 Jun 2020 11:56:45 -0700 Subject: [PATCH 037/457] Bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 96ac46f6..859c6055 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 96ac46f60261a98f1f1fa62fbd6a2fe9df5ba4bb +Subproject commit 859c60553b0cd2e84ee586ad6de25223baefb722 From ce671343292e116aeaa043d75902400783bd42f5 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 21 Jun 2020 23:25:53 +0000 Subject: [PATCH 038/457] Support using bloop instead of SBT --- .gitignore | 1 + common.mk | 22 +++++++++++++++------- project/plugins.sbt | 1 + sims/firesim | 2 +- variables.mk | 17 ++++++++++++++++- 5 files changed, 34 insertions(+), 9 deletions(-) diff --git a/.gitignore b/.gitignore index 47cb4d87..35d9b2d8 100644 --- a/.gitignore +++ b/.gitignore @@ -18,3 +18,4 @@ tags *~ env-riscv-tools.sh env-esp-tools.sh +.bloop/ diff --git a/common.mk b/common.mk index 5b502cb1..abd91b35 100644 --- a/common.mk +++ b/common.mk @@ -60,11 +60,19 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ touch $@ + +######################################################################################### +# Bloop Project Definitions +######################################################################################### +$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(base_dir)/build.sbt + cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall" + touch $@ + ######################################################################################### # create list of simulation file inputs ######################################################################################### -$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) - cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" +$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS) + $(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name)) ######################################################################################### # create firrtl file rule and variables @@ -76,11 +84,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator \ + $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ --name $(long_name) \ --top-module $(MODEL_PACKAGE).$(MODEL) \ - --legacy-configs $(CONFIG_PACKAGE).$(CONFIG)" + --legacy-configs $(CONFIG_PACKAGE).$(CONFIG)) .PHONY: firrtl firrtl: $(FIRRTL_FILE) @@ -101,7 +109,7 @@ $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp @echo "" > /dev/null firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" && touch $(sim_top_blackboxes) $(sim_harness_blackboxes) + $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes) # DOC include end: FirrtlCompiler # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs @@ -111,7 +119,7 @@ $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): top_macro_temp @echo "" > /dev/null top_macro_temp: $(TOP_SMEMS_CONF) - cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)" + $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)) HARNESS_MACROCOMPILER_MODE = --mode synflops .INTERMEDIATE: harness_macro_temp @@ -119,7 +127,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): harness_macro_temp @echo "" > /dev/null harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp - cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" + $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)) ######################################################################################## # remove duplicate files and headers in list of simulation file inputs diff --git a/project/plugins.sbt b/project/plugins.sbt index 8de71081..3fe776fa 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -15,5 +15,6 @@ addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") +addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" diff --git a/sims/firesim b/sims/firesim index c2d8e3a4..5e0ec3fd 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c2d8e3a46e59222e115a1fdaa7267592e1d3c503 +Subproject commit 5e0ec3fd70bc601fd5dae51414805c40f30a9871 diff --git a/variables.mk b/variables.mk index 1a3623a2..3abcc63b 100644 --- a/variables.mk +++ b/variables.mk @@ -125,9 +125,24 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M ######################################################################################### SCALA_VERSION=2.12.10 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) - SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar +BLOOP ?= bloop +BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop + +SCALA_BUILDTOOL_DEPS ?= $(base_dir)/build.sbt + +ifdef ENABLE_BLOOP +override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP +define run_scala_main + cd $(base_dir) && bloop run $(shell echo $(1) | sed 's/{.*}//') --main $(2) -- $(3) +endef +else +define run_scala_main + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" +endef +endif + ######################################################################################### # output directory for tests ######################################################################################### From 5e4d2103cca07a6a7eeb9f294fe8a0df7d3be26b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 21 Jun 2020 23:26:25 +0000 Subject: [PATCH 039/457] [setup] Don't re-init firesim in firesim-setup.sh --- scripts/firesim-setup.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index bb14f39e..a110cb61 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -12,7 +12,6 @@ cd "${scripts_dir}/.." # Reenable the FireSim submodule git config --unset submodule.sims/firesim.update || true -git submodule update --init sims/firesim cd sims/firesim ./build-setup.sh "$@" --library cd "$RDIR" From c5b09541becf957ac51e449aad97ab4a5c36eaf9 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 21 Jun 2020 23:36:23 +0000 Subject: [PATCH 040/457] [make] Find all build.sbt files and use them for bloop prereqs --- common.mk | 2 ++ variables.mk | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index abd91b35..3b2b08fe 100644 --- a/common.mk +++ b/common.mk @@ -34,6 +34,8 @@ lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -prin SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) +# This assumes no SBT meta-build sources +SBT_SOURCES = $(call lookup_srcs,$(base_dir),sbt) ######################################################################################### # rocket and testchipip classes diff --git a/variables.mk b/variables.mk index 3abcc63b..82e32105 100644 --- a/variables.mk +++ b/variables.mk @@ -130,7 +130,7 @@ SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop -SCALA_BUILDTOOL_DEPS ?= $(base_dir)/build.sbt +SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) ifdef ENABLE_BLOOP override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP From f311aa37d1a223f76604d33d1374a9787cda0943 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 21 Jun 2020 23:44:01 +0000 Subject: [PATCH 041/457] [make] Remove unneeded CLASSES variables --- common.mk | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/common.mk b/common.mk index 3b2b08fe..ee888b3b 100644 --- a/common.mk +++ b/common.mk @@ -37,13 +37,6 @@ VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE # This assumes no SBT meta-build sources SBT_SOURCES = $(call lookup_srcs,$(base_dir),sbt) -######################################################################################### -# rocket and testchipip classes -######################################################################################### -# NB: target/ lives under source ----V , due to how we're handling midas dependency injection -ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/src/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" -TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes" - ######################################################################################### # jar creation variables and rules ######################################################################################### @@ -66,7 +59,7 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) ######################################################################################### # Bloop Project Definitions ######################################################################################### -$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(base_dir)/build.sbt +$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall" touch $@ From 74807d6f293aea05a42da576666da52dbef519e4 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Mon, 22 Jun 2020 11:42:54 -0700 Subject: [PATCH 042/457] passes macro_place at 20% utilization --- vlsi/example-nangate45.yml | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index 7d43d068..ecc07d59 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -39,7 +39,7 @@ vlsi.inputs.placement_constraints: x: 0 y: 0 width: 3334.72 - height: 2398.2 + height: 3798.2 margins: left: 0 right: 0 diff --git a/vlsi/hammer b/vlsi/hammer index 4d431566..0e79b8c3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 4d431566a87bac14454c969e7073a63b86e31161 +Subproject commit 0e79b8c31c47988b1dc0dd5d83101ab4a5b26fe0 From 34bc8da0024df1957d7a760d0ac23ed0d8a31874 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 22 Jun 2020 17:57:17 -0700 Subject: [PATCH 043/457] Add a list of common config keys --- docs/Customization/Custom-Core.rst | 98 ++++++++++++++++++++++++++++-- 1 file changed, 93 insertions(+), 5 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 5a5cc627..6d0a9956 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -199,8 +199,8 @@ more info. name = portName, id = IdRange(0, 1 << idBits)))))) -where ``portName`` and ``idBits`` are the parameter provides by the tile. Make sure to read :::ref:`node-tyoes` to check out what -type of nodes Chipyard supports and their parameters! +where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile. +Make sure to read :::ref:`node-tyoes` to check out what type of nodes Chipyard supports and their parameters! Also, by default, there are boundary buffers for both master and slave connections to the bus when they are leaving the tile, and you can override the following two functions to control how to buffer the bus requests/responses: @@ -291,11 +291,19 @@ The implementation class is of the following form: In the body of this class, you can look up any parameters by calling ``p({key})``, where ``{key}`` is the config key of the value you want to look up. For a list of available keys, see the appendix below. -If you create an AXI4 node (or equivalents), you will need to connect them to your core. +If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this: -.. warning:: +.. code-block:: scala - TODO: Documenting bus connection + outer.myAXI4Node.out foreach { case (out, edgeOut) => + // Connect your module IO port to "out" + // The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala + // Please refer to this file for the definition of the ports. + // If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala + // If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala + // (choose one depends on the type of AHB node you create) + // If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala + } Integrate the Core ------------------ @@ -320,3 +328,83 @@ all custom cores. You can also create other config fragments to change other par Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions in :::ref:`_custom_chisel` to add your project to the build system, then create a config by following the steps in :::ref:`_hetero_socs_`. You can now run any desired workflow for the new config just as you do for the built-in cores. + +Appendix: Common Config Keys +---------------------------- + +Chipyard provide a set of keys to store standard parameters. Below are some of the most common key used in core integration. +(Note that internal fields are hidden) + +.. code-block:: scala + + // keys + // Parameters exposed to the top-level design, set based on external requirements, etc. See RISC-V debug specs for more info. + case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) + case object BootROMParams extends Field[BootROMParams] // See chipyard boot process tutorial + case object CLINTKey extends Field[Option[CLINTParams]](None) // Core Local Interrupter setting (See SiFive Interrupt Cookbook) + case object PLICKey extends Field[Option[PLICParams]](None) // Platform Level Interrupt Controller setting (See SiFive Interrupt Cookbook) + case object CacheBlockBytes extends Field[Int](64) // # of bytes in a cache block + case object BroadcastKey extends Field(BroadcastParams()) // L2 Cache broadcast setting + case object BankedL2Key extends Field(BankedL2Params()) // L2 Cache memory setting + case object PgLevels extends Field[Int](2) // Page Level of virtual memory + case object ASIdBits extends Field[Int](0) // Max # of bits for Address Space Identifer (See specs) + case object ExtMem extends Field[Option[MemoryPortParams]](None) // External DRAM setting + case object ExtBus extends Field[Option[MasterPortParams]](None) // External (off-chip) output bus setting + case object ExtIn extends Field[Option[SlavePortParams]](None) // External (off-chip) input bus setting + case object MaxHartIdBits extends Field[Int] // Max # of bits used to represent a Hart ID + case object XLen extends Field[Int] // Instruction bits (32 or 64) + case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil) // See custom ROCC tutorial + + // Values + case class DebugModuleParams ( + nDMIAddrSize : Int = 7, // Size of the Debug Bus Address + nProgramBufferWords: Int = 16, // Number of 32-bit words for Program Buffer + nAbstractDataWords : Int = 4, // Number of 32-bit words for Abstract Commands + nScratch : Int = 1, // Number of scratch memories used + hasBusMaster : Boolean = false, // Whether or not a bus master should be included + clockGate : Boolean = true, // Use clock gating + maxSupportedSBAccess : Int = 32, // Maximum transaction size supported by System Bus Access logic. + supportQuickAccess : Boolean = false, // Whether or not to support the quick access command. + supportHartArray : Boolean = true, // Whether or not to implement the hart array register (if >1 hart). + nHaltGroups : Int = 1, // Number of halt groups (group of harts that are halted together) + nExtTriggers : Int = 0, // Number of extra triggers + hasHartResets : Boolean = false, // Whether harts can be reseted with debugging system + hasImplicitEbreak : Boolean = false, // There is an additional RO program buffer word containing an ebreak + hasAuthentication : Boolean = false, // Has authentication (to prevent unauthorized users to use debugging system) + crossingHasSafeReset : Boolean = true // Include "safe" logic in Async Crossings so that only one side needs to be reset. + ) + case class CLINTParams( + baseAddress: BigInt = 0x02000000, // Default interrupt handler base address for CLINT + intStages: Int = 0 // # of cycles (stages) interrupts are delayed + ) + case class PLICParams( + baseAddress: BigInt = 0xC000000, // Default interrupt handler base address for PLIC + maxPriorities: Int = 7, // Maximum allowed interrupt priority (cannot be over 7) + intStages: Int = 0, // # of cycles (stages) interrupts are delayed + maxHarts: Int = PLICConsts.maxMaxHarts // Maximum number or hart / core connected to it + ) + case class BroadcastParams( + nTrackers: Int = 4, // # of broadcast tracker + bufferless: Boolean = false // Bufferless broadcast + ) + case class BankedL2Params( + nBanks: Int = 1 // Number of banks in L2 cache + ) + case class MasterPortParams( + base: BigInt, // Base memory address for this port + size: BigInt, // Size of this external memory + beatBytes: Int, // Interface width in bytes + idBits: Int, // # of bits in the port ID + maxXferBytes: Int = 256, // Maximum bytes in one transfer transaction + executable: Boolean = true // If the data from this port can be executed as instruciton + ) + /** Specifies the width of external slave ports */ + case class SlavePortParams( + beatBytes: Int, // Interface width in bytes + idBits: Int, // # of bits in the port ID + sourceBits: Int // # of bits in the source address + ) + case class MemoryPortParams( + master: MasterPortParams, // The memory port setting + nMemoryChannels: Int // Number of memory channel + ) From 16c8f47202ec743acaa84516a0ff79da0f13492a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 23 Jun 2020 16:31:41 +0000 Subject: [PATCH 044/457] Bump Firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index c2d8e3a4..82ce80bc 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c2d8e3a46e59222e115a1fdaa7267592e1d3c503 +Subproject commit 82ce80bc129905834426629279098fcd970a9ed3 From bfb09a68b40325b13eb46b5e52ffd01b6349f041 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Wed, 24 Jun 2020 11:22:05 -0700 Subject: [PATCH 045/457] openroad backend works for RocketConfig through drc. no docs --- vlsi/example-nangate45.yml | 7 ++++--- vlsi/hammer | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index ecc07d59..c1c3ba63 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -67,6 +67,7 @@ vlsi.core.par_tool: "openroad" vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"] vlsi.core.par_tool_path_meta: "append" -## OpenROAD-drc options (no lvs) -#vlsi.core.drc_tool: "openroad" -#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] +# OpenROAD-drc options (no lvs) +vlsi.core.drc_tool: "openroad" +vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"] +vlsi.core.drc_tool_path_meta: "append" diff --git a/vlsi/hammer b/vlsi/hammer index 0e79b8c3..70d9feec 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 0e79b8c31c47988b1dc0dd5d83101ab4a5b26fe0 +Subproject commit 70d9feec73a9633a9462ac5896f9c35201ba0bc3 From 774716ac9dcc046136449f28d0a1950eb5dd07f3 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Wed, 24 Jun 2020 12:05:38 -0700 Subject: [PATCH 046/457] udpated docs --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 70d9feec..528e745c 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 70d9feec73a9633a9462ac5896f9c35201ba0bc3 +Subproject commit 528e745c54c3901a311aade7c928e866de1d42d2 From 1c5bc7d0fff0dc20c8952e50b8bb724ede6da464 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 24 Jun 2020 20:55:37 -0700 Subject: [PATCH 047/457] Integrate with new Rocket tile API --- .../src/main/scala/ConfigFragments.scala | 17 +-- .../chipyard/src/main/scala/CoreManager.scala | 123 ------------------ ...icCoreParams.scala => GenericParams.scala} | 37 +++++- .../chipyard/src/main/scala/TestSuites.scala | 26 ++-- .../scala/stage/phases/AddDefaultTests.scala | 8 +- 5 files changed, 56 insertions(+), 155 deletions(-) delete mode 100644 generators/chipyard/src/main/scala/CoreManager.scala rename generators/chipyard/src/main/scala/{GenericCoreParams.scala => GenericParams.scala} (82%) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 1d6281cf..d66d3a07 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -26,7 +26,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} -import chipyard.{GenericTilesKey, GenericTileConfig} +import chipyard.GenericCanAttachTile /** * TODO: Why do we need this? @@ -65,11 +65,8 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nL2TLBEntries = entries))) - case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nL2TLBEntries = entries))) - case other => other + case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))).convert } }) @@ -110,7 +107,6 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { } }) - class WithTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( @@ -124,10 +120,7 @@ class WithTraceIO extends Config((site, here, up) => { class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nPerfCounters = n))) - case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nPerfCounters = n))) - case other => other + case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))).convert } }) diff --git a/generators/chipyard/src/main/scala/CoreManager.scala b/generators/chipyard/src/main/scala/CoreManager.scala deleted file mode 100644 index d013cc7c..00000000 --- a/generators/chipyard/src/main/scala/CoreManager.scala +++ /dev/null @@ -1,123 +0,0 @@ -package chipyard - -import scala.reflect.ClassTag -import scala.reflect.runtime.universe._ - -import chisel3._ - -import freechips.rocketchip.config.{Parameters, Config, Field, View} -import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams, RocketCrossingKey} -import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName} -import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile._ - -import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} -import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} - -case object CoreEntryKey extends Field[Seq[CoreEntryBase]](Nil) - -// If this key is encountered by a GenericTilesKey extractor, throw immediately -// Inside the body of GenericTileConfig, suppressed will be set to true to prevent the extractor from throwing -case class GenericTilesKeyChecker(suppressed: Boolean) extends Field[Int](0) -case class GenericTilesKeyImp(key: Field[Seq[TileParams]]) extends Field[Seq[GenericTileParams]](Nil) -object GenericTilesKey { - def apply(key: Field[Seq[TileParams]]) = GenericTilesKeyImp(key) - def unapply(key: Any): Option[Field[Seq[TileParams]]] = key match { - case GenericTilesKeyChecker(suppressed) if !suppressed => throw new Exception("GenericTilesKey must be in GenericTilesConfig") - case GenericTilesKeyImp(key) => Some(key) - case _ => None - } -} - -// Base trait for all third-party core entries -sealed trait CoreEntryBase { - val name: String - - def keyEqual(key: Any): Boolean - def tileParamsLookup(implicit p: Parameters): Seq[TileParams] - - def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) - (implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, () => BaseTile)] -} - -// Implementation of third-party core entries -class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTile : TypeTag]( - val name: String, - tilesKey: Field[Seq[TileParamsT]], - crossingKey: Field[Seq[RocketCrossingParams]] -) extends CoreEntryBase { - // Use reflection to get the tile's constructor - private val mirror = runtimeMirror(getClass.getClassLoader) - private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass) - private val tileCtor = tileClass.getConstructors.filter(ctor => ctor.getParameterTypes()(4) == classOf[Parameters]).head - - def keyEqual(key: Any) = key == tilesKey - - // Tile parameter lookup using correct type - def tileParamsLookup(implicit p: Parameters) = p(tilesKey) - - // Instantiate a tile and zip it with its parameter info, used by subsystem - def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) - (implicit p: Parameters, valName: ValName) = { - // Sanity check of GenericTilesKey outside of GenericTileConfig - // People would shoot themselves in the foot easily with this design, so a sanity check is necessary - // Simply trigger the exception by looking up the checker key - p(GenericTilesKeyChecker(false)) - - val tileParams = p(tilesKey) - val crossings = crossingLookup(p(crossingKey), tileParams.size) - (tileParams zip crossings) map { - case (param, crossing) => ( - param, - crossing, - (() => LazyModule(tileCtor.newInstance( - param, - crossing, - PriorityMuxHartIdFromSeq(tileParams), - logicalTreeNode, - p.asInstanceOf[Parameters] - ).asInstanceOf[TileT])) - ) - } - } -} - -// Config fragment to register a core -class RegisterCore[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTile : TypeTag]( - name: String, - tilesKey: Field[Seq[TileParamsT]], - crossingKey: Field[Seq[RocketCrossingParams]] -) extends Config((site, here, up) => { - case CoreEntryKey => new CoreEntry[TileParamsT, TileT](name, tilesKey, crossingKey) +: up(CoreEntryKey) -}) - -// The config used along with GenericTilesKey. -// It change a lookup for registered tile parameter into a lookup with GenericTilesKey in the function body temporarily. -class GenericTileConfig(f: (View, View, View) => PartialFunction[Any, Any]) extends Config( - new Config((site, here, up) => { - case GenericTilesKeyChecker(_) => up(GenericTilesKeyChecker(true)) - case key if CoreManager.keyMatch(up, key) => up(GenericTilesKey(key.asInstanceOf[Field[Seq[TileParams]]])) map (t => t.convert) - }) ++ - new Config(f) ++ - new Config((site, here, up) => { - case GenericTilesKeyChecker(_) => up(GenericTilesKeyChecker(false)) - case GenericTilesKey(key) => up(key) map (t => new GenericTileParams(t)) - }) -) - -// A list of all cores. -object CoreManager { - // Built-in cores. - val base_cores: List[CoreEntryBase] = List( - new CoreEntry[RocketTileParams, RocketTile]("Rocket", RocketTilesKey, RocketCrossingKey), - new CoreEntry[BoomTileParams, BoomTile]("Boom", BoomTilesKey, BoomCrossingKey), - new CoreEntry[ArianeTileParams, ArianeTile]("Ariane", ArianeTilesKey, ArianeCrossingKey) - ) - - // Look up all cores that are registered in the current config view. - def cores(view: View): Seq[CoreEntryBase] = view(CoreEntryKey) ++ base_cores - - // Check if the key is among the currently registered cores. - def keyMatch(view: View, key: Any) = (cores(view) filter (c => c.keyEqual(key))).size != 0 -} diff --git a/generators/chipyard/src/main/scala/GenericCoreParams.scala b/generators/chipyard/src/main/scala/GenericParams.scala similarity index 82% rename from generators/chipyard/src/main/scala/GenericCoreParams.scala rename to generators/chipyard/src/main/scala/GenericParams.scala index 28db42b1..8ed0d0f3 100644 --- a/generators/chipyard/src/main/scala/GenericCoreParams.scala +++ b/generators/chipyard/src/main/scala/GenericParams.scala @@ -6,15 +6,12 @@ import scala.reflect.runtime.universe._ import chisel3._ import freechips.rocketchip.config.{Parameters, Config, Field, View} -import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams, RocketCrossingKey} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ -import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} -import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} - // Trait for generic case class of base trait for copying trait ConcreteBaseTrait[Base] { this: Product => @@ -146,3 +143,35 @@ case class GenericTileParams( _origin = tileParams ) } + +case class GenericTileCrossingParamsLike( + val crossingType: ClockCrossingType, + val master: TilePortParamsLike, + val slave: TilePortParamsLike, + val _origin: TileCrossingParamsLike +) extends TileCrossingParamsLike with ConcreteBaseTrait[TileCrossingParamsLike] { + def this(crossing: TileCrossingParamsLike) = this( + crossingType = crossing.crossingType, + master = crossing.master, + slave = crossing.slave, + _origin = crossing + ) +} + +case class GenericCanAttachTileImpl( + val tileParams: GenericTileParams, + val crossingParams: TileCrossingParamsLike, + val lookup: LookupByHartIdImpl, + val _origin: CanAttachTile, +) extends ConcreteBaseTrait[CanAttachTile] { + def this(param: CanAttachTile) = this( + tileParams = new GenericTileParams(param.tileParams), + crossingParams = new GenericTileCrossingParamsLike(param.crossingParams), + lookup = param.lookup, + _origin = param + ) +} + +object GenericCanAttachTile { + def unapply(tile: CanAttachTile) = Some(new GenericCanAttachTileImpl(tile)) +} diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index a3565a53..77aab39b 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -3,8 +3,8 @@ package chipyard import scala.collection.mutable.{LinkedHashSet} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tile.{XLen} -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.tile.{XLen, TileParams} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} import boom.common.{BoomTileAttachParams} @@ -83,16 +83,17 @@ class TestSuiteHelper if (cfg.fLen >= 64) addSuites(env.map(rv64ud)) } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - else - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) addSuites(rvi.map(_("p"))) addSuites(rvu.map(_("p"))) @@ -116,4 +117,3 @@ case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Param class WithTestSuite(suiteFactory: (Seq[TileParams], TestSuiteHelper, Parameters) => Unit) extends Config((site, here, up) => { case TestSuitesKey => suiteFactory }) - diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index b170706e..623dbce4 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -15,10 +15,11 @@ import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} +import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem} import freechips.rocketchip.util.HasRocketChipStageUtils import freechips.rocketchip.tile.XLen -import chipyard.{TestSuiteHelper, CoreManager} +import chipyard.TestSuiteHelper import chipyard.TestSuitesKey class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { @@ -34,12 +35,13 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS val suiteHelper = new TestSuiteHelper // Use Xlen as a proxy for detecting if we are a processor-like target // The underlying test suites expect this field to be defined + val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams) if (p.lift(XLen).nonEmpty) // If a custom test suite is set up, use the custom test suite if (p.lift(TestSuitesKey).nonEmpty) - CoreManager.cores(p) map (core => p(TestSuitesKey).apply(core.tileParamsLookup, suiteHelper, p)) + p(TestSuitesKey).apply(tileParams, suiteHelper, p) else - CoreManager.cores(p) map (core => suiteHelper.addGenericTestSuites(core.tileParamsLookup)) + suiteHelper.addGenericTestSuites(tileParams) // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From a0f103e8430c632f1d82e0e0d8f5bcc97ace13ba Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 25 Jun 2020 14:14:08 -0700 Subject: [PATCH 048/457] [make] Specify a custom bloop server port w/ BLOOP_NAILGUN_PORT --- variables.mk | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index 82e32105..48da498e 100644 --- a/variables.mk +++ b/variables.mk @@ -129,13 +129,22 @@ SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop +# This mirrors the bloop default. Set to a system-unique port in a multi-user environment +BLOOP_NAILGUN_PORT ?= 8212 SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) ifdef ENABLE_BLOOP override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP +# Two notes about the bloop invocation: +# 1) the sed removes a leading {file:} that sometimes needs to be +# provided to SBT when a project but not for bloop. +# 2) Generally, one could could pass '--' to indicate all remaining arguments are +# destined for the scala Main, however a bug in Bloop's argument parsing causes the +# --nailgun-port argument to be lost in this case. Workaround this by prefixing +# every main-destined argument with "--args" define run_scala_main - cd $(base_dir) && bloop run $(shell echo $(1) | sed 's/{.*}//') --main $(2) -- $(3) + cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) endef else define run_scala_main From 02c889b8b15b86587feae852f1165fade348bb4b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 25 Jun 2020 17:42:38 -0700 Subject: [PATCH 049/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index d972de15..8064d880 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit d972de156c50ac48c019681b39270d4a4ac1a3d5 +Subproject commit 8064d8808b9c936711361532a95affbfc2fcbdca From 1dd3ea4aebdcc720af33495fb12b364b643b76de Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 27 Jun 2020 13:44:52 -0700 Subject: [PATCH 050/457] Update TargetConfigs.scala --- generators/firechip/src/main/scala/TargetConfigs.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 830188f3..87662b03 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -125,7 +125,8 @@ class FireSimQuadRocketConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.QuadRocketConfig) -// Should fit on all supported hosts +// A stripped down configuration that should fit on all supported hosts. +// Flat to avoid having to reorganize the config class hierarchy to remove certain features class FireSimSmallSystemConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ From 7b5f474b041a30ff06eb29ee8dbf6914277ba171 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 28 Jun 2020 21:26:50 -0700 Subject: [PATCH 051/457] Finished Custom Core Docs --- docs/Customization/Custom-Core.rst | 26 +++++++------------ docs/Customization/index.rst | 1 + .../NodeTypes.rst | 2 ++ docs/TileLink-Diplomacy-Reference/Widgets.rst | 2 ++ 4 files changed, 15 insertions(+), 16 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 6d0a9956..e2723336 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -4,7 +4,7 @@ Adding a custom core ==================== You may want to add a custom RISC-V core to Chipyard generator. If the top module of your core is not in Chisel, -you will first need to create a Verilog blackbox for it. See ::ref:`_incorporating-verilog-blocks` for instructions. +you will first need to create a Verilog blackbox for it. See :ref:`incorporating-verilog-blocks` for instructions. Once you have a top module in Chisel, you are ready to create integrate it with Chipyard. .. note:: @@ -184,7 +184,7 @@ in the tile class. Below is an example of how to connect a core using AXI4 to th := AXI4Fragmenter() // deal with multi-beat xacts := memAXI4Node) // The custom node, see below -Remember, you may not need all of these intermediate widgets. See :::ref:`Diplomatic-Widgets` for the meaning of each intermediate +Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Also, Chipyard support AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol. See the reference page for more info. @@ -200,7 +200,7 @@ more info. id = IdRange(0, 1 << idBits)))))) where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile. -Make sure to read :::ref:`node-tyoes` to check out what type of nodes Chipyard supports and their parameters! +Make sure to read :ref:`node_types` to check out what type of nodes Chipyard supports and their parameters! Also, by default, there are boundary buffers for both master and slave connections to the bus when they are leaving the tile, and you can override the following two functions to control how to buffer the bus requests/responses: @@ -210,7 +210,7 @@ can override the following two functions to control how to buffer the bus reques protected def makeMasterBoundaryBuffers(implicit p: Parameters): TLBuffer protected def makeSlaveBoundaryBuffers(implicit p: Parameters): TLBuffer -You can find more information on ``TLBuffer`` in :::ref:`Diplomatic-Widgets`. +You can find more information on ``TLBuffer`` in :ref:`diplomatic_widgets`. Interrupt --------- @@ -313,20 +313,14 @@ the current config. An example of such config will be like this: .. code-block:: scala - class WithNMyCores(n: Int) extends Config( - new RegisterCore(new CoreEntry[MyTileParams, MyTile]("MyCore", MyTilesKey, MyCrossingKey)) ++ - new Config((site, here, up) => { - case MyTilesKey => { - List.tabulate(n)(i => MyTileParams(hartId = i)) - } - }) - ) - -Where ``RegisterCore`` will register the core with chipyard so that it can be recognized by generic config. This is required for -all custom cores. You can also create other config fragments to change other parameters. + class WithNMyCores(n: Int) extends Config((site, here, up) => { + case MyTilesKey => { + List.tabulate(n)(i => MyTileParams(hartId = i)) + } + }) Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions -in :::ref:`_custom_chisel` to add your project to the build system, then create a config by following the steps in :::ref:`_hetero_socs_`. +in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`. You can now run any desired workflow for the new config just as you do for the built-in cores. Appendix: Common Config Keys diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index 38fdf622..a7b571b6 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -37,6 +37,7 @@ We recommend reading all these pages in order. Hit next to get started! Heterogeneous-SoCs Custom-Chisel + Custom-Core RoCC-or-MMIO RoCC-Accelerators MMIO-Peripherals diff --git a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst index ddb53c9f..32953944 100644 --- a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst +++ b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst @@ -1,3 +1,5 @@ +.. _node_types: + TileLink Node Types =================== diff --git a/docs/TileLink-Diplomacy-Reference/Widgets.rst b/docs/TileLink-Diplomacy-Reference/Widgets.rst index 7eba871b..791c1b9b 100644 --- a/docs/TileLink-Diplomacy-Reference/Widgets.rst +++ b/docs/TileLink-Diplomacy-Reference/Widgets.rst @@ -1,3 +1,5 @@ +.. _diplomatic_widgets: + Diplomatic Widgets ================== From c85d8c4211c3c888a0ba0b80a92ee5d5b23bbc39 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 29 Jun 2020 11:42:34 -0700 Subject: [PATCH 052/457] Remove generic parameter from this PR --- .../src/main/scala/ConfigFragments.scala | 48 +++-- .../src/main/scala/GenericParams.scala | 177 ------------------ .../chipyard/src/main/scala/TestSuites.scala | 13 +- .../src/main/scala/config/BoomConfigs.scala | 1 + .../src/main/scala/config/HeteroConfigs.scala | 1 + .../src/main/scala/config/RocketConfigs.scala | 1 + .../scala/stage/phases/AddDefaultTests.scala | 18 +- 7 files changed, 42 insertions(+), 217 deletions(-) delete mode 100644 generators/chipyard/src/main/scala/GenericParams.scala diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index d66d3a07..da048ff1 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -25,8 +25,7 @@ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import chipyard.{BuildTop, BuildSystem} -import chipyard.GenericCanAttachTile +import chipyard.{BuildTop, BuildSystem, TestSuitesKey, TestSuiteHelper} /** * TODO: Why do we need this? @@ -65,8 +64,11 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nL2TLBEntries = entries))).convert + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case other => other } }) @@ -97,15 +99,18 @@ class WithMultiRoCC extends Config((site, here, up) => { * * @param harts harts to specify which will get a Hwacha */ -class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { - case MultiRoCCKey => { - up(MultiRoCCKey, site) ++ harts.distinct.map{ i => - (i -> Seq((p: Parameters) => { - LazyModule(new Hwacha()(p)).suggestName("hwacha") - })) +class WithMultiRoCCHwacha(harts: Int*) extends Config( + new chipyard.config.WithHwachaTest ++ + new Config((site, here, up) => { + case MultiRoCCKey => { + up(MultiRoCCKey, site) ++ harts.distinct.map{ i => + (i -> Seq((p: Parameters) => { + LazyModule(new Hwacha()(p)).suggestName("hwacha") + })) + } } - } -}) + }) +) class WithTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { @@ -120,7 +125,22 @@ class WithTraceIO extends Config((site, here, up) => { class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nPerfCounters = n))).convert + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case other => other } }) + +class WithHwachaTest extends Config((site, here, up) => { + case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { + up(TestSuitesKey).apply(tileParams, suiteHelper, p) + import hwacha.HwachaTestSuites._ + suiteHelper.addSuites(rv64uv.map(_("p"))) + suiteHelper.addSuites(rv64uv.map(_("vp"))) + suiteHelper.addSuite(rv64sv("p")) + suiteHelper.addSuite(hwachaBmarks) + "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha" + } +}) \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/GenericParams.scala b/generators/chipyard/src/main/scala/GenericParams.scala deleted file mode 100644 index 8ed0d0f3..00000000 --- a/generators/chipyard/src/main/scala/GenericParams.scala +++ /dev/null @@ -1,177 +0,0 @@ -package chipyard - -import scala.reflect.ClassTag -import scala.reflect.runtime.universe._ - -import chisel3._ - -import freechips.rocketchip.config.{Parameters, Config, Field, View} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName} -import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile._ - -// Trait for generic case class of base trait for copying -trait ConcreteBaseTrait[Base] { - this: Product => - val _origin: Base - - // Convert back to core-specific tile - def convert: Base = { - // Reflection Info of this class - val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init - - // Reflection of target class - val paramClass = _origin.getClass - val paramNames = (paramClass.getDeclaredFields map (f => f.getName)) - val paramCtor = paramClass.getConstructors.head - - // Build a list of parameter in the original parameter class - val nameDict = paramNames.zipWithIndex.toMap - val indexList = fieldNames map (n => nameDict.get(n)) - val fieldList = this.productIterator.toList map { - case c: ConcreteBaseTrait[_] => c.convert - case v => v - } - val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap - val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map - { case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] } - - paramCtor.newInstance(newValues:_*).asInstanceOf[Base] - } -} - -// Case class to change common parameters visible in the base traits. Some fields in the base traits may not be configurable as a -// case class constructor parameter for some cores, and those field will be ignored when applied. -case class GenericCoreParams( - val bootFreqHz: BigInt, - val useVM: Boolean, - val useUser: Boolean, - val useSupervisor: Boolean, - val useDebug: Boolean, - val useAtomics: Boolean, - val useAtomicsOnlyForIO: Boolean, - val useCompressed: Boolean, - override val useVector: Boolean, - val useSCIE: Boolean, - val useRVE: Boolean, - val mulDiv: Option[MulDivParams], - val fpu: Option[FPUParams], - val fetchWidth: Int, - val decodeWidth: Int, - val retireWidth: Int, - val instBits: Int, - val nLocalInterrupts: Int, - val nPMPs: Int, - val pmpGranularity: Int, - val nBreakpoints: Int, - val useBPWatch: Boolean, - val nPerfCounters: Int, - val haveBasicCounters: Boolean, - val haveFSDirty: Boolean, - val misaWritable: Boolean, - val haveCFlush: Boolean, - val nL2TLBEntries: Int, - val mtvecInit: Option[BigInt], - val mtvecWritable: Boolean, - // The original object - val _origin: CoreParams -) extends CoreParams with ConcreteBaseTrait[CoreParams] { - def this(coreParams: CoreParams) = this( - bootFreqHz = coreParams.bootFreqHz, - useVM = coreParams.useVM, - useUser = coreParams.useUser, - useSupervisor = coreParams.useSupervisor, - useDebug = coreParams.useDebug, - useAtomics = coreParams.useAtomics, - useAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO, - useCompressed = coreParams.useCompressed, - useVector = coreParams.useVector, - useSCIE = coreParams.useSCIE, - useRVE = coreParams.useRVE, - mulDiv = coreParams.mulDiv, - fpu = coreParams.fpu, - fetchWidth = coreParams.fetchWidth, - decodeWidth = coreParams.decodeWidth, - retireWidth = coreParams.retireWidth, - instBits = coreParams.instBits, - nLocalInterrupts = coreParams.nLocalInterrupts, - nPMPs = coreParams.nPMPs, - pmpGranularity = coreParams.pmpGranularity, - nBreakpoints = coreParams.nBreakpoints, - useBPWatch = coreParams.useBPWatch, - nPerfCounters = coreParams.nPerfCounters, - haveBasicCounters = coreParams.haveBasicCounters, - haveFSDirty = coreParams.haveFSDirty, - misaWritable = coreParams.misaWritable, - haveCFlush = coreParams.haveCFlush, - nL2TLBEntries = coreParams.nL2TLBEntries, - mtvecInit = coreParams.mtvecInit, - mtvecWritable = coreParams.mtvecWritable, - - _origin = coreParams - ) - - // Implement abstract function as placeholder - def lrscCycles: Int = _origin.lrscCycles -} - -case class GenericTileParams( - val core: GenericCoreParams, - val icache: Option[ICacheParams], - val dcache: Option[DCacheParams], - val btb: Option[BTBParams], - val hartId: Int, - val beuAddr: Option[BigInt], - val blockerCtrlAddr: Option[BigInt], - val name: Option[String], - // The original object - val _origin: TileParams, -) extends TileParams with ConcreteBaseTrait[TileParams] { - // Copy constructor to build the params - def this(tileParams: TileParams) = this( - core = new GenericCoreParams(tileParams.core), - icache = tileParams.icache, - dcache = tileParams.dcache, - btb = tileParams.btb, - hartId = tileParams.hartId, - beuAddr = tileParams.beuAddr, - blockerCtrlAddr = tileParams.blockerCtrlAddr, - name = tileParams.name, - - _origin = tileParams - ) -} - -case class GenericTileCrossingParamsLike( - val crossingType: ClockCrossingType, - val master: TilePortParamsLike, - val slave: TilePortParamsLike, - val _origin: TileCrossingParamsLike -) extends TileCrossingParamsLike with ConcreteBaseTrait[TileCrossingParamsLike] { - def this(crossing: TileCrossingParamsLike) = this( - crossingType = crossing.crossingType, - master = crossing.master, - slave = crossing.slave, - _origin = crossing - ) -} - -case class GenericCanAttachTileImpl( - val tileParams: GenericTileParams, - val crossingParams: TileCrossingParamsLike, - val lookup: LookupByHartIdImpl, - val _origin: CanAttachTile, -) extends ConcreteBaseTrait[CanAttachTile] { - def this(param: CanAttachTile) = this( - tileParams = new GenericTileParams(param.tileParams), - crossingParams = new GenericTileCrossingParamsLike(param.crossingParams), - lookup = param.lookup, - _origin = param - ) -} - -object GenericCanAttachTile { - def unapply(tile: CanAttachTile) = Some(new GenericCanAttachTileImpl(tile)) -} diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 77aab39b..9ca2c08c 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -107,13 +107,8 @@ class TestSuiteHelper /** * Config key of custom test suite. */ -case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => Unit]((tiles, helper, p) => helper.addGenericTestSuites(tiles)(p)) - -/** - * Config fragment to add custom test suite factory function. - * - * @param suiteFactory Test suite factory function. It takes a list of TileParams to be instantiated and the test suite helper. - */ -class WithTestSuite(suiteFactory: (Seq[TileParams], TestSuiteHelper, Parameters) => Unit) extends Config((site, here, up) => { - case TestSuitesKey => suiteFactory +case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => { + helper.addGenericTestSuites(tiles)(p) + // Return an empty string as makefile additional snippets + "" }) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 7b66e3b3..414f10af 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -106,6 +106,7 @@ class HwachaLargeBoomConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.config.WithHwachaTest ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index a7d1c133..4930ddee 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -36,6 +36,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.config.WithHwachaTest ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 06257c7b..566e2757 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -34,6 +34,7 @@ class HwachaRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.config.WithHwachaTest ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 623dbce4..177d26b0 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -38,24 +38,8 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams) if (p.lift(XLen).nonEmpty) // If a custom test suite is set up, use the custom test suite - if (p.lift(TestSuitesKey).nonEmpty) - p(TestSuitesKey).apply(tileParams, suiteHelper, p) - else - suiteHelper.addGenericTestSuites(tileParams) + annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p)) - // if hwacha parameter exists then generate its tests - // TODO: find a more elegant way to do this. either through - // trying to disambiguate BuildRoCC, having a AccelParamsKey, - // or having the Accelerator/Tile add its own tests - import hwacha.HwachaTestSuites._ - if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) { - suiteHelper.addSuites(rv64uv.map(_("p"))) - suiteHelper.addSuites(rv64uv.map(_("vp"))) - suiteHelper.addSuite(rv64sv("p")) - suiteHelper.addSuite(hwachaBmarks) - annotations += CustomMakefragSnippet( - "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha") - } RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations } From d77c4afb36ec37414dadbef63904376f8e0853d3 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 29 Jun 2020 12:05:24 -0700 Subject: [PATCH 053/457] Rollback .gitignore --- .gitignore | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.gitignore b/.gitignore index 57467069..35d9b2d8 100644 --- a/.gitignore +++ b/.gitignore @@ -10,10 +10,6 @@ target *# *~ .idea -.bloop -.metals -project/metals.sbt -.vscode .DS_Store env.sh riscv-tools-install From 863f723708f39304293e6aba52bca2d47e130c85 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 30 Jun 2020 12:26:26 -0700 Subject: [PATCH 054/457] Pipe through AXI4 MMIO and Slave ports to ChipTop | IOBinders fix * Fixes bug with AXI4 MMIO ports not being generated properly due to IOBinders issue. Additionally adds IOCells to AXI4 ports so that they appear in ChipTop * Change IOBinders to also require passing p: Parameters to child functions. Serialization of type targets via ClassTags fails for compound types, so we cannot use `BaseSubsystem with HasSomeTrait` as the type target in OverrideIOBinders. --- .circleci/config.yml | 9 ++ .circleci/defaults.sh | 32 ++--- .../chipyard/src/main/scala/ChipTop.scala | 3 +- .../chipyard/src/main/scala/IOBinders.scala | 117 ++++++++++-------- .../src/main/scala/config/RocketConfigs.scala | 18 +++ .../src/main/scala/BridgeBinders.scala | 39 +++--- tools/barstools | 2 +- 7 files changed, 132 insertions(+), 88 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index ab123661..b6556850 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -287,6 +287,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-spiflashread" + prepare-chipyard-mmios: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-mmios" chipyard-rocket-run-tests: executor: main-env steps: @@ -531,6 +536,10 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-mmios: + requires: + - install-riscv-toolchain + # Run the respective tests # Run the example tests diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index b9aeeb3b..7cb8c1e2 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,23 +47,25 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build strings declare -A mapping -mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" -mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" -mapping["chipyard-streaming-fir"]="SUB_PROJECT=chipyard CONFIG=StreamingFIRRocketConfig" -mapping["chipyard-streaming-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" -mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" -mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" -mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" -mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" -mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" -mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" -mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRocketConfig" -mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig" -mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" -mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" -mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig" +mapping["chipyard-rocket"]="" +mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" +mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" +mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" +mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" +mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig" +mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig" +mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" +mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" +mapping["chipyard-ariane"]=" CONFIG=ArianeConfig" +mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig" +mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig" +mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" +mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" +mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" +mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" + diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index d0b4df02..ea0c804d 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -70,12 +70,13 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with val lSystem = p(BuildSystem)(p).suggestName("system") val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) } + // Call all of the IOBinders and provide them with a default clock and reset withClockAndReset(systemClock, systemReset) { // Call each IOBinder on both the lazyModule instance and the module // instance. Generally, an IOBinder PF should only be defined on one, so // this should not lead to two invocations. - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3 + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem, p) ++ f(system, p)).unzip3 // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1a366d19..2b7cd41c 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} -import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.util._ import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} @@ -48,17 +48,17 @@ type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any] // 3. An optional function to call inside the test harness (e.g. to connect the IOs) type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction]) -case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]]( - Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil) +case object IOBinders extends Field[Map[String, (Any, Parameters) => Seq[IOBinderTuple]]]( + Map[String, (Any, Parameters) => Seq[IOBinderTuple]]().withDefaultValue((Any, Parameters) => Nil) ) // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { + ((t: Any, p: Parameters) => { t match { - case system: T => fn(system) + case system: T => fn(system, p) case _ => Nil } }) @@ -67,12 +67,12 @@ class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassT // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { + ((t: Any, p: Parameters) => { t match { - case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system) - ++ fn(system)) + case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system, p) + ++ fn(system, p)) case _ => Nil } }) @@ -185,10 +185,19 @@ object AddIOCells { (port, ios) } - def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { + def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { - val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}")) - port.suggestName(s"mem_axi4_${i}") + val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_slave_${i}")) + port.suggestName(s"${name}_axi4_slave_${i}") + (port, edge, ios) + }} + } + def axi4(io: Seq[AXI4Bundle], node: AXI4MasterNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { + io.zip(node.out).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { + //val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_master_${i}")) + val port = IO(Flipped(AXI4Bundle(edge.bundle))) + val ios = IOCell.generateFromSignal(mem_axi4, port, Some(s"iocell_${name}_axi4_master_${i}")) + port.suggestName(s"${name}_axi4_master_${i}") (port, edge, ios) }} } @@ -202,7 +211,7 @@ object AddIOCells { // DOC include start: WithGPIOTiedOff class WithGPIOTiedOff extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => { + (system: HasPeripheryGPIOModuleImp, p) => { val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) @@ -211,7 +220,7 @@ class WithGPIOTiedOff extends OverrideIOBinder({ // DOC include end: WithGPIOTiedOff class WithUARTAdapter extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { + (system: HasPeripheryUARTModuleImp, p) => { val (ports, ioCells2d) = AddIOCells.uart(system.uart) val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -219,7 +228,7 @@ class WithUARTAdapter extends OverrideIOBinder({ }) class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ - (system: HasPeripherySPIFlashModuleImp) => { + (system: HasPeripherySPIFlashModuleImp, p) => { val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -227,7 +236,7 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ }) class WithSimBlockDevice extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p) @@ -238,7 +247,7 @@ class WithSimBlockDevice extends OverrideIOBinder({ }) class WithBlockDeviceModel extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { BlockDeviceModel.connect(Some(port))(system.p) @@ -249,11 +258,11 @@ class WithBlockDeviceModel extends OverrideIOBinder({ }) class WithLoopbackNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil + (system: CanHavePeripheryIceNICModuleImp, p) => system.connectNicLoopback(); Nil }) class WithSimNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil + (system: CanHavePeripheryIceNICModuleImp, p) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) // Note: The parameters instance is accessible only through the BaseSubsystem @@ -262,16 +271,16 @@ class WithSimNIC extends OverrideIOBinder({ // accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + (system: CanHaveMasterAXI4MemPort, p) => { + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") // TODO: we are inlining the connectMem method of SimAXIMem because // it takes in a dut rather than seq of axi4 ports val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => - val mem = LazyModule(new SimAXIMem(edge, size = system.p(ExtMem).get.master.size)(system.p)) + val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)(p)) Module(mem.module).suggestName("mem") mem.io_axi4.head <> port - } + } Nil } Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) @@ -280,12 +289,12 @@ class WithSimAXIMem extends OverrideIOBinder({ // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + (system: CanHaveMasterAXI4MemPort, p) => { + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => - val memSize = system.p(ExtMem).get.master.size - val lineSize = system.p(CacheBlockBytes) + val memSize = p(ExtMem).get.master.size + val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) mem.io.axi <> port mem.io.clock := th.clock @@ -298,15 +307,26 @@ class WithBlackBoxSimMem extends OverrideIOBinder({ }) class WithSimAXIMMIO extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil + (system: CanHaveMasterAXI4MMIOPort, p) => { + val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem") + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => + val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)(p)) + Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") + mmio_mem.io_axi4.head <> port + } + Nil + } + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) + } }) class WithDontTouchPorts extends OverrideIOBinder({ - (system: DontTouch) => system.dontTouchPorts(); Nil + (system: DontTouch, p) => system.dontTouchPorts(); Nil }) class WithTieOffInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp) => { + (system: HasExtInterruptsModuleImp, p) => { val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) port.suggestName("interrupts") val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil } @@ -315,26 +335,21 @@ class WithTieOffInterrupts extends OverrideIOBinder({ }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4Port with BaseSubsystem) => { - system.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - case _ => throw new Exception("Unknown AXI port direction") + (system: CanHaveSlaveAXI4Port, p) => { + val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus") + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => + port := DontCare // tieoff doesn't completely tie-off, for some reason + port.tieoff() } - }) - Nil + Nil + } + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) } }) class WithTiedOffDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { + (system: HasPeripheryDebugModuleImp, p) => { val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -352,7 +367,7 @@ class WithTiedOffDebug extends OverrideIOBinder({ }) class WithSimDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { + (system: HasPeripheryDebugModuleImp, p) => { val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -367,7 +382,7 @@ class WithSimDebug extends OverrideIOBinder({ }) class WithTiedOffSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { SerialAdapter.tieoff(port) @@ -378,7 +393,7 @@ class WithTiedOffSerial extends OverrideIOBinder({ }) class WithSimSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset) @@ -390,7 +405,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp) => { + (system: TraceGenSystemModuleImp, p) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } @@ -399,7 +414,7 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ }) class WithSimDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => { + (system: CanHaveTraceIOModuleImp, p) => { system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 06257c7b..3dc7d22d 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -542,3 +542,21 @@ class LargeNVDLARocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) + +class MMIORocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithTieOffL2FBusAXI ++ // Tie-off the incoming MMIO port + new chipyard.iobinders.WithSimAXIMMIO ++ // Attach a simulated memory to the outwards MMIO port + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index eeb19559..6af7bd0a 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -35,29 +35,28 @@ object MainMemoryConsts { } class WithSerialBridge extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => - system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil + (system: CanHavePeripherySerialModuleImp, p) => + system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(p)); Nil }) class WithNICBridge extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => - system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil + (system: CanHavePeripheryIceNICModuleImp, p) => + system.net.foreach(n => NICBridge(system.clock, n)(p)); Nil }) class WithUARTBridge extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => - system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil + (system: HasPeripheryUARTModuleImp, p) => + system.uart.foreach(u => UARTBridge(system.clock, u)(p)); Nil }) class WithBlockDeviceBridge extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => - system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil + (system: CanHavePeripheryBlockDeviceModuleImp, p) => + system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(p)); Nil }) class WithFASEDBridge extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - implicit val p = system.p + (system: CanHaveMasterAXI4MemPort, p) => { (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) => val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, axi4.ar.bits.addr.getWidth, @@ -73,26 +72,26 @@ class WithFASEDBridge extends OverrideIOBinder({ }) class WithTracerVBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => - system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil + (system: CanHaveTraceIOModuleImp, p) => + system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(p))); Nil }) class WithDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => { - system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil + (system: CanHaveTraceIOModuleImp, p) => { + system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(p))); Nil } }) class WithTraceGenBridge extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp) => + (system: TraceGenSystemModuleImp, p) => GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (system: HasTilesModuleImp) => { + (system: HasTilesModuleImp, p) => { system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -116,13 +115,13 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ }) class WithTiedOffSystemGPIO extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => + (system: HasPeripheryGPIOModuleImp, p) => system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil }) class WithTiedOffSystemDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { - Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) + (system: HasPeripheryDebugModuleImp, p) => { + Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(p) // tieoffDebug doesn't actually tie everything off :/ system.debug.foreach { d => d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) @@ -133,7 +132,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({ }) class WithTiedOffSystemInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp) => + (system: HasExtInterruptsModuleImp, p) => system.interrupts := 0.U; Nil }) diff --git a/tools/barstools b/tools/barstools index 7e6e19b8..aa1c90c4 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 7e6e19b8adf3b625b31b09173ecae5f634c83e1b +Subproject commit aa1c90c4ccb73c2c379550f3296892cc81e8a195 From 02a951703b0d6da5f5bff9118dc10ef49afa6cba Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 2 Jul 2020 00:52:51 -0700 Subject: [PATCH 055/457] Initialize riscv-sodor --- .gitmodules | 3 +++ generators/riscv-sodor | 1 + 2 files changed, 4 insertions(+) create mode 160000 generators/riscv-sodor diff --git a/.gitmodules b/.gitmodules index aab9a8f7..f374fa1f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -128,3 +128,6 @@ [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/riscv-boom/dromajo.git +[submodule "generators/riscv-sodor"] + path = generators/riscv-sodor + url = https://github.com/ucb-bar/riscv-sodor.git diff --git a/generators/riscv-sodor b/generators/riscv-sodor new file mode 160000 index 00000000..73af1b70 --- /dev/null +++ b/generators/riscv-sodor @@ -0,0 +1 @@ +Subproject commit 73af1b7099764350c6dab6c5960334abcb7bdf07 From 104c350a59af995d0d36affc5f1203582be838ca Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 2 Jul 2020 15:56:15 -0700 Subject: [PATCH 056/457] Custom Core Integration Doc, 1st Revision --- docs/Customization/Custom-Core.rst | 113 +++++++++----------- docs/TileLink-Diplomacy-Reference/index.rst | 2 + 2 files changed, 51 insertions(+), 64 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index e2723336..dcf2c257 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -7,34 +7,32 @@ You may want to add a custom RISC-V core to Chipyard generator. If the top modul you will first need to create a Verilog blackbox for it. See :ref:`incorporating-verilog-blocks` for instructions. Once you have a top module in Chisel, you are ready to create integrate it with Chipyard. +``generators/ariane/src/main/scala/ArianeTile.scala`` and ``generators/boom/src/main/scala/common/tile.scala`` +provide two examples of how to integrate a core. + .. note:: - RoCC is not supported by custom core currently. Please use Rocket or Boom if you need to use RoCC. + RoCC is not supported by custom core currently. Please use Rocket or Boom as the RoCC base core if you need to use RoCC. Parameter Case Classes ---------------------- -Chipyard will generate a core for every ``TileParams`` object it discovered in the current config. -``TileParams`` is a trait containing the information needed to create a tile, and every custom core must implement -their own version of ``TileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``. +Chipyard will generate a core for every ``InstantiableTileParams`` object it discovered in the current config. +This object is derived from``TileParams``, a trait containing the information needed to create a tile. All cores must have +their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``. -``TileParams`` holds the parameters that are the same for every generated core, while ``CoreParams`` contains those -that can vary from cores to cores. They must be implemented as case classes with fields that can be overridden by +``TileParams`` holds the parameters for the tile, which are the same for every generated core, while ``CoreParams`` +contains the parameters for individual cores. They must be implemented as case classes with fields that can be overridden by other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. -Now you have your parameter classes, you will need config keys to hold them. There are two required keys: +``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``. +All custom cores will also need to implement ``instantiate()`` in their tile parameter class to return a new instance +of the tile class ``TileType``. -.. code-block:: scala - - case object MyTilesKey extends Field[Seq[MyTileParams]](Nil) - case object MyCrossingKey extends Field[Seq[RocketCrossingParams]](List(RocketCrossingParams())) - -``MyCrossingKey`` here is used to store information about the clock-crossing behavior of the core, and it is normally -set to its default values. - -``TileParams`` and ``CoreParams`` contains the following fields (you may ignore any fields marked "Rocket specific" and -use their default values, although it is recommended to use them if you need a custom field with similar purposes) : +``TileParams``, ``InstantiableTileParams[TileType]`` and ``CoreParams`` contains the following fields (you may ignore +any fields marked "Rocket specific" and use their default values, although it is recommended to use them if you +need a custom field with similar purposes): .. code-block:: scala @@ -49,6 +47,11 @@ use their default values, although it is recommended to use them if you need a c val name: Option[String] // Name of the core } + abstract class InstantiableTileParams[TileType <: BaseTile] extends TileParams { + def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl) + (implicit p: Parameters): TileType + } + trait CoreParams { val bootFreqHz: BigInt // Frequency val useVM: Boolean // Support virtual memory @@ -87,7 +90,7 @@ use their default values, although it is recommended to use them if you need a c def hasSupervisorMode: Boolean = useSupervisor || useVM def instBytes: Int = instBits / 8 def fetchBytes: Int = fetchWidth * instBytes - // Rocket specific: Longest possible latency of Rocket core D1 cache. Simply set it to the default value 80. + // Rocket specific: Longest possible latency of Rocket core D1 cache. Simply set it to the default value 80 if you don't use it. def lrscCycles: Int def dcacheReqTagBits: Int = 6 @@ -109,14 +112,23 @@ use their default values, although it is recommended to use them if you need a c Most of the fields here are originally designed for Rocket core and contains some architecture-specific details, but many of them are general enough to be useful for other cores. It is strongly recommended to use these fields instead -of creating your own custom fields when applicable. +of creating your own custom fields when applicable. + +.. note:: + + Implementations may choose to ignore some fields here or use them in a non-standard way, but using an inaccurate + value may break Chipyard components that rely on them (e.g. inaccurate indication of supported ISA extension will + result in incorrect test suite being generated) as well as any custom module that use them. ALWAYS document any + fields you ignore or with altered usage in your core implementation, and if you are implementing other devices that + would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but + you should document them if you use them. Tile Class ---------- -In Chipyard, all connections with other components on SoC are defined a core's `Tile` class, while the implementation -of the actual hardware are in the implementation class. This structure allows Chipyard to use the Diplomacy framework -to resolve paramters and connections before elaboration. +In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System +interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. +See :ref:`tilelink_and_diplomacy` for more details. All tile classes implement ``BaseTile`` and will normally implement ``SinksExternalInterrupts`` and ``SourcesExternalNotifications``, which allow the tile to accept external interrupt. A typical tile has the following form: @@ -169,7 +181,8 @@ TileLink Connection ------------------- Chipyard use TileLink as its onboard bus protocol, and if your core doesn't use TileLink, you will need to convert them -in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus: +in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by +Chipyards: .. code-block:: scala @@ -185,9 +198,12 @@ in the tile class. Below is an example of how to connect a core using AXI4 to th := memAXI4Node) // The custom node, see below Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate -widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Also, Chipyard -support AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol. See the reference page for -more info. +widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also +provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the +source files in ``generators/rocket-chip/src/main/scala/amba`` for more info. + +If you are using other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba`` +as the template, but it is not recommended unless you are familiar with TileLink. ``memAXI4Node`` is an AXI4 master node and is defined as following in our example: @@ -232,7 +248,8 @@ The definition of ``TileInterrupts`` is } This function should be in the implementation class since it involves hardware generation. -Also, the tile can also notify other cores or devices for some events by calling following functions (in implementation class): +Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications`` +from the implementation class: .. code-block:: scala @@ -241,39 +258,6 @@ Also, the tile can also notify other cores or devices for some events by calling reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed -Trace (Optional) ----------------- - -Chipyard provides a set of ports for instruction trace that conforms with related RISC-V standard. -If you are using FireSim, it is recommended to implement these trace ports to enable FireSim to read trace. - -There are one inbound node ``traceAuxSinkNode.bundle: TraceAux`` and two outbound nodes ``traceCoreSourceNode.bundle: TraceCoreInterface`` -and ``bpwatchSourceNode.bundle: Vec[BPWatch]``. Note that the length of ``bpwatchSourceNode`` is equal to the max number of -breakpoints (set by ``nBreakpoints`` in ``CoreParams``). Below is the definition of these types: - -.. code-block:: scala - - // Control signal from the external tracer - class TraceAux extends Bundle { - val enable = Bool() // Enable trace output - val stall = Bool() // If true, the core should stall - } - // Check RISC-V Processor Trace spec V1.0 for more information of this interface - class TraceCoreInterface (val params: TraceCoreParams) extends Bundle { - val group = Vec(params.nGroups, new TraceCoreGroup(params)) - val priv = UInt(4.W) - val tval = UInt(params.xlen.W) - val cause = UInt(params.xlen.W) - } - // Address Breakpoint and watchpoint info (n is the retire width) - class BPWatch (val n: Int) extends Bundle() { - val valid = Vec(n, Bool()) // Valid bit of the output - val rvalid = Vec(n, Bool()) // Break on read - val wvalid = Vec(n, Bool()) // Break on write - val ivalid = Vec(n, Bool()) // Break on execute - val action = UInt(3.W) // Exception code (3 usually) - } - Implementation Class -------------------- @@ -313,12 +297,13 @@ the current config. An example of such config will be like this: .. code-block:: scala - class WithNMyCores(n: Int) extends Config((site, here, up) => { - case MyTilesKey => { - List.tabulate(n)(i => MyTileParams(hartId = i)) - } + class WithNMyCores(n: Int, hartidOffset: Int) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) :++ List.tabulate(n)(i => MyTileParams(hartId = i + hartidOffset)) }) +Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``. +This config fragment simply appends new tile parameters to the end of this list. + Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`. You can now run any desired workflow for the new config just as you do for the built-in cores. diff --git a/docs/TileLink-Diplomacy-Reference/index.rst b/docs/TileLink-Diplomacy-Reference/index.rst index dfc2ec5a..9c70287d 100644 --- a/docs/TileLink-Diplomacy-Reference/index.rst +++ b/docs/TileLink-Diplomacy-Reference/index.rst @@ -1,3 +1,5 @@ +.. _tilelink_and_diplomacy: + TileLink and Diplomacy Reference ================================ From a7047c4ba2e7b9c4a2433a3e8ff0346bc3a67ab5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 1 Jul 2020 12:21:51 -0700 Subject: [PATCH 057/457] Fix FireChip BridgeBinders --- .../chipyard/src/main/scala/ChipTop.scala | 3 +- .../chipyard/src/main/scala/IOBinders.scala | 84 +++++++++++-------- .../src/main/scala/BridgeBinders.scala | 54 ++++++------ 3 files changed, 79 insertions(+), 62 deletions(-) diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index ea0c804d..d0b4df02 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -70,13 +70,12 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with val lSystem = p(BuildSystem)(p).suggestName("system") val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) } - // Call all of the IOBinders and provide them with a default clock and reset withClockAndReset(systemClock, systemReset) { // Call each IOBinder on both the lazyModule instance and the module // instance. Generally, an IOBinder PF should only be defined on one, so // this should not lead to two invocations. - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem, p) ++ f(system, p)).unzip3 + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3 // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 2b7cd41c..115723ab 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -5,7 +5,7 @@ import chisel3._ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} @@ -48,17 +48,32 @@ type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any] // 3. An optional function to call inside the test harness (e.g. to connect the IOs) type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction]) -case object IOBinders extends Field[Map[String, (Any, Parameters) => Seq[IOBinderTuple]]]( - Map[String, (Any, Parameters) => Seq[IOBinderTuple]]().withDefaultValue((Any, Parameters) => Nil) +case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]]( + Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil) ) +// Note: The parameters instance is accessible only through LazyModule +// or LazyModuleImpLike. The self-type requirement in traits like +// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder +// As a result, IOBinders only work on Modules which inherit LazyModule or +// or LazyModuleImpLike +object GetSystemParameters { + def apply(s: Any): Parameters = { + s match { + case s: LazyModule => s.p + case s: LazyModuleImpLike => s.p + case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike") + } + } +} + // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any, p: Parameters) => { + ((t: Any) => { t match { - case system: T => fn(system, p) + case system: T => fn(system) case _ => Nil } }) @@ -67,12 +82,12 @@ class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any, p: Parameters) => { + ((t: Any) => { t match { - case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system, p) - ++ fn(system, p)) + case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system) + ++ fn(system)) case _ => Nil } }) @@ -211,7 +226,7 @@ object AddIOCells { // DOC include start: WithGPIOTiedOff class WithGPIOTiedOff extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp, p) => { + (system: HasPeripheryGPIOModuleImp) => { val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) @@ -220,7 +235,7 @@ class WithGPIOTiedOff extends OverrideIOBinder({ // DOC include end: WithGPIOTiedOff class WithUARTAdapter extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp, p) => { + (system: HasPeripheryUARTModuleImp) => { val (ports, ioCells2d) = AddIOCells.uart(system.uart) val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -228,7 +243,7 @@ class WithUARTAdapter extends OverrideIOBinder({ }) class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ - (system: HasPeripherySPIFlashModuleImp, p) => { + (system: HasPeripherySPIFlashModuleImp) => { val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -236,7 +251,7 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ }) class WithSimBlockDevice extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p) @@ -247,7 +262,7 @@ class WithSimBlockDevice extends OverrideIOBinder({ }) class WithBlockDeviceModel extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { BlockDeviceModel.connect(Some(port))(system.p) @@ -258,26 +273,23 @@ class WithBlockDeviceModel extends OverrideIOBinder({ }) class WithLoopbackNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp, p) => system.connectNicLoopback(); Nil + (system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil }) class WithSimNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp, p) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil + (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) -// Note: The parameters instance is accessible only through the BaseSubsystem -// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The -// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it -// accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort, p) => { + (system: CanHaveMasterAXI4MemPort) => { + implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") // TODO: we are inlining the connectMem method of SimAXIMem because // it takes in a dut rather than seq of axi4 ports val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => - val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)(p)) + val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) Module(mem.module).suggestName("mem") mem.io_axi4.head <> port } @@ -289,7 +301,8 @@ class WithSimAXIMem extends OverrideIOBinder({ // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort, p) => { + (system: CanHaveMasterAXI4MemPort) => { + implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => @@ -307,11 +320,12 @@ class WithBlackBoxSimMem extends OverrideIOBinder({ }) class WithSimAXIMMIO extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MMIOPort, p) => { + (system: CanHaveMasterAXI4MMIOPort) => { + implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => - val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)(p)) + val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)) Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") mmio_mem.io_axi4.head <> port } @@ -322,11 +336,11 @@ class WithSimAXIMMIO extends OverrideIOBinder({ }) class WithDontTouchPorts extends OverrideIOBinder({ - (system: DontTouch, p) => system.dontTouchPorts(); Nil + (system: DontTouch) => system.dontTouchPorts(); Nil }) class WithTieOffInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp, p) => { + (system: HasExtInterruptsModuleImp) => { val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) port.suggestName("interrupts") val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil } @@ -335,7 +349,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4Port, p) => { + (system: CanHaveSlaveAXI4Port) => { val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => @@ -349,7 +363,7 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ }) class WithTiedOffDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp, p) => { + (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -367,7 +381,7 @@ class WithTiedOffDebug extends OverrideIOBinder({ }) class WithSimDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp, p) => { + (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -382,7 +396,7 @@ class WithSimDebug extends OverrideIOBinder({ }) class WithTiedOffSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { SerialAdapter.tieoff(port) @@ -393,7 +407,7 @@ class WithTiedOffSerial extends OverrideIOBinder({ }) class WithSimSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset) @@ -405,7 +419,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp, p) => { + (system: TraceGenSystemModuleImp) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } @@ -414,7 +428,7 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ }) class WithSimDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp, p) => { + (system: CanHaveTraceIOModuleImp) => { system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 6af7bd0a..eba57451 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -26,7 +26,7 @@ import ariane.ArianeTile import boom.common.{BoomTile} -import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} +import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters} import testchipip.{CanHaveTraceIOModuleImp} object MainMemoryConsts { @@ -35,63 +35,67 @@ object MainMemoryConsts { } class WithSerialBridge extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp, p) => - system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(p)); Nil + (system: CanHavePeripherySerialModuleImp) => + system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil }) class WithNICBridge extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp, p) => - system.net.foreach(n => NICBridge(system.clock, n)(p)); Nil + (system: CanHavePeripheryIceNICModuleImp) => + system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil }) class WithUARTBridge extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp, p) => - system.uart.foreach(u => UARTBridge(system.clock, u)(p)); Nil + (system: HasPeripheryUARTModuleImp) => + system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil }) class WithBlockDeviceBridge extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, p) => - system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(p)); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => + system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil }) class WithFASEDBridge extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort, p) => { + (system: CanHaveMasterAXI4MemPort) => { + implicit val p: Parameters = GetSystemParameters(system) (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) => val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, axi4.ar.bits.addr.getWidth, axi4.ar.bits.id.getWidth) - FASEDBridge(system.module.clock, axi4, system.module.reset.toBool, - CompleteConfig(p(firesim.configs.MemModelKey), - nastiKey, - Some(AXI4EdgeSummary(edge)), - Some(MainMemoryConsts.globalName))) + system match { + case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool, + CompleteConfig(p(firesim.configs.MemModelKey), + nastiKey, + Some(AXI4EdgeSummary(edge)), + Some(MainMemoryConsts.globalName))) + case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design") + } }) Nil } }) class WithTracerVBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp, p) => - system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(p))); Nil + (system: CanHaveTraceIOModuleImp) => + system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil }) class WithDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp, p) => { - system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(p))); Nil + (system: CanHaveTraceIOModuleImp) => { + system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil } }) class WithTraceGenBridge extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp, p) => + (system: TraceGenSystemModuleImp) => GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (system: HasTilesModuleImp, p) => { + (system: HasTilesModuleImp) => { system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -115,13 +119,13 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ }) class WithTiedOffSystemGPIO extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp, p) => + (system: HasPeripheryGPIOModuleImp) => system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil }) class WithTiedOffSystemDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp, p) => { - Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(p) + (system: HasPeripheryDebugModuleImp) => { + Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) // tieoffDebug doesn't actually tie everything off :/ system.debug.foreach { d => d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) @@ -132,7 +136,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({ }) class WithTiedOffSystemInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp, p) => + (system: HasExtInterruptsModuleImp) => system.interrupts := 0.U; Nil }) From 744e73fa9223c9b5571b91d388566b8a07ba8949 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 5 Jul 2020 21:05:21 -0700 Subject: [PATCH 058/457] Editing Docs --- docs/Customization/Custom-Core.rst | 179 ++++++------------ .../src/main/scala/example/TutorialTile.scala | 179 ++++++++++++++++++ 2 files changed, 241 insertions(+), 117 deletions(-) create mode 100644 generators/chipyard/src/main/scala/example/TutorialTile.scala diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index dcf2c257..17b9b125 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -3,21 +3,24 @@ Adding a custom core ==================== -You may want to add a custom RISC-V core to Chipyard generator. If the top module of your core is not in Chisel, -you will first need to create a Verilog blackbox for it. See :ref:`incorporating-verilog-blocks` for instructions. -Once you have a top module in Chisel, you are ready to create integrate it with Chipyard. - -``generators/ariane/src/main/scala/ArianeTile.scala`` and ``generators/boom/src/main/scala/common/tile.scala`` -provide two examples of how to integrate a core. +You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides a step-to-step +instruction on how to achieve this. .. note:: - RoCC is not supported by custom core currently. Please use Rocket or Boom as the RoCC base core if you need to use RoCC. + RoCC is currently not supported by cores other than Rocket and BOOM. Please use Rocket or BOOM as the RoCC base core if you need to use RoCC. -Parameter Case Classes ----------------------- -Chipyard will generate a core for every ``InstantiableTileParams`` object it discovered in the current config. +Wrap Verilog Module with Blackbox (Optional) +-------------------------------------------- + +Since Chipyard uses Scala and Chisel, if the top module of your core is not in Chisel, you will first need to create a Verilog +blackbox for it so that it can be processed by Chipyard. See :ref:`incorporating-verilog-blocks` for instructions. + +Create Parameter Case Classes +----------------------------- + +Chipyard will generate a core for every ``InstantiableTileParams`` object it discovered in the ``TilesLocated(InSubsystem)`` key. This object is derived from``TileParams``, a trait containing the information needed to create a tile. All cores must have their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``. @@ -41,7 +44,7 @@ need a custom field with similar purposes): val icache: Option[ICacheParams] // Rocket specific: I1 cache option val dcache: Option[DCacheParams] // Rocket specific: D1 cache option val btb: Option[BTBParams] // Rocket specific: BTB / branch predictor option - val hartId: Int // Hart ID: Must be unique within a design config + val hartId: Int // Hart ID: Must be unique within a design config (This MUST be a case class parameter) val beuAddr: Option[BigInt] // Rocket specific: Bus Error Unit for Rocket Core val blockerCtrlAddr: Option[BigInt] // Rocket specific: Bus Blocker for Rocket Core val name: Option[String] // Name of the core @@ -110,110 +113,64 @@ need a custom field with similar purposes): dfmaLatency: Int = 4 // Rocket specific: Fused multiply-add pipeline latency (double precision) ) -Most of the fields here are originally designed for Rocket core and contains some architecture-specific details, but +Most of the fields here are originally designed for the Rocket core and thus contain some implementation-specific details, but many of them are general enough to be useful for other cores. It is strongly recommended to use these fields instead of creating your own custom fields when applicable. +You will also need a ``CanAttachTile`` class to add the tile config into the config system, with the following format: + +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :lines: 61-67 + .. note:: Implementations may choose to ignore some fields here or use them in a non-standard way, but using an inaccurate - value may break Chipyard components that rely on them (e.g. inaccurate indication of supported ISA extension will - result in incorrect test suite being generated) as well as any custom module that use them. ALWAYS document any + value may break Chipyard components that rely on them (e.g. an inaccurate indication of supported ISA extension will + result in an incorrect test suite being generated) as well as any custom modules that use them. ALWAYS document any fields you ignore or with altered usage in your core implementation, and if you are implementing other devices that would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but you should document them if you use them. -Tile Class ----------- +Create Tile Class +----------------- In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. -See :ref:`tilelink_and_diplomacy` for more details. +See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core. All tile classes implement ``BaseTile`` and will normally implement ``SinksExternalInterrupts`` and ``SourcesExternalNotifications``, which allow the tile to accept external interrupt. A typical tile has the following form: -.. code-block:: scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :lines: 87-125, 143 - class MyTile( - val myParams: MyTileParams, - crossing: ClockCrossingType, - lookup: LookupByHartIdImpl, - q: Parameters, - logicalTreeNode: LogicalTreeNode) - extends BaseTile(myParams, crossing, lookup, q) - with SinksExternalInterrupts - with SourcesExternalNotifications - { +Connect TileLink Buses +---------------------- - // Private constructor ensures altered LazyModule.p is used implicitly - def this(params: MyTileParams, crossing: RocketCrossingParams, lookup: LookupByHartIdImpl, logicalTreeNode: LogicalTreeNode)(implicit p: Parameters) = - this(params, crossing.crossingType, lookup, p, logicalTreeNode) - - // Require TileLink nodes - val intOutwardNode = IntIdentityNode() - val masterNode = visibilityNode - val slaveNode = TLIdentityNode() - - // Implementation class (See below) - override lazy val module = new MyTileModuleImp(this) - - // Required entry of CPU device in the device tree for interrupt purpose - val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("my-organization,my-cpu", "riscv")) { - override def parent = Some(ResourceAnchors.cpus) - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - Description(name, mapping ++ - cpuProperties ++ - nextLevelCacheProperty ++ - tileProperties) - } - } - - ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) - } - - // (Connection to bus, interrupt, etc.) - } - -TileLink Connection -------------------- - -Chipyard use TileLink as its onboard bus protocol, and if your core doesn't use TileLink, you will need to convert them +Chipyard use TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters +between the core's memory protocol and TileLink in the Tile module. in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by -Chipyards: +Rocket chip: -.. code-block:: scala - - val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node - (tlMasterXbar.node // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar - := memoryTap - := TLBuffer() - := TLFIFOFixer(TLFIFOFixer.all) // fix FIFO ordering - := TLWidthWidget(beatBytes) // reduce size of TL - := AXI4ToTL() // convert to TL - := AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed - := AXI4Fragmenter() // deal with multi-beat xacts - := memAXI4Node) // The custom node, see below +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :lines: 133-142 Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the source files in ``generators/rocket-chip/src/main/scala/amba`` for more info. -If you are using other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba`` +If you are using some other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba`` as the template, but it is not recommended unless you are familiar with TileLink. ``memAXI4Node`` is an AXI4 master node and is defined as following in our example: -.. code-block:: scala - - val memAXI4Node = AXI4MasterNode( - Seq(AXI4MasterPortParameters( - masters = Seq(AXI4MasterParameters( - name = portName, - id = IdRange(0, 1 << idBits)))))) +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :lines: 126-132 where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile. Make sure to read :ref:`node_types` to check out what type of nodes Chipyard supports and their parameters! @@ -228,8 +185,8 @@ can override the following two functions to control how to buffer the bus reques You can find more information on ``TLBuffer`` in :ref:`diplomatic_widgets`. -Interrupt ---------- +Connect Interrupt +----------------- Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and @@ -258,48 +215,33 @@ from the implementation class: reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed -Implementation Class --------------------- +Create Implementation Class +--------------------------- -The implementation class is of the following form: +The implementation class for your core is of the following form: -.. code-block:: scala - - class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ - // annotate the parameters - Annotated.params(this, outer.tileParams) - - // TODO: Create the top module of the core and connect it with the ports in "outer" - } +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :lines: 145-149, 160 In the body of this class, you can look up any parameters by calling ``p({key})``, where ``{key}`` is the config key of -the value you want to look up. For a list of available keys, see the appendix below. +the value you want to look up. For a list of frequently used keys, see the appendix below. If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this: -.. code-block:: scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :lines: 151-159 - outer.myAXI4Node.out foreach { case (out, edgeOut) => - // Connect your module IO port to "out" - // The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala - // Please refer to this file for the definition of the ports. - // If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala - // If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala - // (choose one depends on the type of AHB node you create) - // If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala - } +Create Config Fragments to Integrate the Core +--------------------------------------------- -Integrate the Core ------------------- - -To use your core in a set of config, you would need a config fragment that would create a ``TileParams`` object of your core in +To use your core in a Chipyard config, you would need a config fragment that would create a ``TileParams`` object of your core in the current config. An example of such config will be like this: -.. code-block:: scala - - class WithNMyCores(n: Int, hartidOffset: Int) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) :++ List.tabulate(n)(i => MyTileParams(hartId = i + hartidOffset)) - }) +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :lines: 162-179 Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``. This config fragment simply appends new tile parameters to the end of this list. @@ -308,6 +250,9 @@ Now you have finished all the steps to prepare your cores for Chipyard! To gener in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`. You can now run any desired workflow for the new config just as you do for the built-in cores. +If you would like to see how an actual core are integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala`` +provides a concrete example of integrating a third party Verilog core Ariane. + Appendix: Common Config Keys ---------------------------- diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala new file mode 100644 index 00000000..12173184 --- /dev/null +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -0,0 +1,179 @@ +package chipyard.example + +import chisel3._ +import chisel3.util._ + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode} +import freechips.rocketchip.rocket._ +import freechips.rocketchip.subsystem.{RocketCrossingParams} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.tile._ +import freechips.rocketchip.amba.axi4._ + +// Example parameter class copied from Ariane, not included in documentation but for compile check only +// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure +// out what parameters you need before you write the parameter class +case class MyCoreParams( + bootFreqHz: BigInt = BigInt(1700000000), + rasEntries: Int = 4, + btbEntries: Int = 16, + bhtEntries: Int = 16, + enableToFromHostCaching: Boolean = false, +) extends CoreParams { + val useVM: Boolean = true + val useUser: Boolean = true + val useSupervisor: Boolean = false + val useDebug: Boolean = true + val useAtomics: Boolean = true + val useAtomicsOnlyForIO: Boolean = false // copied from Rocket + val useCompressed: Boolean = true + override val useVector: Boolean = false + val useSCIE: Boolean = false + val useRVE: Boolean = false + val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket + val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket + val nLocalInterrupts: Int = 0 + val nPMPs: Int = 0 // TODO: Check + val pmpGranularity: Int = 4 // copied from Rocket + val nBreakpoints: Int = 0 // TODO: Check + val useBPWatch: Boolean = false + val nPerfCounters: Int = 29 + val haveBasicCounters: Boolean = true + val haveFSDirty: Boolean = false + val misaWritable: Boolean = false + val haveCFlush: Boolean = false + val nL2TLBEntries: Int = 512 // copied from Rocket + val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket + val mtvecWritable: Boolean = true // copied from Rocket + val instBits: Int = if (useCompressed) 16 else 32 + val lrscCycles: Int = 80 // copied from Rocket + val decodeWidth: Int = 1 // TODO: Check + val fetchWidth: Int = 1 // TODO: Check + val retireWidth: Int = 2 +} + +case class MyTileAttachParams( + tileParams: MyTileParams, + crossingParams: RocketCrossingParams +) extends CanAttachTile { + type TileType = MyTile + val lookup = PriorityMuxHartIdFromSeq(Seq(tileParams)) +} + +case class MyTileParams( + name: Option[String] = Some("my_tile"), + hartId: Int = 0, + trace: Boolean = false, + val core: MyCoreParams = MyCoreParams() +) extends InstantiableTileParams[MyTile] +{ + val beuAddr: Option[BigInt] = None + val blockerCtrlAddr: Option[BigInt] = None + val btb: Option[BTBParams] = Some(BTBParams()) + val boundaryBuffers: Boolean = false + val dcache: Option[DCacheParams] = Some(DCacheParams()) + val icache: Option[ICacheParams] = Some(ICacheParams()) + def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { + new MyTile(this, crossing, lookup) + } +} + +class MyTile( + val myParams: MyTileParams, + crossing: ClockCrossingType, + lookup: LookupByHartIdImpl, + q: Parameters) + extends BaseTile(myParams, crossing, lookup, q) + with SinksExternalInterrupts + with SourcesExternalNotifications +{ + + // Private constructor ensures altered LazyModule.p is used implicitly + def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + this(params, crossing.crossingType, lookup, p) + + // Require TileLink nodes + val intOutwardNode = IntIdentityNode() + val masterNode = visibilityNode + val slaveNode = TLIdentityNode() + + // Implementation class (See below) + override lazy val module = new MyTileModuleImp(this) + + // Required entry of CPU device in the device tree for interrupt purpose + val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("my-organization,my-cpu", "riscv")) { + override def parent = Some(ResourceAnchors.cpus) + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + Description(name, mapping ++ + cpuProperties ++ + nextLevelCacheProperty ++ + tileProperties) + } + } + + ResourceBinding { + Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) + } + + // (Connection to bus, interrupt, etc.) + // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. + val idBits = 4 + val memAXI4Node = AXI4MasterNode( + Seq(AXI4MasterPortParameters( + masters = Seq(AXI4MasterParameters( + name = "myPortName", + id = IdRange(0, 1 << idBits)))))) + val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node + (tlMasterXbar.node // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar + := memoryTap + := TLBuffer() + := TLFIFOFixer(TLFIFOFixer.all) // fix FIFO ordering + := TLWidthWidget(masterPortBeatBytes) // reduce size of TL + := AXI4ToTL() // convert to TL + := AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed + := AXI4Fragmenter() // deal with multi-beat xacts + := memAXI4Node) // The custom node, see below +} + +class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ + // annotate the parameters + Annotated.params(this, outer.myParams) + + // TODO: Create the top module of the core and connect it with the ports in "outer" + + outer.memAXI4Node.out foreach { case (out, edgeOut) => + // Connect your module IO port to "out" + // The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala + // Please refer to this file for the definition of the ports. + // If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala + // If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala + // (choose one depends on the type of AHB node you create) + // If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala + } +} + +class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + // Calculate the next available hart ID (since hart ID cannot be duplicated) + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + // Create TileAttachParams for every core to be instantiated + (0 until n).map { i => + MyTileAttachParams( + tileParams = MyTileParams(hartId = i + idOffset), + crossingParams = RocketCrossingParams() + ) + } ++ prev + } + // Configurate # of bytes in one memory / IO transaction. For RV64, one load/store instruction can transfer 8 bytes at most. + case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8) + // The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits. + case XLen => 64 +}) From 6cb8a60a808d426a111cd470cf360460bbde3cbd Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 5 Jul 2020 21:18:31 -0700 Subject: [PATCH 059/457] Remove Key List --- docs/Customization/Custom-Core.rst | 83 ------------------------------ 1 file changed, 83 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 17b9b125..94d47505 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -224,9 +224,6 @@ The implementation class for your core is of the following form: :language: scala :lines: 145-149, 160 -In the body of this class, you can look up any parameters by calling ``p({key})``, where ``{key}`` is the config key of -the value you want to look up. For a list of frequently used keys, see the appendix below. - If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this: .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -252,83 +249,3 @@ You can now run any desired workflow for the new config just as you do for the b If you would like to see how an actual core are integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala`` provides a concrete example of integrating a third party Verilog core Ariane. - -Appendix: Common Config Keys ----------------------------- - -Chipyard provide a set of keys to store standard parameters. Below are some of the most common key used in core integration. -(Note that internal fields are hidden) - -.. code-block:: scala - - // keys - // Parameters exposed to the top-level design, set based on external requirements, etc. See RISC-V debug specs for more info. - case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) - case object BootROMParams extends Field[BootROMParams] // See chipyard boot process tutorial - case object CLINTKey extends Field[Option[CLINTParams]](None) // Core Local Interrupter setting (See SiFive Interrupt Cookbook) - case object PLICKey extends Field[Option[PLICParams]](None) // Platform Level Interrupt Controller setting (See SiFive Interrupt Cookbook) - case object CacheBlockBytes extends Field[Int](64) // # of bytes in a cache block - case object BroadcastKey extends Field(BroadcastParams()) // L2 Cache broadcast setting - case object BankedL2Key extends Field(BankedL2Params()) // L2 Cache memory setting - case object PgLevels extends Field[Int](2) // Page Level of virtual memory - case object ASIdBits extends Field[Int](0) // Max # of bits for Address Space Identifer (See specs) - case object ExtMem extends Field[Option[MemoryPortParams]](None) // External DRAM setting - case object ExtBus extends Field[Option[MasterPortParams]](None) // External (off-chip) output bus setting - case object ExtIn extends Field[Option[SlavePortParams]](None) // External (off-chip) input bus setting - case object MaxHartIdBits extends Field[Int] // Max # of bits used to represent a Hart ID - case object XLen extends Field[Int] // Instruction bits (32 or 64) - case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil) // See custom ROCC tutorial - - // Values - case class DebugModuleParams ( - nDMIAddrSize : Int = 7, // Size of the Debug Bus Address - nProgramBufferWords: Int = 16, // Number of 32-bit words for Program Buffer - nAbstractDataWords : Int = 4, // Number of 32-bit words for Abstract Commands - nScratch : Int = 1, // Number of scratch memories used - hasBusMaster : Boolean = false, // Whether or not a bus master should be included - clockGate : Boolean = true, // Use clock gating - maxSupportedSBAccess : Int = 32, // Maximum transaction size supported by System Bus Access logic. - supportQuickAccess : Boolean = false, // Whether or not to support the quick access command. - supportHartArray : Boolean = true, // Whether or not to implement the hart array register (if >1 hart). - nHaltGroups : Int = 1, // Number of halt groups (group of harts that are halted together) - nExtTriggers : Int = 0, // Number of extra triggers - hasHartResets : Boolean = false, // Whether harts can be reseted with debugging system - hasImplicitEbreak : Boolean = false, // There is an additional RO program buffer word containing an ebreak - hasAuthentication : Boolean = false, // Has authentication (to prevent unauthorized users to use debugging system) - crossingHasSafeReset : Boolean = true // Include "safe" logic in Async Crossings so that only one side needs to be reset. - ) - case class CLINTParams( - baseAddress: BigInt = 0x02000000, // Default interrupt handler base address for CLINT - intStages: Int = 0 // # of cycles (stages) interrupts are delayed - ) - case class PLICParams( - baseAddress: BigInt = 0xC000000, // Default interrupt handler base address for PLIC - maxPriorities: Int = 7, // Maximum allowed interrupt priority (cannot be over 7) - intStages: Int = 0, // # of cycles (stages) interrupts are delayed - maxHarts: Int = PLICConsts.maxMaxHarts // Maximum number or hart / core connected to it - ) - case class BroadcastParams( - nTrackers: Int = 4, // # of broadcast tracker - bufferless: Boolean = false // Bufferless broadcast - ) - case class BankedL2Params( - nBanks: Int = 1 // Number of banks in L2 cache - ) - case class MasterPortParams( - base: BigInt, // Base memory address for this port - size: BigInt, // Size of this external memory - beatBytes: Int, // Interface width in bytes - idBits: Int, // # of bits in the port ID - maxXferBytes: Int = 256, // Maximum bytes in one transfer transaction - executable: Boolean = true // If the data from this port can be executed as instruciton - ) - /** Specifies the width of external slave ports */ - case class SlavePortParams( - beatBytes: Int, // Interface width in bytes - idBits: Int, // # of bits in the port ID - sourceBits: Int // # of bits in the source address - ) - case class MemoryPortParams( - master: MasterPortParams, // The memory port setting - nMemoryChannels: Int // Number of memory channel - ) From 661038f992b281b0f39ea58c45216128e476a18f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 3 Jul 2020 16:21:30 -0700 Subject: [PATCH 060/457] Deduplicate across Chiypard configs into a ChipyardBaseConfig --- docs/Customization/Heterogeneous-SoCs.rst | 51 +- .../src/main/scala/ConfigFragments.scala | 13 + .../main/scala/config/AbstractConfig.scala | 26 + .../src/main/scala/config/ArianeConfigs.scala | 35 +- .../src/main/scala/config/BoomConfigs.scala | 141 +----- .../src/main/scala/config/HeteroConfigs.scala | 104 +--- .../src/main/scala/config/RocketConfigs.scala | 461 ++---------------- .../RocketConfigs.scala.patch | 16 +- 8 files changed, 129 insertions(+), 718 deletions(-) create mode 100644 generators/chipyard/src/main/scala/config/AbstractConfig.scala diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index c640e31c..155d623d 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -8,7 +8,7 @@ Creating a Rocket and BOOM System ------------------------------------------- Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific config fragments. -Both BOOM and Rocket have config fragments labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_. +Both BOOM and Rocket have config fragments labelled ``WithN{Small|Medium|Large|etc.}BoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_. When used together you can create a heterogeneous system. The following example shows a dual core BOOM with a single core Rocket. @@ -18,52 +18,6 @@ The following example shows a dual core BOOM with a single core Rocket. :start-after: DOC include start: DualBoomAndRocket :end-before: DOC include end: DualBoomAndRocket -In this example, the ``WithNBoomCores`` and ``WithNBigCores`` config fragments set up the default parameters for the multiple BOOM and Rocket cores, respectively. -However, for BOOM, an extra config fragment called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters. -This config fragment applies to all BOOM cores in the system and changes the parameters for each. - -Great! Now you have a heterogeneous setup with BOOMs and Rockets. -The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId`` (a ``hartId`` is the hardware thread id of the core). -The ``WithRenumberHarts`` config fragment solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first). -The reason this is needed is because by default the ``WithN...Cores(X)`` config fragment assumes that there are only BOOM or only Rocket cores in the system. -Thus, without the ``WithRenumberHarts`` config fragment, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. - -Another alternative option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core. -The config fragment to add to your system would look something like the following. - -.. code-block:: scala - - // create 6 cores (4 boom and 2 rocket) - class WithHeterCoresSetup extends Config((site, here, up) => { - case BoomTilesKey => { - val boomTile0 = BoomTileParams(...) // params for boom core 0 - val boomTile1 = BoomTileParams(...) // params for boom core 1 - val boomTile2 = BoomTileParams(...) // params for boom core 2 - val boomTile3 = BoomTileParams(...) // params for boom core 3 - Seq(boomTile0, boomTile1, boomTile2, boomTile3) - } - - case RocketTilesKey => { - val rocketTile0 = RocketTileParams(...) // params for rocket core 0 - val rocketTile1 = RocketTileParams(...) // params for rocket core 1 - Seq(rocketTile0, rocketTile1) - } - }) - -Then you could use this new config fragment like the following. - -.. code-block:: scala - - class SixCoreConfig extends Config( - new WithTSI ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithHeterCoresSetup ++ - new freechips.rocketchip.system.BaseConfig) - -Note, in this setup you need to specify the ``hartId`` of each core in the "TileParams", where each ``hartId`` is unique. Adding Hwachas ------------------------------------------- @@ -92,8 +46,7 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a :start-after: DOC include start: DualBoomAndRocketOneHwacha :end-before: DOC include end: DualBoomAndRocketOneHwacha -In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores. -Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core). +The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core). Finally, the ``WithMultiRoCC`` config fragment is called. This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default. This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter. diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index ad33fa47..024f5695 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -130,3 +130,16 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { case other => other } }) + +class WithRocketICacheScratchpad extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site) map { r => + r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000)))) + } +}) + +class WithRocketDCacheScratchpad extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site) map { r => + r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000)))) + } +}) + diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala new file mode 100644 index 00000000..22f64925 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -0,0 +1,26 @@ +package chipyard.config + +import freechips.rocketchip.config.{Config} + +// -------------- +// Chipyard abstract ("base") configuration +// NOTE: This configuration is NOT INSTANTIABLE, as it defines a empty system with no tiles +// -------------- + +class AbstractConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 6fb2ef00..7bc985aa 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -9,34 +9,11 @@ import freechips.rocketchip.config.{Config} // --------------------- class ArianeConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new ariane.WithNArianeCores(1) ++ // single Ariane core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new ariane.WithNArianeCores(1) ++ // single Ariane core + new chipyard.config.AbstractConfig) class dmiArianeConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffSerial ++ - new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new ariane.WithNArianeCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.iobinders.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation, override default tie-off debug + new ariane.WithNArianeCores(1) ++ // single Ariane core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 7b66e3b3..1f41c252 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -7,151 +7,40 @@ import freechips.rocketchip.config.{Config} // --------------------- class SmallBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new boom.common.WithNSmallBooms(1) ++ // small boom config - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.config.AbstractConfig) class MediumBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithNMediumBooms(1) ++ // medium boom config - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new boom.common.WithNMediumBooms(1) ++ // medium boom config + new chipyard.config.AbstractConfig) class LargeBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithNLargeBooms(1) ++ // large boom config - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class MegaBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithNMegaBooms(1) ++ // mega boom config - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new boom.common.WithBoomBranchPrintf ++ + new boom.common.WithNMegaBooms(1) ++ // mega boom config + new chipyard.config.AbstractConfig) class DualSmallBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithNSmallBooms(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new boom.common.WithNSmallBooms(2) ++ // 2 boom cores + new chipyard.config.AbstractConfig) class HwachaLargeBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new boom.common.WithNLargeBooms(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class LoopbackNICLargeBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback - new testchipip.WithTSI ++ - new icenet.WithIceNIC ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new icenet.WithIceNIC ++ // build a NIC new boom.common.WithNLargeBooms(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class DromajoBoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithSimDromajoBridge ++ // attach Dromajo - new testchipip.WithTSI ++ new chipyard.config.WithTraceIO ++ // enable the traceio - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithNSmallBooms(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index a7d1c133..9eb0b2f5 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -7,108 +7,38 @@ import freechips.rocketchip.config.{Config} // --------------------- class LargeBoomAndRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new boom.common.WithNLargeBooms(1) ++ // single-core boom - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.config.AbstractConfig) // DOC include start: BoomAndRocketWithHwacha class HwachaLargeBoomAndHwachaRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new boom.common.WithNLargeBooms(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts + new boom.common.WithNLargeBooms(1) ++ // add 1 boom core + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core + new chipyard.config.AbstractConfig) // DOC include end: BoomAndRocketWithHwacha -// DOC include start: DualBoomAndRocketOneHwacha +// DOC include start: DualBoomAndRocketOneHwacha class LargeBoomAndHwachaRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-1 (rocket) - new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithNLargeBooms(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys + new boom.common.WithNLargeBooms(1) ++ // add 1 boom core + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core + new chipyard.config.AbstractConfig) // DOC include end: DualBoomAndRocketOneHwacha // DOC include start: DualBoomAndRocket class DualLargeBoomAndDualRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithNLargeBooms(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // add 2 rocket cores + new chipyard.config.AbstractConfig) // DOC include end: DualBoomAndRocket class LargeBoomAndRocketWithControlCoreConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small control core - new boom.common.WithNLargeBooms(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core + new boom.common.WithNLargeBooms(1) ++ // Add 1 boom core + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 3dc7d22d..8e6e4867 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -7,556 +7,179 @@ import freechips.rocketchip.config.{Config} // -------------- class RocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.config.AbstractConfig) class HwachaRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include start: GemminiRocketConfig class GemminiRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: GemminiRocketConfig -class RoccRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - // DOC include start: JtagRocket class jtagRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.iobinders.WithSimDebug ++ // add SimDebug, in addition to default SimSerial new freechips.rocketchip.subsystem.WithJtagDTM ++ // sets DTM communication interface to JTAG - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: JtagRocket // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffSerial ++ - new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new chipyard.iobinders.WithTiedOffSerial ++ // tie-off serial, override default add SimSerial + new chipyard.iobinders.WithSimDebug ++ // add SimDebug, override default tie-off debug new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: DmiRocket // DOC include start: GCDTLRocketConfig class GCDTLRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: GCDTLRocketConfig // DOC include start: GCDAXI4BlackBoxRocketConfig class GCDAXI4BlackBoxRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig class LargeSPIFlashROMRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ new chipyard.config.WithSPIFlash ++ // add the SPI flash controller - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class SmallSPIFlashRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class SimAXIRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class SimBlockDeviceRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice - new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class BlockDeviceModelRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel - new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include start: GPIORocketConfig class GPIORocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top - new testchipip.WithTSI ++ new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: GPIORocketConfig class QuadRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class RV32RocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class GB1MemoryRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include start: Sha3Rocket class Sha3RocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: Sha3Rocket // DOC include start: InitZeroRocketConfig class InitZeroRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: InitZeroRocketConfig class LoopbackNICRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback - new testchipip.WithTSI ++ new icenet.WithIceNIC ++ // add an IceNIC - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include start: l1scratchpadrocket -class L1ScratchpadSmallRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ +class ScratchpadOnlyRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) // DOC include end: l1scratchpadrocket +class L1ScratchpadRocketConfig extends Config( + new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad + new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + // DOC include start: mbusscratchpadrocket class MbusScratchpadRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: mbusscratchpadrocket // DOC include start: RingSystemBusRocket class RingSystemBusRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new testchipip.WithRingSystemBus ++ // Ring-topology system bus - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: RingSystemBusRocket class StreamingPassthroughRocketConfig extends Config( new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include start: StreamingFIRRocketConfig class StreamingFIRRocketConfig extends Config ( new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) // DOC include end: StreamingFIRRocketConfig class SmallNVDLARocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class LargeNVDLARocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) class MMIORocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithTieOffL2FBusAXI ++ // Tie-off the incoming MMIO port new chipyard.iobinders.WithSimAXIMMIO ++ // Attach a simulated memory to the outwards MMIO port - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port + new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.config.AbstractConfig) diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch index cc9910c7..351f8ca2 100644 --- a/scripts/tutorial-patches/RocketConfigs.scala.patch +++ b/scripts/tutorial-patches/RocketConfigs.scala.patch @@ -1,13 +1,13 @@ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -index f29c580..0bd36ca 100644 +index 8e6e486..fc3a811 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -@@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config( - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ +@@ -105,7 +105,7 @@ class GB1MemoryRocketConfig extends Config( + + // DOC include start: Sha3Rocket + class Sha3RocketConfig extends Config( - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator +// new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + // DOC include end: Sha3Rocket From c023cf06883cd5581d012162add5e49038ac5800 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 23 Jun 2020 14:56:46 -0700 Subject: [PATCH 061/457] Rough initial implementation of diplomatic multiclock --- .../chipyard/src/main/scala/ChipTop.scala | 134 ++++++------------ .../chipyard/src/main/scala/Clocks.scala | 115 +++++++++++++++ .../src/main/scala/ConfigFragments.scala | 7 + .../chipyard/src/main/scala/IOBinders.scala | 4 +- .../chipyard/src/main/scala/Subsystem.scala | 24 +++- .../chipyard/src/main/scala/TestHarness.scala | 9 +- .../main/scala/config/AbstractConfig.scala | 1 + .../main/scala/config/TracegenConfigs.scala | 5 + .../main/scala/config/TutorialConfigs.scala | 4 + 9 files changed, 207 insertions(+), 96 deletions(-) create mode 100644 generators/chipyard/src/main/scala/Clocks.scala diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index d0b4df02..0227feb8 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -4,8 +4,10 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} +import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} +import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike} import freechips.rocketchip.util.{ResetCatchAndSync} import chipyard.config.ConfigValName._ import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple} @@ -14,108 +16,62 @@ import barstools.iocell.chisel._ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => LazyModule(new DigitalTop()(p))) -/** - * Chipyard provides three baseline, top-level reset schemes, set using the - * [[GlobalResetSchemeKey]] in a Parameters instance. These are: - * - * 1) Synchronous: The input coming to the chip is synchronous to the provided - * clocks and will be used without modification as a synchronous reset. - * This is safe only for use in FireSim and SW simulation. - * - * 2) Asynchronous: The input reset is asynchronous to the input clock, but it - * is caught and synchronized to that clock before it is dissemenated. - * Thus, downsteam modules will be emitted with synchronously reset state - * elements. - * - * 3) Asynchronous Full: The input reset is asynchronous to the input clock, - * and is used globally as an async reset. Downstream modules will be emitted - * with asynchronously reset state elements. - * - */ -sealed trait GlobalResetScheme { - def pinIsAsync: Boolean -} -sealed trait HasAsyncInput { self: GlobalResetScheme => - def pinIsAsync = true -} - -sealed trait HasSyncInput { self: GlobalResetScheme => - def pinIsAsync = false -} - -case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput -case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput -case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput -case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous) - /** * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, - * named "system", which is an instance of DigitalTop by default. The default clock and reset for "system" are set by two - * wires, "systemClock" and "systemReset", which are intended to be driven by traits mixed-in with this base class. + * named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock, + * is aggregated into the clockGroupNode. The parameterized functions controlled by ChipyardClockKey and GlobalResetSchemeKey + * drive clock and reset generation */ -abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with HasTestHarnessFunctions { +class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions { // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) val iocells = ArrayBuffer.empty[IOCell] // A list of functions to call in the test harness val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction] - // The system clock - // These are given so that IOCell can use DataMirror and generate ports with - // the right flow (Input/Output) - val systemClock = Wire(Input(Clock())) - val systemReset = Wire(Input(Reset())) // The system module specified by BuildSystem val lSystem = p(BuildSystem)(p).suggestName("system") - val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) } - // Call all of the IOBinders and provide them with a default clock and reset - withClockAndReset(systemClock, systemReset) { - // Call each IOBinder on both the lazyModule instance and the module - // instance. Generally, an IOBinder PF should only be defined on one, so - // this should not lead to two invocations. - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3 - // We ignore _ports for now... - iocells ++= _iocells.flatten - harnessFunctions ++= _harnessFunctions.flatten + // The systemClockSinkNode provides the implicit clock and reset for the System + private val systemClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) + + // clockGroupNode provides a single node which aggregates all clock groups in the design + val clockGroupNode = ClockGroupIdentityNode() + + // If the specified system has diplomatic clocks, connect it to our clockGroupNode + if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { + lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode :*= clockGroupNode } } + // Connect the system implicit clock node to the clockGroupNode + systemClockSinkNode := ClockGroup() := clockGroupNode + // Drive the entire diplomatic clock network using this configured Key + clockGroupNode :*=* p(ChipyardClockKey)(this) + + // NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children + // of ChipTop (ex: ClockGroup) do not receive clock or reset. + // However. anonymous children of ChipTop should not need an implicit Clock or Reset + // anyways, they probably need to be explicitly clocked. + lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) { + // These become the implicit clock and reset to the System + val system_clock = systemClockSinkNode.in.head._1.clock + val system_reset = systemClockSinkNode.in.head._1.reset + + // The implicit clock and reset for the system is also, by convention, used for all the IOBinders + // TODO: This may not be the right thing to do in all cases + withClockAndReset(system_clock, system_reset) { + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(lSystem.module)).unzip3 + // We ignore _ports for now... + iocells ++= _iocells.flatten + harnessFunctions ++= _harnessFunctions.flatten + } + + // Connect the implicit clock/reset, if present + lSystem.module match { case l: LazyModuleImp => { + l.clock := system_clock + l.reset := system_reset + }} + } } -/** - * A simple clock and reset implementation that punches out clock and reset ports with the same - * names as the implicit clock and reset for standard Module classes. Three basic reset schemes - * are provided. See [[GlobalResetScheme]]. - */ -trait HasChipTopSimpleClockAndReset { this: BaseChipTop => - - val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) - val (reset, systemResetIO) = p(GlobalResetSchemeKey) match { - case GlobalResetSynchronous => - IOCell.generateIOFromSignal(systemReset, Some("iocell_reset")) - case GlobalResetAsynchronousFull => - IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"), abstractResetAsAsync = true) - case GlobalResetAsynchronous => - val asyncResetCore = Wire(Input(AsyncReset())) - systemReset := ResetCatchAndSync(systemClock, asyncResetCore.asBool) - IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_reset"), abstractResetAsAsync = true) - } - - iocells ++= systemClockIO - iocells ++= systemResetIO - - // Add a TestHarnessFunction that connects clock and reset - harnessFunctions += { (th: TestHarness) => { - // Connect clock; it's not done implicitly with RawModule - clock := th.clock - // Connect reset; it's not done implicitly with RawModule - // Note that we need to use dutReset, not harnessReset - reset := th.dutReset - Nil - } } - -} - -class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p) - with HasChipTopSimpleClockAndReset diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala new file mode 100644 index 00000000..b9508d96 --- /dev/null +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -0,0 +1,115 @@ +package chipyard + +import chisel3._ + +import scala.collection.mutable.{ArrayBuffer} + +import freechips.rocketchip.prci._ +import freechips.rocketchip.subsystem.{BaseSubsystem} +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody} +import freechips.rocketchip.util.{ResetCatchAndSync} +import chipyard.config.ConfigValName._ + +import barstools.iocell.chisel._ + +import ChipyardClockDrivers._ + +case object ChipyardClockKey extends Field[ClockInstantiationFn](simpleTestHarnessClock) + + +/** + * Chipyard provides three baseline, top-level reset schemes, set using the + * [[GlobalResetSchemeKey]] in a Parameters instance. These are: + * + * 1) Synchronous: The input coming to the chip is synchronous to the provided + * clocks and will be used without modification as a synchronous reset. + * This is safe only for use in FireSim and SW simulation. + * + * 2) Asynchronous: The input reset is asynchronous to the input clock, but it + * is caught and synchronized to that clock before it is dissemenated. + * Thus, downsteam modules will be emitted with synchronously reset state + * elements. + * + * 3) Asynchronous Full: The input reset is asynchronous to the input clock, + * and is used globally as an async reset. Downstream modules will be emitted + * with asynchronously reset state elements. + * + */ +sealed trait GlobalResetScheme { + def pinIsAsync: Boolean +} +sealed trait HasAsyncInput { self: GlobalResetScheme => + def pinIsAsync = true +} + +sealed trait HasSyncInput { self: GlobalResetScheme => + def pinIsAsync = false +} + +case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput +case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput +case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput +case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous) + +/** + * A simple reset implementation that punches out reset ports + * for standard Module classes. Three basic reset schemes + * are provided. See [[GlobalResetScheme]]. + */ +object GenerateReset { + def apply(chiptop: ChipTop, clock: Clock): Reset = { + implicit val p = chiptop.p + // this needs directionality so generateIOFromSignal works + val reset_wire = Wire(Input(Reset())) + val (reset_io, resetIOCell) = p(GlobalResetSchemeKey) match { + case GlobalResetSynchronous => + IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset")) + case GlobalResetAsynchronousFull => + IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset"), abstractResetAsAsync = true) + case GlobalResetAsynchronous => { + val async_reset_wire = Wire(Input(AsyncReset())) + reset_wire := ResetCatchAndSync(clock, async_reset_wire.asBool()) + IOCell.generateIOFromSignal(async_reset_wire, Some("iocell_reset"), abstractResetAsAsync = true) + } + } + reset_io.suggestName("reset") + chiptop.iocells ++= resetIOCell + chiptop.harnessFunctions += ((th: TestHarness) => { + reset_io := th.dutReset + Nil + }) + reset_wire + } +} + +object ChipyardClockDrivers { + type ClockInstantiationFn = ChipTop => OutwardNodeHandle[ClockGroupSourceParameters, ClockGroupSinkParameters, ClockGroupEdgeParameters, ClockGroupBundle] + + // A simple clock provider, for testing. All clocks in system are aggregated into one, + // and are driven by directly punching out to the TestHarness clock + val simpleTestHarnessClock: ClockInstantiationFn = { chiptop => + implicit val p = chiptop.p + val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + InModuleBody { + // this needs directionality so generateIOFromSignal works + val clock_wire = Wire(Input(Clock())) + val reset_wire = GenerateReset(chiptop, clock_wire) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) + chiptop.iocells ++= clockIOCell + + clock_io.suggestName("clock") + + simpleClockGroupSourceNode.out.unzip._1.flatMap(_.member).map { o => + o.clock := clock_wire + o.reset := reset_wire + } + + chiptop.harnessFunctions += ((th: TestHarness) => { + clock_io := th.clock + Nil + }) + } + ClockGroupAggregator() := simpleClockGroupSourceNode + } +} diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 024f5695..ac70f8e5 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -143,3 +143,10 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) +// The default RocketChip BaseSubsystem drives its diplomatic clock graph +// with the implicit clocks of Subsystem. Don't do that, instead we extend +// the diplomacy graph upwards into the ChipTop, where we connect it to +// our clock drivers +class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { + case SubsystemDriveAsyncClockGroupsKey => None +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 115723ab..3f986757 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -201,14 +201,14 @@ object AddIOCells { } def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { - io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { + io.zip(node.edges.in).zipWithIndex.map{ case ((mem_axi4, edge), i) => { val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_slave_${i}")) port.suggestName(s"${name}_axi4_slave_${i}") (port, edge, ios) }} } def axi4(io: Seq[AXI4Bundle], node: AXI4MasterNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { - io.zip(node.out).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { + io.zip(node.edges.out).zipWithIndex.map{ case ((mem_axi4, edge), i) => { //val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_master_${i}")) val port = IO(Flipped(AXI4Bundle(edge.bundle))) val ios = IOCell.generateFromSignal(mem_axi4, port, Some(s"iocell_${name}_axi4_master_${i}")) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 3ca5ab11..50714cc4 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -8,6 +8,7 @@ package chipyard import chisel3._ import chisel3.internal.sourceinfo.{SourceInfo} +import freechips.rocketchip.prci._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} @@ -48,6 +49,10 @@ trait CanHaveHTIF { this: BaseSubsystem => } +// Controls whether tiles are driven by implicit subsystem clock, or by +// diplomatic clock graph +case object UseDiplomaticTileClocks extends Field[Boolean](false) + class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem with HasTiles with CanHaveHTIF @@ -56,6 +61,19 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle }.toList + + // TODO: In the future, RC tiles may extend ClockDomain. When that happens, + // we won't need to manually create this clock node and connect it to the + // tiles' implicit clocks + + val tilesClockSinkNode = if (p(UseDiplomaticTileClocks)) { + val node = ClockSinkNode(List(ClockSinkParameters())) + node := ClockGroup()(p, ValName("chipyard_tiles")) := asyncClockGroupsNode + Some(node) + } else { + None + } + override lazy val module = new ChipyardSubsystemModuleImp(this) } @@ -64,11 +82,15 @@ class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends Bas with HasResetVectorWire with HasTilesModuleImp { - for (i <- 0 until outer.tiles.size) { val wire = tile_inputs(i) wire.hartid := outer.hartIdList(i).U wire.reset_vector := global_reset_vector + + outer.tilesClockSinkNode.map( n => { + outer.tiles(i).module.clock := n.in.head._1.clock + outer.tiles(i).module.reset := n.in.head._1.reset + }) } // create file with core params diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index a82d3a33..9344cadf 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -8,10 +8,10 @@ import chipyard.iobinders.{TestHarnessFunction} import chipyard.config.ConfigValName._ // ------------------------------- -// BOOM and/or Rocket Test Harness +// Chipyard Test Harness // ------------------------------- -case object BuildTop extends Field[Parameters => HasTestHarnessFunctions]((p: Parameters) => Module(new ChipTop()(p))) +case object BuildTop extends Field[Parameters => LazyModule with HasTestHarnessFunctions]((p: Parameters) => LazyModule(new ChipTop()(p))) trait HasTestHarnessFunctions { val harnessFunctions: Seq[TestHarnessFunction] @@ -22,13 +22,14 @@ class TestHarness(implicit val p: Parameters) extends Module { val success = Output(Bool()) }) - val dut = p(BuildTop)(p) + val ldut = p(BuildTop)(p) + val dut = Module(ldut.module) io.success := false.B // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) - dut.harnessFunctions.foreach(_(this)) + ldut.harnessFunctions.foreach(_(this)) def success = io.success def harnessReset = this.reset.asBool diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 22f64925..2b9473ed 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -17,6 +17,7 @@ class AbstractConfig extends Config( new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index e8aeeb29..47d567fb 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -7,6 +7,7 @@ class TraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.groundtest.GroundTestBaseConfig) @@ -15,6 +16,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.groundtest.GroundTestBaseConfig) @@ -23,6 +25,7 @@ class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ @@ -32,6 +35,7 @@ class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ @@ -41,6 +45,7 @@ class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index 56e6362b..8872ed5e 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -31,6 +31,7 @@ class TutorialStarterConfig extends Config( new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM new chipyard.config.WithUART ++ // Add a UART + new chipyard.config.WithNoSubsystemDrivenClocks ++ // Don't drive the subsystem clocks from within the subsystem // CUSTOMIZE THE CORE // Uncomment out one (or multiple) of the lines below, and choose @@ -65,6 +66,7 @@ class TutorialMMIOConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ // Attach either a TileLink or AXI4 version of GCD // Uncomment one of the below lines @@ -92,6 +94,7 @@ class TutorialSha3Config extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo // new sha3.WithSha3Accel ++ @@ -117,6 +120,7 @@ class TutorialSha3BlackBoxConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ // Uncomment these lines once SHA3 is integrated // new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl From 56e1aeb4007b2b2d252c2296fd2095ecf11320ec Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 7 Jul 2020 17:18:10 -0700 Subject: [PATCH 062/457] Support FireSim diplomatic multiclock --- .../chipyard/src/main/scala/ChipTop.scala | 23 +-- .../chipyard/src/main/scala/Clocks.scala | 86 +++++++--- .../src/main/scala/ConfigFragments.scala | 18 +-- .../chipyard/src/main/scala/IOBinders.scala | 51 +++--- .../chipyard/src/main/scala/Subsystem.scala | 54 ++----- .../chipyard/src/main/scala/TestHarness.scala | 21 ++- .../src/main/scala/config/RocketConfigs.scala | 8 + .../src/main/scala/BridgeBinders.scala | 2 +- .../firechip/src/main/scala/FireSim.scala | 147 ++++++++++++++---- .../src/main/scala/FireSimMulticlockPOC.scala | 107 ------------- .../src/main/scala/TargetConfigs.scala | 12 +- .../src/test/scala/ScalaTestSuite.scala | 4 +- 12 files changed, 273 insertions(+), 260 deletions(-) delete mode 100644 generators/firechip/src/main/scala/FireSimMulticlockPOC.scala diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 0227feb8..ff3e2aed 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -9,12 +9,11 @@ import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGr import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike} import freechips.rocketchip.util.{ResetCatchAndSync} -import chipyard.config.ConfigValName._ import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple} import barstools.iocell.chisel._ -case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => LazyModule(new DigitalTop()(p))) +case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p)) /** @@ -31,23 +30,15 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction] // The system module specified by BuildSystem - val lSystem = p(BuildSystem)(p).suggestName("system") + val lSystem = LazyModule(p(BuildSystem)(p)).suggestName("system") // The systemClockSinkNode provides the implicit clock and reset for the System - private val systemClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) + val systemClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) + val systemClockGroup = LazyModule(new ClockGroup("system_clock")) + systemClockSinkNode := systemClockGroup.node - // clockGroupNode provides a single node which aggregates all clock groups in the design - val clockGroupNode = ClockGroupIdentityNode() - - // If the specified system has diplomatic clocks, connect it to our clockGroupNode - if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { - lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode :*= clockGroupNode } - } - // Connect the system implicit clock node to the clockGroupNode - systemClockSinkNode := ClockGroup() := clockGroupNode - - // Drive the entire diplomatic clock network using this configured Key - clockGroupNode :*=* p(ChipyardClockKey)(this) + // Generate Clocks and Reset + p(ChipyardClockKey)(this) // NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children // of ChipTop (ex: ClockGroup) do not receive clock or reset. diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index b9508d96..9c71ed96 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -5,19 +5,13 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci._ -import freechips.rocketchip.subsystem.{BaseSubsystem} +import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody} -import freechips.rocketchip.util.{ResetCatchAndSync} -import chipyard.config.ConfigValName._ +import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody, LazyModule} +import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} import barstools.iocell.chisel._ -import ChipyardClockDrivers._ - -case object ChipyardClockKey extends Field[ClockInstantiationFn](simpleTestHarnessClock) - - /** * Chipyard provides three baseline, top-level reset schemes, set using the * [[GlobalResetSchemeKey]] in a Parameters instance. These are: @@ -75,7 +69,7 @@ object GenerateReset { } reset_io.suggestName("reset") chiptop.iocells ++= resetIOCell - chiptop.harnessFunctions += ((th: TestHarness) => { + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { reset_io := th.dutReset Nil }) @@ -83,33 +77,89 @@ object GenerateReset { } } -object ChipyardClockDrivers { - type ClockInstantiationFn = ChipTop => OutwardNodeHandle[ClockGroupSourceParameters, ClockGroupSinkParameters, ClockGroupEdgeParameters, ClockGroupBundle] +case object ChipyardClockKey extends Field[ChipTop => Unit](ClockDrivers.harnessClock) + + + +object ClockDrivers { // A simple clock provider, for testing. All clocks in system are aggregated into one, // and are driven by directly punching out to the TestHarness clock - val simpleTestHarnessClock: ClockInstantiationFn = { chiptop => + val harnessClock: ChipTop => Unit = { chiptop => implicit val p = chiptop.p val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + val clockAggregator = LazyModule(new ClockGroupAggregator("clocks")) + + // Aggregate all 3 possible clock groups with the clockAggregator + chiptop.systemClockGroup.node := clockAggregator.node + if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { + chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := clockAggregator.node } + } + chiptop.lSystem match { + case l: ChipyardSubsystem => l.tileClockGroupNode := clockAggregator.node + case _ => + } + + + clockAggregator.node := simpleClockGroupSourceNode InModuleBody { // this needs directionality so generateIOFromSignal works val clock_wire = Wire(Input(Clock())) val reset_wire = GenerateReset(chiptop, clock_wire) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) chiptop.iocells ++= clockIOCell - clock_io.suggestName("clock") simpleClockGroupSourceNode.out.unzip._1.flatMap(_.member).map { o => o.clock := clock_wire o.reset := reset_wire } - - chiptop.harnessFunctions += ((th: TestHarness) => { - clock_io := th.clock + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + clock_io := th.harnessClock Nil }) } - ClockGroupAggregator() := simpleClockGroupSourceNode + } + + val harnessMultiClock: ChipTop => Unit = { chiptop => + implicit val p = chiptop.p + val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters(), ClockGroupSourceParameters())) + val uncoreClockAggregator = LazyModule(new ClockGroupAggregator("uncore_clocks")) + + // Aggregate only the uncoreclocks + chiptop.systemClockGroup.node := uncoreClockAggregator.node + if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { + chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := uncoreClockAggregator.node } + } + + uncoreClockAggregator.node := simpleClockGroupSourceNode + chiptop.lSystem match { + case l: ChipyardSubsystem => l.tileClockGroupNode := simpleClockGroupSourceNode + case _ => throw new Exception("MultiClock assumes ChipyardSystem") + } + + InModuleBody { + // this needs directionality so generateIOFromSignal works + val clock_wire = Wire(Input(Clock())) + val reset_wire = GenerateReset(chiptop, clock_wire) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) + chiptop.iocells ++= clockIOCell + clock_io.suggestName("clock") + val div_clock = Pow2ClockDivider(clock_wire, 2) + + simpleClockGroupSourceNode.out(0)._1.member.map { o => + o.clock := div_clock + o.reset := ResetCatchAndSync(div_clock, reset_wire.asBool) + } + simpleClockGroupSourceNode.out(1)._1.member.map { o => + o.clock := clock_wire + o.reset := reset_wire + } + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + clock_io := th.harnessClock + Nil + }) + } + } } diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index ac70f8e5..60ccc999 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -25,15 +25,8 @@ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import chipyard.{BuildTop, BuildSystem} +import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey} -/** - * TODO: Why do we need this? - */ -object ConfigValName { - implicit val valName = ValName("TestHarness") -} -import ConfigValName._ // ----------------------- // Common Config Fragments @@ -73,7 +66,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { }) class WithTracegenSystem extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => LazyModule(new TraceGenSystem()(p)) + case BuildSystem => (p: Parameters) => new TraceGenSystem()(p) }) /** @@ -103,7 +96,8 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { case MultiRoCCKey => { up(MultiRoCCKey, site) ++ harts.distinct.map{ i => (i -> Seq((p: Parameters) => { - LazyModule(new Hwacha()(p)).suggestName("hwacha") + val hwacha = LazyModule(new Hwacha()(p)) + hwacha })) } } @@ -150,3 +144,7 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { case SubsystemDriveAsyncClockGroupsKey => None }) + +class WithTileMultiClock extends Config((site, here, up) => { + case ChipyardClockKey => ClockDrivers.harnessMultiClock +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 3f986757..84ef5269 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -41,7 +41,7 @@ import scala.reflect.{ClassTag} // DOC include start: IOBinders // This type describes a function callable on the TestHarness instance. Its return type is unused. -type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any] +type TestHarnessFunction = (chipyard.HasHarnessUtils) => Seq[Any] // IOBinders will return a Seq of this tuple, which contains three fields: // 1. A Seq containing all IO ports created by the IOBinder function // 2. A Seq containing all IO cell modules created by the IOBinder function @@ -228,7 +228,7 @@ object AddIOCells { class WithGPIOTiedOff extends OverrideIOBinder({ (system: HasPeripheryGPIOModuleImp) => { val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) - val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } + val harnessFn = (th: HasHarnessUtils) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) } }) @@ -237,7 +237,7 @@ class WithGPIOTiedOff extends OverrideIOBinder({ class WithUARTAdapter extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { val (ports, ioCells2d) = AddIOCells.uart(system.uart) - val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil } + val harnessFn = (th: HasHarnessUtils) => { UARTAdapter.connect(ports)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) } }) @@ -245,7 +245,7 @@ class WithUARTAdapter extends OverrideIOBinder({ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ (system: HasPeripherySPIFlashModuleImp) => { val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") - val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil } + val harnessFn = (th: HasHarnessUtils) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) } }) @@ -253,8 +253,9 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ class WithSimBlockDevice extends OverrideIOBinder({ (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) - val harnessFn = (th: chipyard.TestHarness) => { - SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p) + val harnessFn = (th: HasHarnessUtils) => { + // TODO: Using harness clock/reset will be incorrect when systemClock =/= harnessClock + SimBlockDevice.connect(th.harnessClock, th.harnessReset.asBool, Some(port))(system.p) Nil } Seq((Seq(port), ios, Some(harnessFn))) @@ -264,7 +265,7 @@ class WithSimBlockDevice extends OverrideIOBinder({ class WithBlockDeviceModel extends OverrideIOBinder({ (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { BlockDeviceModel.connect(Some(port))(system.p) Nil } @@ -287,7 +288,7 @@ class WithSimAXIMem extends OverrideIOBinder({ val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") // TODO: we are inlining the connectMem method of SimAXIMem because // it takes in a dut rather than seq of axi4 ports - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { peiTuples.map { case (port, edge, ios) => val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) Module(mem.module).suggestName("mem") @@ -304,14 +305,15 @@ class WithBlackBoxSimMem extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort) => { implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { peiTuples.map { case (port, edge, ios) => val memSize = p(ExtMem).get.master.size val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) mem.io.axi <> port - mem.io.clock := th.clock - mem.io.reset := th.reset + // TODO: Using harness clock/reset will be incorrect when systemClock =/= harnessClock + mem.io.clock := th.harnessClock + mem.io.reset := th.harnessReset } Nil } @@ -323,7 +325,7 @@ class WithSimAXIMMIO extends OverrideIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem") - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)) Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") @@ -343,7 +345,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ (system: HasExtInterruptsModuleImp) => { val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) port.suggestName("interrupts") - val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil } + val harnessFn = (th: HasHarnessUtils) => { port := 0.U; Nil } Seq((Seq(port), ioCells, Some(harnessFn))) } }) @@ -351,7 +353,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ class WithTieOffL2FBusAXI extends OverrideIOBinder({ (system: CanHaveSlaveAXI4Port) => { val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus") - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => port := DontCare // tieoff doesn't completely tie-off, for some reason port.tieoff() @@ -366,13 +368,14 @@ class WithTiedOffDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) // tieoffDebug doesn't actually tie everything off :/ debugPortOpt.foreach { d => - d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.clock }) + // TODO: Using harness clock/reset will be incorrect when systemClock =/= harnessClock + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.harnessClock }) d.dmactiveAck := DontCare - d.clock := th.clock + d.clock := th.harnessClock } Nil } @@ -384,11 +387,11 @@ class WithSimDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { val dtm_success = Wire(Bool()) - Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p) + Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.harnessClock, th.harnessReset.asBool, dtm_success)(system.p) when (dtm_success) { th.success := true.B } - th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B) + th.dutReset := th.harnessReset.asBool | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B) Nil } Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) @@ -398,7 +401,7 @@ class WithSimDebug extends OverrideIOBinder({ class WithTiedOffSerial extends OverrideIOBinder({ (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) - val harnessFn = (th: chipyard.TestHarness) => { + val harnessFn = (th: HasHarnessUtils) => { SerialAdapter.tieoff(port) Nil } @@ -409,8 +412,8 @@ class WithTiedOffSerial extends OverrideIOBinder({ class WithSimSerial extends OverrideIOBinder({ (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) - val harnessFn = (th: chipyard.TestHarness) => { - val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset) + val harnessFn = (th: HasHarnessUtils) => { + val ser_success = SerialAdapter.connectSimSerial(port, th.harnessClock, th.harnessReset) when (ser_success) { th.success := true.B } Nil } @@ -422,7 +425,7 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ (system: TraceGenSystemModuleImp) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") - val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } + val harnessFn = (th: HasHarnessUtils) => { when (successPort) { th.success := true.B }; Nil } Seq((Seq(successPort), ioCells, Some(harnessFn))) } }) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 50714cc4..65ceddc9 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -11,7 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.prci._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} @@ -25,59 +25,24 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile} -import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey} - - -trait CanHaveHTIF { this: BaseSubsystem => - // Advertise HTIF if system can communicate with fesvr - if (this match { - case _: CanHavePeripherySerial if p(SerialKey) => true - case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true - case _ => false - }) { - ResourceBinding { - val htif = new Device { - def describe(resources: ResourceBindings): Description = { - val compat = resources("compat").map(_.value) - Description("htif", Map( - "compatible" -> compat)) - } - } - Resource(htif, "compat").bind(ResourceString("ucb,htif0")) - } - } -} - - -// Controls whether tiles are driven by implicit subsystem clock, or by -// diplomatic clock graph -case object UseDiplomaticTileClocks extends Field[Boolean](false) +import testchipip.{DromajoHelper} class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem with HasTiles - with CanHaveHTIF { def coreMonitorBundles = tiles.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle }.toList - // TODO: In the future, RC tiles may extend ClockDomain. When that happens, - // we won't need to manually create this clock node and connect it to the - // tiles' implicit clocks - - val tilesClockSinkNode = if (p(UseDiplomaticTileClocks)) { - val node = ClockSinkNode(List(ClockSinkParameters())) - node := ClockGroup()(p, ValName("chipyard_tiles")) := asyncClockGroupsNode - Some(node) - } else { - None - } + val tileClockSinkNode = ClockSinkNode(List(ClockSinkParameters())) + val tileClockGroup = LazyModule(new ClockGroup("tile_clock")) + val tileClockGroupNode = tileClockGroup.node + tileClockSinkNode := tileClockGroupNode override lazy val module = new ChipyardSubsystemModuleImp(this) } - class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) with HasResetVectorWire with HasTilesModuleImp @@ -87,10 +52,9 @@ class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends Bas wire.hartid := outer.hartIdList(i).U wire.reset_vector := global_reset_vector - outer.tilesClockSinkNode.map( n => { - outer.tiles(i).module.clock := n.in.head._1.clock - outer.tiles(i).module.reset := n.in.head._1.reset - }) + + outer.tiles(i).module.clock := outer.tileClockSinkNode.in.head._1.clock + outer.tiles(i).module.reset := outer.tileClockSinkNode.in.head._1.reset } // create file with core params diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 9344cadf..92b1dd29 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -5,34 +5,41 @@ import chisel3._ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import chipyard.iobinders.{TestHarnessFunction} -import chipyard.config.ConfigValName._ // ------------------------------- // Chipyard Test Harness // ------------------------------- -case object BuildTop extends Field[Parameters => LazyModule with HasTestHarnessFunctions]((p: Parameters) => LazyModule(new ChipTop()(p))) +case object BuildTop extends Field[Parameters => LazyModule with HasTestHarnessFunctions]((p: Parameters) => new ChipTop()(p)) trait HasTestHarnessFunctions { val harnessFunctions: Seq[TestHarnessFunction] } -class TestHarness(implicit val p: Parameters) extends Module { +trait HasHarnessUtils { + val harnessClock: Clock + val harnessReset: Reset + val dutReset: Reset + val success: Bool +} + +class TestHarness(implicit val p: Parameters) extends Module with HasHarnessUtils { val io = IO(new Bundle { val success = Output(Bool()) }) - val ldut = p(BuildTop)(p) + val ldut = LazyModule(p(BuildTop)(p)).suggestName("ChipTop") val dut = Module(ldut.module) io.success := false.B + val harnessClock = clock + val harnessReset = WireInit(reset) + val success = io.success + // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) ldut.harnessFunctions.foreach(_(this)) - def success = io.success - def harnessReset = this.reset.asBool - } diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 8e6e4867..af0b06b7 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -183,3 +183,11 @@ class MMIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) + +// NOTE: This config doesn't work yet because SimWidgets in the TestHarness +// always get the TestHarness clock. The Tiles and Uncore receive the correct clocks +class MultiClockRocketConfig extends Config( + new chipyard.config.WithTileMultiClock ++ // Put the Tile on its own clock domain + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index eba57451..b59d477d 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -58,7 +58,7 @@ class WithBlockDeviceBridge extends OverrideIOBinder({ class WithFASEDBridge extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort) => { implicit val p: Parameters = GetSystemParameters(system) - (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) => + (system.mem_axi4 zip system.memAXI4Node.edges.in).foreach({ case (axi4, edge) => val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, axi4.ar.bits.addr.getWidth, axi4.ar.bits.id.getWidth) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index a4cea5ec..d35dd7b6 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -3,13 +3,17 @@ package firesim.firesim import chisel3._ +import chisel3.experimental.{IO} +import freechips.rocketchip.prci._ +import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.diplomacy.{LazyModule, InModuleBody} +import freechips.rocketchip.util.{ResetCatchAndSync} -import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge} +import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} -import chipyard.{BuildSystem} +import chipyard.{BuildSystem, BuildTop, HasHarnessUtils, ChipyardSubsystem, ChipyardClockKey, ChipTop} import chipyard.iobinders.{IOBinders} // Determines the number of times to instantiate the DUT in the harness. @@ -20,6 +24,16 @@ class WithNumNodes(n: Int) extends Config((pname, site, here) => { case NumNodes => n }) +// Note, the main prerequisite for supporting an additional clock domain in a +// FireSim simulation is to supply an additional clock parameter +// (RationalClock) to the clock bridge (RationalClockBridge). The bridge +// produces a vector of clocks, based on the provided parameter list, which you +// may use freely without further modifications to your target design. +case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) { + def numClocks(): Int = additionalClocks.size + 1 +} +case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq())) + // Hacky: Set before each node is generated. Ideally we'd give IO binders // accesses to the the Harness's parameters instance. We could then alter that. object NodeIdx { @@ -28,33 +42,108 @@ object NodeIdx { def apply(): Int = idx } -class FireSim(implicit val p: Parameters) extends RawModule { - freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) - val clockBridge = Module(new RationalClockBridge) - val clock = clockBridge.io.clocks.head - val reset = WireInit(false.B) - withClockAndReset(clock, reset) { - // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes)) { - // It's not a RC bump without some hacks... - // Copy the AsyncClockGroupsKey to generate a fresh node on each - // instantiation of the dut, otherwise the initial instance will be - // reused across each node - import freechips.rocketchip.subsystem.AsyncClockGroupsKey - val lazyModule = p(BuildSystem)(p.alterPartial({ - case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy - })) - (lazyModule, Module(lazyModule.module)) - } +class WithFireSimSimpleClocks extends Config((site, here, up) => { + case ChipyardClockKey => { chiptop: ChipTop => + implicit val p = chiptop.p + val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + val clockAggregator = LazyModule(new ClockGroupAggregator("clocks")) - val peekPokeBridge = PeekPokeBridge(clock, reset) - // A Seq of partial functions that will instantiate the right bridge only - // if that Mixin trait is present in the target's LazyModule class instance - // - // Apply each partial function to each DUT instance - for ((lazyModule, module) <- targets) { - p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module)) - NodeIdx.increment() + // Aggregate all 3 possible clock groups with the clockAggregator + chiptop.systemClockGroup.node := clockAggregator.node + if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { + chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := clockAggregator.node } + } + chiptop.lSystem match { case l: ChipyardSubsystem => l.tileClockGroupNode := clockAggregator.node } + + clockAggregator.node := simpleClockGroupSourceNode + InModuleBody { + val clock = IO(Input(Clock())).suggestName("clock") + val reset = IO(Input(Reset())).suggestName("reset") + + simpleClockGroupSourceNode.out.unzip._1.flatMap(_.member).map { o => + o.clock := clock + o.reset := reset + } + + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + clock := th.harnessClock + reset := th.harnessReset + Nil + }) } } +}) + +class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) + case ChipyardClockKey => { chiptop: ChipTop => + implicit val p = chiptop.p + val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters(), ClockGroupSourceParameters())) + val uncoreClockAggregator = LazyModule(new ClockGroupAggregator("uncore_clocks")) + + // Aggregate only the uncoreclocks + chiptop.systemClockGroup.node := uncoreClockAggregator.node + if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { + chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := uncoreClockAggregator.node } + } + + uncoreClockAggregator.node := simpleClockGroupSourceNode + chiptop.lSystem match { + case l: ChipyardSubsystem => l.tileClockGroupNode := simpleClockGroupSourceNode + case _ => throw new Exception("MultiClock assumes ChipyardSystem") + } + + InModuleBody { + val uncore_clock = IO(Input(Clock())).suggestName("uncore_clock") + val tile_clock = IO(Input(Clock())).suggestName("tile_clock") + val reset = IO(Input(Reset())).suggestName("reset") + + simpleClockGroupSourceNode.out(0)._1.member.map { o => + o.clock := uncore_clock + o.reset := reset + } + + simpleClockGroupSourceNode.out(1)._1.member.map { o => + o.clock := tile_clock + o.reset := ResetCatchAndSync(tile_clock, reset.asBool) + } + + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + uncore_clock := th.harnessClock + reset := th.harnessReset + th match { + case f: FireSim => tile_clock := f.additionalClocks(0) + case _ => throw new Exception("FireSimMultiClock must be used with FireSim") + } + Nil + }) + } + } +}) + +class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessUtils { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) + val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) + val harnessClock = clockBridge.io.clocks.head // This is the reference clock + val additionalClocks = clockBridge.io.clocks.tail + val harnessReset = WireInit(false.B) + val peekPokeBridge = PeekPokeBridge(harnessClock, harnessReset) + val dutReset = false.B // unused (if used, its a bug) + val success = false.B // unused (if used, its a bug) + + // Instantiate multiple instances of the DUT to implement supernode + for (i <- 0 until p(NumNodes)) { + // It's not a RC bump without some hacks... + // Copy the AsyncClockGroupsKey to generate a fresh node on each + // instantiation of the dut, otherwise the initial instance will be + // reused across each node + import freechips.rocketchip.subsystem.AsyncClockGroupsKey + val lazyModule = LazyModule(p(BuildTop)(p.alterPartial({ + case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy + }))) + val module = Module(lazyModule.module) + require(lazyModule.harnessFunctions.size == 1, "There should only be 1 harness function to connect clock+reset") + lazyModule.harnessFunctions.foreach(_(this)) + NodeIdx.increment() + } } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala deleted file mode 100644 index bf0e0e26..00000000 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ /dev/null @@ -1,107 +0,0 @@ -//See LICENSE for license details. - -package firesim.firesim - -import chisel3._ - -import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossing} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.util.{ResetCatchAndSync} - -import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} -import firesim.configs._ - -import boom.common.{WithRationalBoomTiles} - -import chipyard.{BuildSystem, DigitalTop, DigitalTopModule} -import chipyard.config.ConfigValName._ -import chipyard.iobinders.{IOBinders} - -// WIP! This file is a sketch of one means of defining a multiclock target-design -// that can be simulated in FireSim, pending a canonicalized form in Chipyard. -// -// Note, the main prerequisite for supporting an additional clock domain in a -// FireSim simulation is to supply an additional clock parameter -// (RationalClock) to the clock bridge (RationalClockBridge). The bridge -// produces a vector of clocks, based on the provided parameter list, which you -// may use freely without further modifications to your target design. - -case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) { - def numClocks(): Int = additionalClocks.size + 1 -} -case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq())) - -trait HasAdditionalClocks extends LazyModuleImp { - val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock()))) -} - -// Presupposes only 1 or 2 clocks. -trait HasFireSimClockingImp extends HasAdditionalClocks { - val outer: HasTiles - val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { - case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) - case None => (clocks.head, reset) - } - - outer.tiles.foreach({ case tile => - tile.module.clock := tileClock - tile.module.reset := tileReset - }) -} - -// Config Fragment -class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config( - new WithRationalRocketTiles ++ - new WithRationalBoomTiles ++ - new Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) - }) -) - -class HalfRateUncore extends WithSingleRationalTileDomain(2,1) - -class WithFiresimMulticlockTop extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => LazyModule(new FiresimMulticlockTop()(p)).suggestName("system") -}) - -// Complete Config -class FireSimQuadRocketMulticlockConfig extends Config( - new HalfRateUncore ++ - new WithFiresimMulticlockTop ++ - new FireSimQuadRocketConfig) - -// Top Definition -class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop -{ - override lazy val module = new FiresimMulticlockTopModule(this) -} - - -class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp - -// Harness Definition -class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { - freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) - val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) - val refClock = clockBridge.io.clocks.head - val reset = WireInit(false.B) - withClockAndReset(refClock, reset) { - // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes)) { - val lazyModule = p(BuildSystem)(p) - (lazyModule, Module(lazyModule.module)) - } - val peekPokeBridge = PeekPokeBridge(refClock, reset) - // A Seq of partial functions that will instantiate the right bridge only - // if that Mixin trait is present in the target's class instance - // - // Apply each partial function to each DUT instance - for ((lazyModule, module) <- targets) { - p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module)) - } - targets.collect({ case (_, t: HasAdditionalClocks) => t.clocks := clockBridge.io.clocks }) - } -} - - diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 2828580a..d9ba92ec 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -22,7 +22,6 @@ import testchipip.WithRingSystemBus import firesim.bridges._ import firesim.configs._ -import chipyard.config.ConfigValName._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -67,6 +66,8 @@ class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small") // Tweaks that are generally applied to all firesim configs class WithFireSimConfigTweaks extends Config( + // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset + new WithFireSimSimpleClocks ++ // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source new WithBootROM ++ // Optional*: Removing this will require target-software changes to properly capture UART output @@ -170,3 +171,12 @@ class FireSimArianeConfig extends Config( new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ new chipyard.ArianeConfig) + + +class FireSimMulticlockRocketConfig extends Config( + new WithFireSimRationalTileDomain(2, 1) ++ + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.MultiClockRocketConfig) + diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index f92a7960..ea1627b7 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -106,8 +106,8 @@ class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimL class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") // Multiclock tests class RocketMulticlockF1Tests extends FireSimTestSuite( - "FireSimMulticlockPOC", - "FireSimQuadRocketMulticlockConfig", + "FireSim", + "FireSimMulticlockRocketConfig", "WithSynthAsserts_BaseF1Config") class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") From b55e579c91386f86bcd945412e6d4ac6ba301edc Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Tue, 7 Jul 2020 23:00:14 -0700 Subject: [PATCH 063/457] Override default baud rate for FireChip This avoids target software needing to explicitly set the divisor to match the UART bridge. --- generators/chipyard/src/main/scala/ConfigFragments.scala | 6 +++--- generators/firechip/src/main/scala/TargetConfigs.scala | 7 ++++--- generators/sifive-blocks | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index da048ff1..dde0e6d8 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -51,9 +51,9 @@ class WithGPIO extends Config((site, here, up) => { }) // DOC include end: gpio config fragment -class WithUART extends Config((site, here, up) => { +class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { case PeripheryUARTKey => Seq( - UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) + UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) }) class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { @@ -143,4 +143,4 @@ class WithHwachaTest extends Config((site, here, up) => { suiteHelper.addSuite(hwachaBmarks) "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha" } -}) \ No newline at end of file +}) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 2828580a..8aef9f8c 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -69,7 +69,8 @@ class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small") class WithFireSimConfigTweaks extends Config( // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source new WithBootROM ++ - // Optional*: Removing this will require target-software changes to properly capture UART output + // Optional*: Removing this will require adjusting the UART baud rate and + // potential target-software changes to properly capture UART output new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ // Required: Existing FAME-1 transform cannot handle black-box clock gates new WithoutClockGating ++ @@ -85,8 +86,8 @@ class WithFireSimConfigTweaks extends Config( new testchipip.WithTSI ++ // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ - // Required*: - new chipyard.config.WithUART + // Required*: Scale default baud rate with periphery bus frequency + new chipyard.config.WithUART(BigInt(3686400L)) ) /******************************************************************************* diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c1dee823..c240e629 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c1dee8234c23c8fc454108e59ecba20987f95cde +Subproject commit c240e629e2fc111cbb12e4fe707be898b5204984 From 763ba42b4c35915d1824b662fe73976697b0662b Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Wed, 8 Jul 2020 12:36:09 -0700 Subject: [PATCH 064/457] Bump testchipip for FDT alignment and minLatency fixes --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 29eb87c9..8b5c89a5 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 29eb87c938a2106249b85e3b3dffd00046f5077c +Subproject commit 8b5c89a5f7120e64a7ac5ce5210165426a58f3de From 85069387c9ccce5b12d86215b3fce10fe6679ea1 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 8 Jul 2020 14:45:12 -0700 Subject: [PATCH 065/457] Base Scratchpad --- build.sbt | 6 +++++- generators/riscv-sodor | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 5d642c1d..750878ab 100644 --- a/build.sbt +++ b/build.sbt @@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla) + gemmini, icenet, tracegen, ariane, nvdla, sodor) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -158,6 +158,10 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) +lazy val sodor = (project in file("generators/riscv-sodor")) + .dependsOn(rocketchip) + .settings(commonSettings) + lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) .settings(commonSettings) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 73af1b70..607f346f 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 73af1b7099764350c6dab6c5960334abcb7bdf07 +Subproject commit 607f346ff2e92977dcadda6cbd5b85589edcfbea From 9ad9d00a232ec38dc19269b61df2a5e0151dad8a Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 8 Jul 2020 16:02:31 -0700 Subject: [PATCH 066/457] Second revision --- docs/Customization/Custom-Core.rst | 66 ++++++++++++------- .../src/main/scala/example/TutorialTile.scala | 22 ++++++- 2 files changed, 62 insertions(+), 26 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 94d47505..9a2249ba 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -121,7 +121,8 @@ You will also need a ``CanAttachTile`` class to add the tile config into the con .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala :language: scala - :lines: 61-67 + :start-after: DOC include start: CanAttachTile + :end-before: DOC include end: CanAttachTile .. note:: @@ -137,14 +138,17 @@ Create Tile Class In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. -See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core. +See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core, +which specifies the constraints on the core's parameters and the connections with other diplomatic nodes. This class +usually contains Diplomacy/TileLink code only, and Chisel RTL code should not go here. All tile classes implement ``BaseTile`` and will normally implement ``SinksExternalInterrupts`` and ``SourcesExternalNotifications``, which allow the tile to accept external interrupt. A typical tile has the following form: .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala :language: scala - :lines: 87-125, 143 + :start-after: DOC include start: Tile class + :end-before: DOC include end: Tile class Connect TileLink Buses ---------------------- @@ -156,7 +160,8 @@ Rocket chip: .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala :language: scala - :lines: 133-142 + :start-after: DOC include start: AXI4 convert + :end-before: DOC include end: AXI4 convert Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also @@ -170,7 +175,8 @@ as the template, but it is not recommended unless you are familiar with TileLink .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala :language: scala - :lines: 126-132 + :start-after: DOC include start: AXI4 node + :end-before: DOC include end: AXI4 node where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile. Make sure to read :ref:`node_types` to check out what type of nodes Chipyard supports and their parameters! @@ -185,12 +191,36 @@ can override the following two functions to control how to buffer the bus reques You can find more information on ``TLBuffer`` in :ref:`diplomatic_widgets`. +Create Implementation Class +--------------------------- + +The implementation class contains the parameterized, actual hardware that depends on the values resolved by the Diplomacy +framework according to the info provided in the Tile class. This class will normally contains Chisel RTL codes, and if your +core is in Verilog, you will need to put the black box class you created in the first step here and connect it with the buses +and other components. No Diplomacy/TileLink code should be in this class; you should only connect the IO signals in TileLink +interfaces or other diplomatically defined components, which are located in the tile class. + +The implementation class for your core is of the following form: + +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :start-after: DOC include start: Implementation class + :end-before: DOC include end: Implementation class + +If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this: + +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :start-after: DOC include start: AXI4 connect + :end-before: DOC include end: AXI4 connect + Connect Interrupt ----------------- Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and -call ``decodeCoreInterrupts`` with the object as the argument. You can then read the interrupt bits from the object. +call ``decodeCoreInterrupts`` with the object as the argument. Note that you should call this function in the implementation +class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the object. The definition of ``TileInterrupts`` is .. code-block:: scala @@ -204,7 +234,6 @@ The definition of ``TileInterrupts`` is val lip = Vec(coreParams.nLocalInterrupts, Bool()) // Local interrupts } -This function should be in the implementation class since it involves hardware generation. Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications`` from the implementation class: @@ -215,21 +244,6 @@ from the implementation class: reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed -Create Implementation Class ---------------------------- - -The implementation class for your core is of the following form: - -.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala - :language: scala - :lines: 145-149, 160 - -If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this: - -.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala - :language: scala - :lines: 151-159 - Create Config Fragments to Integrate the Core --------------------------------------------- @@ -238,7 +252,8 @@ the current config. An example of such config will be like this: .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala :language: scala - :lines: 162-179 + :start-after: DOC include start: Config fragment + :end-before: DOC include end: Config fragment Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``. This config fragment simply appends new tile parameters to the end of this list. @@ -247,5 +262,6 @@ Now you have finished all the steps to prepare your cores for Chipyard! To gener in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`. You can now run any desired workflow for the new config just as you do for the built-in cores. -If you would like to see how an actual core are integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala`` -provides a concrete example of integrating a third party Verilog core Ariane. +If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala`` +provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI +interface with the memory coherency system. \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 12173184..41f79892 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -58,6 +58,7 @@ case class MyCoreParams( val retireWidth: Int = 2 } +// DOC include start: CanAttachTile case class MyTileAttachParams( tileParams: MyTileParams, crossingParams: RocketCrossingParams @@ -65,6 +66,7 @@ case class MyTileAttachParams( type TileType = MyTile val lookup = PriorityMuxHartIdFromSeq(Seq(tileParams)) } +// DOC include end: CanAttachTile case class MyTileParams( name: Option[String] = Some("my_tile"), @@ -84,6 +86,7 @@ case class MyTileParams( } } +// DOC include start: Tile class class MyTile( val myParams: MyTileParams, crossing: ClockCrossingType, @@ -123,6 +126,10 @@ class MyTile( } // (Connection to bus, interrupt, etc.) +// } + // DOC include end: Tile class + + // DOC include start: AXI4 node // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. val idBits = 4 val memAXI4Node = AXI4MasterNode( @@ -131,6 +138,9 @@ class MyTile( name = "myPortName", id = IdRange(0, 1 << idBits)))))) val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node + // DOC include end: AXI4 node + + // DOC include start: AXI4 convert (tlMasterXbar.node // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar := memoryTap := TLBuffer() @@ -140,14 +150,20 @@ class MyTile( := AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed := AXI4Fragmenter() // deal with multi-beat xacts := memAXI4Node) // The custom node, see below + // DOC include end: AXI4 convert + } +// DOC include start: Implementation class class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ // annotate the parameters Annotated.params(this, outer.myParams) - // TODO: Create the top module of the core and connect it with the ports in "outer" + // TODO: Create the top module of the core and connect it with the ports in "outer" } +//} + // DOC include end: Implementation class + // DOC include start: AXI4 connect outer.memAXI4Node.out foreach { case (out, edgeOut) => // Connect your module IO port to "out" // The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala @@ -157,8 +173,11 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ // (choose one depends on the type of AHB node you create) // If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala } + // DOC include end: AXI4 connect + } +// DOC include start: Config fragment class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { // Calculate the next available hart ID (since hart ID cannot be duplicated) @@ -177,3 +196,4 @@ class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Con // The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits. case XLen => 64 }) +// DOC include end: Config fragment From 11c87777fe7ce8dba0854d2bcc65321f8e0d27a7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 9 Jul 2020 11:29:58 -0700 Subject: [PATCH 067/457] Remove BOOM debug print --- generators/chipyard/src/main/scala/config/BoomConfigs.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 1f41c252..8b7cd31e 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -19,7 +19,6 @@ class LargeBoomConfig extends Config( new chipyard.config.AbstractConfig) class MegaBoomConfig extends Config( - new boom.common.WithBoomBranchPrintf ++ new boom.common.WithNMegaBooms(1) ++ // mega boom config new chipyard.config.AbstractConfig) @@ -43,4 +42,3 @@ class DromajoBoomConfig extends Config( new chipyard.config.WithTraceIO ++ // enable the traceio new boom.common.WithNSmallBooms(1) ++ new chipyard.config.AbstractConfig) - From 8124ce3df1483b5a1321f60005bf86c0c296cec4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 9 Jul 2020 12:38:21 -0700 Subject: [PATCH 068/457] Add FIRRTL_LOGLEVEL variable --- variables.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/variables.mk b/variables.mk index 48da498e..e6de6ca0 100644 --- a/variables.mk +++ b/variables.mk @@ -152,6 +152,8 @@ define run_scala_main endef endif +FIRRTL_LOGLEVEL ?= error + ######################################################################################### # output directory for tests ######################################################################################### From 2196a621c67d1cc598116ddfd498719c57d4f17a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 9 Jul 2020 12:39:17 -0700 Subject: [PATCH 069/457] Pass FIRRTL_LOGLEVEL to GenerateTopAndHarness --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 62e4399e..71f4440c 100644 --- a/common.mk +++ b/common.mk @@ -104,7 +104,7 @@ $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp @echo "" > /dev/null firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) - $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes) + $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir) -ll $(FIRRTL_LOGLEVEL)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes) # DOC include end: FirrtlCompiler # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs From ced7ea634cc2eae5a8045a20ce81c177f347c0b3 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 12 Jul 2020 01:08:13 -0700 Subject: [PATCH 070/457] 3rd Revision --- docs/Customization/Custom-Core.rst | 41 +++++++++++-------- .../src/main/scala/example/TutorialTile.scala | 4 +- 2 files changed, 25 insertions(+), 20 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 9a2249ba..d6a19f04 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -3,8 +3,8 @@ Adding a custom core ==================== -You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides a step-to-step -instruction on how to achieve this. +You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides step-by-step +instructions on how to achieve this. .. note:: @@ -24,18 +24,18 @@ Chipyard will generate a core for every ``InstantiableTileParams`` object it dis This object is derived from``TileParams``, a trait containing the information needed to create a tile. All cores must have their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``. -``TileParams`` holds the parameters for the tile, which are the same for every generated core, while ``CoreParams`` -contains the parameters for individual cores. They must be implemented as case classes with fields that can be overridden by +``TileParams`` holds the parameters for the tile, which include parameters for all components in the tile (e.g. +core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile. +They must be implemented as case classes with fields that can be overridden by other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. -``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``. +``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``, +where ``TileType`` is the tile class (see the next section). All custom cores will also need to implement ``instantiate()`` in their tile parameter class to return a new instance of the tile class ``TileType``. -``TileParams``, ``InstantiableTileParams[TileType]`` and ``CoreParams`` contains the following fields (you may ignore -any fields marked "Rocket specific" and use their default values, although it is recommended to use them if you -need a custom field with similar purposes): +``TileParams``, ``InstantiableTileParams[TileType]`` and ``CoreParams`` contains the following fields: .. code-block:: scala @@ -113,9 +113,11 @@ need a custom field with similar purposes): dfmaLatency: Int = 4 // Rocket specific: Fused multiply-add pipeline latency (double precision) ) -Most of the fields here are originally designed for the Rocket core and thus contain some implementation-specific details, but -many of them are general enough to be useful for other cores. It is strongly recommended to use these fields instead -of creating your own custom fields when applicable. +Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some +implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore +any fields marked "Rocket specific" and use their default values; however, if you need to store additional information +with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of +creating your own custom fields. You will also need a ``CanAttachTile`` class to add the tile config into the config system, with the following format: @@ -124,6 +126,9 @@ You will also need a ``CanAttachTile`` class to add the tile config into the con :start-after: DOC include start: CanAttachTile :end-before: DOC include end: CanAttachTile +During elaboration, Chipyard will look for subclasses of ``CanAttachTile`` in the config system and instantiate a tile +from the parameters in this class for every such class it found. + .. note:: Implementations may choose to ignore some fields here or use them in a non-standard way, but using an inaccurate @@ -153,8 +158,8 @@ which allow the tile to accept external interrupt. A typical tile has the follow Connect TileLink Buses ---------------------- -Chipyard use TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters -between the core's memory protocol and TileLink in the Tile module. +Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters +between the core's memory protocol and TileLink within the Tile module. in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by Rocket chip: @@ -195,8 +200,8 @@ Create Implementation Class --------------------------- The implementation class contains the parameterized, actual hardware that depends on the values resolved by the Diplomacy -framework according to the info provided in the Tile class. This class will normally contains Chisel RTL codes, and if your -core is in Verilog, you will need to put the black box class you created in the first step here and connect it with the buses +framework according to the info provided in the Tile class. This class will normally contains Chisel RTL code. If your +core is in Verilog, you will need to instantiate the black box class that wraps your Verilog implementation and connect it with the buses and other components. No Diplomacy/TileLink code should be in this class; you should only connect the IO signals in TileLink interfaces or other diplomatically defined components, which are located in the tile class. @@ -247,7 +252,7 @@ from the implementation class: Create Config Fragments to Integrate the Core --------------------------------------------- -To use your core in a Chipyard config, you would need a config fragment that would create a ``TileParams`` object of your core in +To use your core in a Chipyard config, you will need a config fragment that will create a ``TileParams`` object of your core in the current config. An example of such config will be like this: .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -260,8 +265,8 @@ This config fragment simply appends new tile parameters to the end of this list. Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`. -You can now run any desired workflow for the new config just as you do for the built-in cores. +You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports). If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala`` provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI -interface with the memory coherency system. \ No newline at end of file +interface with the memory coherency system. diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 41f79892..75ff1e5b 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -125,7 +125,7 @@ class MyTile( Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) } - // (Connection to bus, interrupt, etc.) + // TODO: Create TileLink nodes and connections here. // } // DOC include end: Tile class @@ -159,7 +159,7 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ // annotate the parameters Annotated.params(this, outer.myParams) - // TODO: Create the top module of the core and connect it with the ports in "outer" } + // TODO: Create the top module of the core and connect it with the ports in "outer" //} // DOC include end: Implementation class From 14399e88b3fb7c048244c93d53c6600129f5c500 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 12 Jul 2020 01:23:34 -0700 Subject: [PATCH 071/457] Minor change --- docs/Customization/Custom-Core.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index d6a19f04..16d19f27 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -225,7 +225,7 @@ Connect Interrupt Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and call ``decodeCoreInterrupts`` with the object as the argument. Note that you should call this function in the implementation -class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the object. +class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the resulting object. The definition of ``TileInterrupts`` is .. code-block:: scala From 1933fd8cbe21d697fafeebebabe50c775e65c55a Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Tue, 14 Jul 2020 12:10:12 -0700 Subject: [PATCH 072/457] Update sodor package structure --- .../src/main/scala/config/SodorConfigs.scala | 20 +++++++++++++++++++ generators/riscv-sodor | 2 +- 2 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 generators/chipyard/src/main/scala/config/SodorConfigs.scala diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala new file mode 100644 index 00000000..dfcfebe7 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -0,0 +1,20 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} + +class SodorConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new sodor.common.WithNSodorCores(1) ++ // single Ariane core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 607f346f..5e6a775d 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 607f346ff2e92977dcadda6cbd5b85589edcfbea +Subproject commit 5e6a775ded0c19719f61acbae11874478bc9a8b5 From 7ea464dc906eb629db1df7deb67ca9641ce01298 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Tue, 14 Jul 2020 12:49:36 -0700 Subject: [PATCH 073/457] 4th revision --- docs/Customization/Custom-Core.rst | 26 ++++++++++++++----- .../src/main/scala/example/TutorialTile.scala | 25 ++++++++++++++++++ 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 16d19f27..4a7f57f1 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -224,9 +224,9 @@ Connect Interrupt Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and -call ``decodeCoreInterrupts`` with the object as the argument. Note that you should call this function in the implementation -class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the resulting object. -The definition of ``TileInterrupts`` is +call ``decodeCoreInterrupts()`` with the object as the argument. Note that you should call this function in the implementation +class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the ``TileInterrupts`` bundle +we create above. The definition of ``TileInterrupts`` is .. code-block:: scala @@ -239,15 +239,29 @@ The definition of ``TileInterrupts`` is val lip = Vec(coreParams.nLocalInterrupts, Bool()) // Local interrupts } +Here is an example on how to connect these signals in the implementation class: + +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :start-after: DOC include start: connect interrupt + :end-before: DOC include end: connect interrupt + Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications`` from the implementation class: .. code-block:: scala def reportHalt(could_halt: Option[Bool]) // Triggered when there is an unrecoverable hardware error (halt the machine) - def reportHalt(errors: Seq[CanHaveErrors]) // Varient for standard error bundle (used only by cache when there's an ECC error) - reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) - reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed + def reportHalt(errors: Seq[CanHaveErrors]) // Varient for standard error bundle (Rocket specific: used only by cache when there's an ECC error) + def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) + def reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed + +Here is an example on how to use these functions to raise interrupt. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala + :language: scala + :start-after: DOC include start: raise interrupt + :end-before: DOC include end: raise interrupt Create Config Fragments to Integrate the Core --------------------------------------------- diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 75ff1e5b..c8f71b85 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -163,6 +163,31 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ //} // DOC include end: Implementation class + // DOC include start: connect interrupt + // For example, our core support debug interrupt and machine-level interrupt, and suppose the following two signals + // are the interrupt inputs to the core. (DO NOT COPY this code - if your core treat each type of interrupt differently, + // you need to connect them to different interrupt ports of your core) + val debug_i = Wire(Bool()) + val mtip_i = Wire(Bool()) + // We create a bundle here and decode the interrupt. + val int_bundle = new TileInterrupts() + outer.decodeCoreInterrupts(int_bundle) + debug_i := int_bundle.debug + mtip_i := int_bundle.meip & int_bundle.msip & int_bundle.mtip + // DOC include end: connect interrupt + + // DOC include start: raise interrupt + // This is a demo. You should call these function according to your core + // Suppose that the following signal is from the decoder indicating a WFI instruction is received. + val wfi_o = Wire(Bool()) + outer.reportWFI(Some(wfi_o)) + // Suppose that the following signal indicate an unreconverable hardware error. + val halt_o = Wire(Bool()) + outer.reportHalt(Some(halt_o)) + // Suppose that our core never stall for a long time / stop retiring. Use None to indicate that this interrupt never fires. + outer.reportCease(None) + // DOC include end: raise interrupt + // DOC include start: AXI4 connect outer.memAXI4Node.out foreach { case (out, edgeOut) => // Connect your module IO port to "out" From 9fbc0a5bea7fe7f1b20a46389b18c9e71ee78f4e Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 15 Jul 2020 11:08:36 -0700 Subject: [PATCH 074/457] Add links --- docs/Customization/Custom-Core.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 4a7f57f1..3d6a6393 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -39,6 +39,7 @@ of the tile class ``TileType``. .. code-block:: scala + // The two classes below can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala. trait TileParams { val core: CoreParams // Core parameters (see below) val icache: Option[ICacheParams] // Rocket specific: I1 cache option @@ -55,6 +56,7 @@ of the tile class ``TileType``. (implicit p: Parameters): TileType } + // This class can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Core.scala. trait CoreParams { val bootFreqHz: BigInt // Frequency val useVM: Boolean // Support virtual memory @@ -105,6 +107,7 @@ of the tile class ``TileType``. def vMemDataBits: Int = 0 } + // This class can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/FPU.scala. case class FPUParams( minFLen: Int = 32, // Minimum floating point length (no need to change) fLen: Int = 64, // Maximum floating point length, use 32 if only single precision is supported @@ -191,6 +194,9 @@ can override the following two functions to control how to buffer the bus reques .. code-block:: scala + // This two functions can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala, + // in the class "BaseTile". + // By default, their value is "TLBuffer(BufferParams.none)". protected def makeMasterBoundaryBuffers(implicit p: Parameters): TLBuffer protected def makeSlaveBoundaryBuffers(implicit p: Parameters): TLBuffer @@ -230,6 +236,7 @@ we create above. The definition of ``TileInterrupts`` is .. code-block:: scala + // This class can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala. class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val debug = Bool() // debug interrupt val mtip = Bool() // Machine level timer interrupt @@ -251,6 +258,8 @@ from the implementation class: .. code-block:: scala + // These functions can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala, + // in the trait "SourcesExternalNotifications". def reportHalt(could_halt: Option[Bool]) // Triggered when there is an unrecoverable hardware error (halt the machine) def reportHalt(errors: Seq[CanHaveErrors]) // Varient for standard error bundle (Rocket specific: used only by cache when there's an ECC error) def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) From 7bb1a48b1a5eacfc942d6b3f461823ecb8fd17c8 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 16 Jul 2020 14:12:29 -0700 Subject: [PATCH 075/457] Connect TileLink nodes --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 5e6a775d..fbb9a9df 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 5e6a775ded0c19719f61acbae11874478bc9a8b5 +Subproject commit fbb9a9df0fb33f9228616902c1cf53083a73e6b6 From fddf2181471a1d227f75c592e394ec0bc39cc6c7 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 16 Jul 2020 15:39:07 -0700 Subject: [PATCH 076/457] 5th revision --- .../src/main/scala/example/TutorialTile.scala | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index c8f71b85..1f58e5e4 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -126,7 +126,6 @@ class MyTile( } // TODO: Create TileLink nodes and connections here. -// } // DOC include end: Tile class // DOC include start: AXI4 node @@ -160,7 +159,20 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ Annotated.params(this, outer.myParams) // TODO: Create the top module of the core and connect it with the ports in "outer" -//} + + // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like + // val core = Module(new MyCoreBlackbox(params...)) + // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial + // (link on the top of the page) for more info. + // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala + // for a Verilog example. + + // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module + // and connect appropriate signal. You can even implement this class as your top module. + // See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and + // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for + // Chisel example. + // DOC include end: Implementation class // DOC include start: connect interrupt From ae1e44a9e360f51abb925958fab0686f36eb8d8b Mon Sep 17 00:00:00 2001 From: banahogg Date: Sat, 18 Jul 2020 17:44:52 -0700 Subject: [PATCH 077/457] Update BOOM URL in README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 285d337b..ab542cf3 100644 --- a/README.md +++ b/README.md @@ -78,7 +78,7 @@ These additional publications cover many of the internal components used in Chip [berkeley]: https://berkeley.edu [riscv]: https://riscv.org/ [rocket-chip]: https://github.com/freechipsproject/rocket-chip -[boom]: https://github.com/ucb-bar/riscv-boom +[boom]: https://github.com/riscv-boom/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ [ariane]: https://github.com/pulp-platform/ariane/ [gemmini]: https://github.com/ucb-bar/gemmini From 2c7e7f3199d497668a20d8a635dfb2aeca27b81d Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 19 Jul 2020 21:36:50 -0700 Subject: [PATCH 078/457] Fixed file links --- docs/Customization/Custom-Core.rst | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 3d6a6393..fa14fff6 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -35,11 +35,14 @@ where ``TileType`` is the tile class (see the next section). All custom cores will also need to implement ``instantiate()`` in their tile parameter class to return a new instance of the tile class ``TileType``. -``TileParams``, ``InstantiableTileParams[TileType]`` and ``CoreParams`` contains the following fields: +``TileParams`` (in the file `BaseTile.scala `_) , +``InstantiableTileParams`` (in the file `BaseTile.scala `_), +``CoreParams`` (in the file `Core.scala `_), +and ``FPUParams`` (in the file `FPU.scala `_) +contains the following fields: .. code-block:: scala - // The two classes below can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala. trait TileParams { val core: CoreParams // Core parameters (see below) val icache: Option[ICacheParams] // Rocket specific: I1 cache option @@ -56,7 +59,6 @@ of the tile class ``TileType``. (implicit p: Parameters): TileType } - // This class can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Core.scala. trait CoreParams { val bootFreqHz: BigInt // Frequency val useVM: Boolean // Support virtual memory @@ -106,8 +108,7 @@ of the tile class ``TileType``. def eLen(xLen: Int, fLen: Int): Int = xLen max fLen def vMemDataBits: Int = 0 } - - // This class can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/FPU.scala. + case class FPUParams( minFLen: Int = 32, // Minimum floating point length (no need to change) fLen: Int = 64, // Maximum floating point length, use 32 if only single precision is supported @@ -191,11 +192,11 @@ Make sure to read :ref:`node_types` to check out what type of nodes Chipyard sup Also, by default, there are boundary buffers for both master and slave connections to the bus when they are leaving the tile, and you can override the following two functions to control how to buffer the bus requests/responses: +(You can find the definition of these two functions in the class ``BaseTile`` in the file +`BaseTile.scala `_) .. code-block:: scala - // This two functions can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala, - // in the class "BaseTile". // By default, their value is "TLBuffer(BufferParams.none)". protected def makeMasterBoundaryBuffers(implicit p: Parameters): TLBuffer protected def makeSlaveBoundaryBuffers(implicit p: Parameters): TLBuffer @@ -232,11 +233,11 @@ Chipyard allows a tile to either receive interrupts from other devices or initia In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and call ``decodeCoreInterrupts()`` with the object as the argument. Note that you should call this function in the implementation class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the ``TileInterrupts`` bundle -we create above. The definition of ``TileInterrupts`` is +we create above. The definition of ``TileInterrupts`` +(in the file `Interrupts.scala `_) is .. code-block:: scala - // This class can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala. class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val debug = Bool() // debug interrupt val mtip = Bool() // Machine level timer interrupt @@ -255,11 +256,11 @@ Here is an example on how to connect these signals in the implementation class: Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications`` from the implementation class: +(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file +`Interrupts.scala `_) .. code-block:: scala - // These functions can be found in https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala, - // in the trait "SourcesExternalNotifications". def reportHalt(could_halt: Option[Bool]) // Triggered when there is an unrecoverable hardware error (halt the machine) def reportHalt(errors: Seq[CanHaveErrors]) // Varient for standard error bundle (Rocket specific: used only by cache when there's an ECC error) def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating) From 0a39819f442ce54d3b280870eab0d3e398235f6c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 19 Jul 2020 21:46:32 -0700 Subject: [PATCH 079/457] Add source file note --- docs/Customization/Custom-Core.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index fa14fff6..4f529efc 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -10,6 +10,11 @@ instructions on how to achieve this. RoCC is currently not supported by cores other than Rocket and BOOM. Please use Rocket or BOOM as the RoCC base core if you need to use RoCC. +.. note:: + + This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately + from Chipyard. If you find any discrepency between the code on this page and the code in the source file, please report it through + GitHub issues! Wrap Verilog Module with Blackbox (Optional) -------------------------------------------- From 692b120b65ab72f6e3f1a7885efed74057b08747 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 19 Jul 2020 21:48:07 -0700 Subject: [PATCH 080/457] Fixed typo --- docs/Customization/Custom-Core.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index 4f529efc..a76741ec 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -13,7 +13,7 @@ instructions on how to achieve this. .. note:: This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately - from Chipyard. If you find any discrepency between the code on this page and the code in the source file, please report it through + from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through GitHub issues! Wrap Verilog Module with Blackbox (Optional) From b719919934b3e9663edb5753d97ca5639641b9c6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Jul 2020 18:30:05 -0700 Subject: [PATCH 081/457] Add RANDOM_SEED variable to set random init for VCS and Verilator simulations --- common.mk | 10 +++++----- generators/tracegen/tracegen.mk | 2 +- sims/vcs/Makefile | 6 ++---- sims/verilator/Makefile | 9 ++++++++- vcs.mk | 8 ++++++++ 5 files changed, 24 insertions(+), 11 deletions(-) diff --git a/common.mk b/common.mk index 71f4440c..9d322f00 100644 --- a/common.mk +++ b/common.mk @@ -141,19 +141,19 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### run-binary-fast: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -167,10 +167,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% $(output_d ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/generators/tracegen/tracegen.mk b/generators/tracegen/tracegen.mk index fc4bd246..fec62288 100644 --- a/generators/tracegen/tracegen.mk +++ b/generators/tracegen/tracegen.mk @@ -9,7 +9,7 @@ $(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh cd $(AXE_DIR) && ./make.sh $(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) $(base_dir)/scripts/check-tracegen.sh $< > $@ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index df2dbbe6..14ebae59 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -47,13 +47,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(E # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - -debug_pp + rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG \ - -debug_pp + +define+DEBUG ######################################################################################### # create a vcs vpd rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 667c856c..3d676efd 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -30,6 +30,13 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug WAVEFORM_FLAG=-v$(sim_out_name).vcd +# If verilator seed unspecified, verilator uses srand as random seed +ifdef RANDOM_SEED +SEED_FLAG=+verilator+seed+I$(RANDOM_SEED) +else +SEED_FLAG= +endif + .PHONY: default debug default: $(sim) debug: $(sim_debug) @@ -145,7 +152,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/vcs.mk b/vcs.mk index 96cd0636..93e75c19 100644 --- a/vcs.mk +++ b/vcs.mk @@ -1,5 +1,13 @@ WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +# If ntb_random_seed unspecified, vcs uses 1 as constant seed. +# Set ntb_random_seed_automatic to actually get a random seed +ifdef RANDOM_SEED +SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) +else +SEED_FLAG=+ntb_random_seed_automatic +endif + CLOCK_PERIOD ?= 1.0 RESET_DELAY ?= 777.7 From df07790a5adb8e5c2f98bfc678a4d8203b902067 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 17 Jul 2020 12:22:22 -0400 Subject: [PATCH 082/457] Bump FireMarshal/QEMU/riscv-isa-sim for OpenSBI --- software/firemarshal | 2 +- toolchains/qemu | 2 +- toolchains/riscv-tools/riscv-isa-sim | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/software/firemarshal b/software/firemarshal index 6c6a08f9..83b86610 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 6c6a08f9790c660823e9f858ca87f93b2502fa44 +Subproject commit 83b866104c6860b5d03989a6cf8439aa6934b398 diff --git a/toolchains/qemu b/toolchains/qemu index 4f591025..fdd76fec 160000 --- a/toolchains/qemu +++ b/toolchains/qemu @@ -1 +1 @@ -Subproject commit 4f59102571fce49af180cfc6d4cdd2b5df7bdb14 +Subproject commit fdd76fecdde1ad444ff4deb7f1c4f7e4a1ef97d6 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 9443c1db..8d860c19 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 9443c1dbac0301faf3a47c5e6914cc7dcb34983e +Subproject commit 8d860c190640e19e0f23a21d2479b4a36d13d342 From d56df6252c7d3f5ebe5eb630cf84e156b573d8b9 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 23 Jul 2020 19:24:44 -0700 Subject: [PATCH 083/457] Sync --- .../src/main/scala/config/SodorConfigs.scala | 30 +++++++++++-------- generators/riscv-sodor | 2 +- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index dfcfebe7..1e1b7e51 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -5,16 +5,20 @@ import chisel3._ import freechips.rocketchip.config.{Config} class SodorConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new sodor.common.WithNSodorCores(1) ++ // single Ariane core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) \ No newline at end of file diff --git a/generators/riscv-sodor b/generators/riscv-sodor index fbb9a9df..f78d07e3 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit fbb9a9df0fb33f9228616902c1cf53083a73e6b6 +Subproject commit f78d07e387fcb90ae324bfdc5881b7f88e509248 From 14e2a9dbd1be267698f6eb0996a753de2e4f8921 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 24 Jul 2020 14:17:29 -0700 Subject: [PATCH 084/457] Fixed tile_master --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index f78d07e3..c3423720 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit f78d07e387fcb90ae324bfdc5881b7f88e509248 +Subproject commit c34237201ec83c24f33b4b5dbc02bd7f1368dfcd From 6131ab58e5b826598b4fb0b082e033c6235cacb8 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Tue, 28 Jul 2020 13:37:07 -0700 Subject: [PATCH 085/457] Connect cores --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index c3423720..e9b9aa4e 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit c34237201ec83c24f33b4b5dbc02bd7f1368dfcd +Subproject commit e9b9aa4e0150aba1326644318243619c4899c9ae From 98ef89cbde8cd166fe39cfe96f55d45edd58006f Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 29 Jul 2020 15:02:33 -0700 Subject: [PATCH 086/457] Created Internal Tiles --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index e9b9aa4e..a4d5c5c0 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit e9b9aa4e0150aba1326644318243619c4899c9ae +Subproject commit a4d5c5c0e582146ec09d018af466fe5def979f3b From 16d4186ea4e8d275a6bdd55dd0c1ea8f6e145597 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Fri, 31 Jul 2020 10:29:53 -0700 Subject: [PATCH 087/457] updated openroad hash --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 528e745c..cbc907df 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 528e745c54c3901a311aade7c928e866de1d42d2 +Subproject commit cbc907dfe8005a8d72f1b2fb7b414ad9dbfe14b1 From a2bd26b91cbef686d56460dab86861e7e32673c4 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 31 Jul 2020 20:54:42 -0700 Subject: [PATCH 088/457] Finished Sodor Design --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index a4d5c5c0..eed11e8a 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit a4d5c5c0e582146ec09d018af466fe5def979f3b +Subproject commit eed11e8ab242d9144c3c6eb60e3fdd65218ade31 From d7f3f91f18de038b69b9ba8cbd6a894437c543b0 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 30 Jul 2020 10:58:35 -0700 Subject: [PATCH 089/457] implement fast loadmem feature --- docs/Simulation/Software-RTL-Simulation.rst | 23 +++++++++++++++++++++ generators/testchipip | 2 +- sims/firesim | 2 +- variables.mk | 5 +++++ 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index bdafd60f..93e4dcc6 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -62,6 +62,12 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. +The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. + +.. code-block:: shell + + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -126,6 +132,23 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. +Fast Memory Loading +------------------- + +The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. + +.. code-block:: shell + + make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + +The ``.hex`` file should be a text file with a hexadecimal number on each line. + +.. code-block:: text + + deadbeef + 0123 + +Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. Generating Waveforms ----------------------- diff --git a/generators/testchipip b/generators/testchipip index 8b5c89a5..3366844f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8b5c89a5f7120e64a7ac5ce5210165426a58f3de +Subproject commit 3366844f50a7969f1997125c07ce8d00e5494cf0 diff --git a/sims/firesim b/sims/firesim index 8064d880..ec9d615f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8064d8808b9c936711361532a95affbfc2fcbdca +Subproject commit ec9d615f6db72684cfee16a2b57f50493b63ca1f diff --git a/variables.mk b/variables.mk index 48da498e..1aa129f3 100644 --- a/variables.mk +++ b/variables.mk @@ -163,7 +163,12 @@ output_dir=$(sim_dir)/output/$(long_name) PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= +LOADMEM ?= +LOADMEM_ADDR ?= 81000000 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) +ifneq ($(LOADMEM),) +override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +endif VERBOSE_FLAGS ?= +verbose sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) From 813d1fdb9e37391e9a6e9445bedcb7181be74e23 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 3 Aug 2020 16:09:16 -0700 Subject: [PATCH 090/457] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index ec9d615f..b13e7529 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ec9d615f6db72684cfee16a2b57f50493b63ca1f +Subproject commit b13e75296c44b1f3fa987d15df6a595668842dfe From 578ae6fca2f521982ab74f5045a972fe7dd0fccd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 3 Aug 2020 14:23:08 -0700 Subject: [PATCH 091/457] Bump to July 2020 rocketchip --- .circleci/do-rtl-build.sh | 2 +- generators/ariane | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/ChipTop.scala | 17 ++-- .../chipyard/src/main/scala/Clocks.scala | 77 +++++++++++-------- .../src/main/scala/ConfigFragments.scala | 10 +-- .../chipyard/src/main/scala/Subsystem.scala | 18 +---- .../chipyard/src/main/scala/System.scala | 5 +- .../chipyard/src/main/scala/TestHarness.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 11 ++- .../firechip/src/main/scala/FireSim.scala | 71 ++++++++++------- .../src/main/scala/TargetConfigs.scala | 14 ++-- generators/hwacha | 2 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/System.scala | 10 +-- generators/tracegen/src/main/scala/Tile.scala | 10 ++- tools/chisel3 | 2 +- tools/firrtl | 2 +- 19 files changed, 142 insertions(+), 119 deletions(-) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index a7c8ad50..3973026f 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -59,7 +59,7 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ make -C $REMOTE_SIM_DIR clean; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/generators/ariane b/generators/ariane index 0ed91074..3a2eed60 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 0ed9107485281545bf5abf2a042dface55e740bf +Subproject commit 3a2eed602faac24e58a530db429f23f11810aae9 diff --git a/generators/boom b/generators/boom index 859c6055..dc22cacf 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 859c60553b0cd2e84ee586ad6de25223baefb722 +Subproject commit dc22cacf71fe88b95f3393d622f53648bf0440bd diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index ff3e2aed..f7b94d2b 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -32,10 +32,8 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc // The system module specified by BuildSystem val lSystem = LazyModule(p(BuildSystem)(p)).suggestName("system") - // The systemClockSinkNode provides the implicit clock and reset for the System - val systemClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) - val systemClockGroup = LazyModule(new ClockGroup("system_clock")) - systemClockSinkNode := systemClockGroup.node + // The implicitClockSinkNode provides the implicit clock and reset for the System + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) // Generate Clocks and Reset p(ChipyardClockKey)(this) @@ -46,12 +44,13 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc // anyways, they probably need to be explicitly clocked. lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) { // These become the implicit clock and reset to the System - val system_clock = systemClockSinkNode.in.head._1.clock - val system_reset = systemClockSinkNode.in.head._1.reset + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + // The implicit clock and reset for the system is also, by convention, used for all the IOBinders // TODO: This may not be the right thing to do in all cases - withClockAndReset(system_clock, system_reset) { + withClockAndReset(implicit_clock, implicit_reset) { val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(lSystem.module)).unzip3 // We ignore _ports for now... iocells ++= _iocells.flatten @@ -60,8 +59,8 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc // Connect the implicit clock/reset, if present lSystem.module match { case l: LazyModuleImp => { - l.clock := system_clock - l.reset := system_reset + l.clock := implicit_clock + l.reset := implicit_reset }} } } diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 9c71ed96..7f181bb5 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -83,59 +83,65 @@ case object ChipyardClockKey extends Field[ChipTop => Unit](ClockDrivers.harness object ClockDrivers { - // A simple clock provider, for testing. All clocks in system are aggregated into one, - // and are driven by directly punching out to the TestHarness clock + // A simple clock provider, for testing val harnessClock: ChipTop => Unit = { chiptop => implicit val p = chiptop.p - val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - val clockAggregator = LazyModule(new ClockGroupAggregator("clocks")) - // Aggregate all 3 possible clock groups with the clockAggregator - chiptop.systemClockGroup.node := clockAggregator.node - if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { - chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := clockAggregator.node } - } - chiptop.lSystem match { - case l: ChipyardSubsystem => l.tileClockGroupNode := clockAggregator.node - case _ => + val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) + chiptop.implicitClockSinkNode := implicitClockSourceNode + + // Drive the diplomaticclock graph of the DigitalTop (if present) + val simpleClockGroupSourceNode = chiptop.lSystem match { + case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { + val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + l.asyncClockGroupsNode := n + Some(n) + } + case _ => None } - - clockAggregator.node := simpleClockGroupSourceNode InModuleBody { - // this needs directionality so generateIOFromSignal works + //this needs directionality so generateIOFromSignal works val clock_wire = Wire(Input(Clock())) val reset_wire = GenerateReset(chiptop, clock_wire) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) chiptop.iocells ++= clockIOCell clock_io.suggestName("clock") - simpleClockGroupSourceNode.out.unzip._1.flatMap(_.member).map { o => + implicitClockSourceNode.out.unzip._1.map { o => o.clock := clock_wire o.reset := reset_wire } + + simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => + out.member.data.foreach { o => + o.clock := clock_wire + o.reset := reset_wire + } + }} + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { clock_io := th.harnessClock Nil }) } + } - val harnessMultiClock: ChipTop => Unit = { chiptop => + + val harnessDividedClock: ChipTop => Unit = { chiptop => implicit val p = chiptop.p - val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters(), ClockGroupSourceParameters())) - val uncoreClockAggregator = LazyModule(new ClockGroupAggregator("uncore_clocks")) - // Aggregate only the uncoreclocks - chiptop.systemClockGroup.node := uncoreClockAggregator.node - if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { - chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := uncoreClockAggregator.node } - } + val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) + chiptop.implicitClockSinkNode := implicitClockSourceNode - uncoreClockAggregator.node := simpleClockGroupSourceNode - chiptop.lSystem match { - case l: ChipyardSubsystem => l.tileClockGroupNode := simpleClockGroupSourceNode - case _ => throw new Exception("MultiClock assumes ChipyardSystem") + val simpleClockGroupSourceNode = chiptop.lSystem match { + case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { + val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + l.asyncClockGroupsNode := n + Some(n) + } + case _ => throw new Exception("Harness multiclock assumes BaseSubsystem") } InModuleBody { @@ -147,14 +153,19 @@ object ClockDrivers { clock_io.suggestName("clock") val div_clock = Pow2ClockDivider(clock_wire, 2) - simpleClockGroupSourceNode.out(0)._1.member.map { o => + implicitClockSourceNode.out.unzip._1.map { o => o.clock := div_clock - o.reset := ResetCatchAndSync(div_clock, reset_wire.asBool) - } - simpleClockGroupSourceNode.out(1)._1.member.map { o => - o.clock := clock_wire o.reset := reset_wire } + + simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => + out.member.elements.map { case (name, data) => + // This is mega hacks, how are you actually supposed to do this? + data.clock := (if (name.contains("core")) clock_wire else div_clock) + data.reset := reset_wire + } + }} + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { clock_io := th.harnessClock Nil diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index dd17b0a1..704b849a 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -6,12 +6,13 @@ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Field, Parameters, Config} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{LazyModule, ValName} -import freechips.rocketchip.devices.tilelink.BootROMParams +import freechips.rocketchip.devices.tilelink.{BootROMLocated} import freechips.rocketchip.devices.debug.{Debug} import freechips.rocketchip.groundtest.{GroundTestSubsystem} import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} import freechips.rocketchip.util.{AsyncResetReg} +import freechips.rocketchip.prci._ import testchipip._ import tracegen.{TraceGenSystem} @@ -33,8 +34,7 @@ import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey, TestSuit // ----------------------- class WithBootROM extends Config((site, here, up) => { - case BootROMParams => BootROMParams( - contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") + case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")) }) // DOC include start: gpio config fragment @@ -159,6 +159,6 @@ class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { case SubsystemDriveAsyncClockGroupsKey => None }) -class WithTileMultiClock extends Config((site, here, up) => { - case ChipyardClockKey => ClockDrivers.harnessMultiClock +class WithTileDividedClock extends Config((site, here, up) => { + case ChipyardClockKey => ClockDrivers.harnessDividedClock }) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 65ceddc9..3184bcaa 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -35,32 +35,16 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem case b: BoomTile => b.module.core.coreMonitorBundle }.toList - val tileClockSinkNode = ClockSinkNode(List(ClockSinkParameters())) - val tileClockGroup = LazyModule(new ClockGroup("tile_clock")) - val tileClockGroupNode = tileClockGroup.node - tileClockSinkNode := tileClockGroupNode - override lazy val module = new ChipyardSubsystemModuleImp(this) } class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasResetVectorWire with HasTilesModuleImp { - for (i <- 0 until outer.tiles.size) { - val wire = tile_inputs(i) - wire.hartid := outer.hartIdList(i).U - wire.reset_vector := global_reset_vector - - - outer.tiles(i).module.clock := outer.tileClockSinkNode.in.head._1.clock - outer.tiles(i).module.reset := outer.tileClockSinkNode.in.head._1.reset - } - // create file with core params ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) // Generate C header with relevant information for Dromajo // This is included in the `dromajo_params.h` header file - DromajoHelper.addArtefacts() + DromajoHelper.addArtefacts(InSubsystem) } diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index b0ae8a44..bd20ddc7 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -26,8 +26,10 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port - with HasPeripheryBootROM { + + val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } + val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } override lazy val module = new ChipyardSystemModule(this) } @@ -37,5 +39,4 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) with HasRTCModuleImp with HasExtInterruptsModuleImp - with HasPeripheryBootROMModuleImp with DontTouch diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 92b1dd29..70802783 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -28,7 +28,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessUtil val success = Output(Bool()) }) - val ldut = LazyModule(p(BuildTop)(p)).suggestName("ChipTop") + val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") val dut = Module(ldut.module) io.success := false.B diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f7ce5a84..e0587454 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -187,8 +187,15 @@ class MMIORocketConfig extends Config( // NOTE: This config doesn't work yet because SimWidgets in the TestHarness // always get the TestHarness clock. The Tiles and Uncore receive the correct clocks -class MultiClockRocketConfig extends Config( - new chipyard.config.WithTileMultiClock ++ // Put the Tile on its own clock domain +class DividedClockRocketConfig extends Config( + new chipyard.config.WithTileDividedClock ++ // Put the Tile on its own clock domain new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) + + +class TestClockRocketConfig extends Config( + //new chipyard.config.WithTileMultiClock ++ // Put the Tile on its own clock domain + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(8, 3) ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index d35dd7b6..8f1de11d 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -45,26 +45,36 @@ object NodeIdx { class WithFireSimSimpleClocks extends Config((site, here, up) => { case ChipyardClockKey => { chiptop: ChipTop => implicit val p = chiptop.p - val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - val clockAggregator = LazyModule(new ClockGroupAggregator("clocks")) - // Aggregate all 3 possible clock groups with the clockAggregator - chiptop.systemClockGroup.node := clockAggregator.node - if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { - chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := clockAggregator.node } + val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) + chiptop.implicitClockSinkNode := implicitClockSourceNode + + // Drive the diplomaticclock graph of the DigitalTop (if present) + val simpleClockGroupSourceNode = chiptop.lSystem match { + case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { + val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + l.asyncClockGroupsNode := n + Some(n) + } + case _ => None } - chiptop.lSystem match { case l: ChipyardSubsystem => l.tileClockGroupNode := clockAggregator.node } - clockAggregator.node := simpleClockGroupSourceNode InModuleBody { - val clock = IO(Input(Clock())).suggestName("clock") - val reset = IO(Input(Reset())).suggestName("reset") + val clock = IO(Input(Clock())).suggestName("clock") + val reset = IO(Input(Reset())).suggestName("reset") - simpleClockGroupSourceNode.out.unzip._1.flatMap(_.member).map { o => + implicitClockSourceNode.out.unzip._1.map { o => o.clock := clock o.reset := reset } + simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => + out.member.data.foreach { o => + o.clock := clock + o.reset := reset + } + }} + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { clock := th.harnessClock reset := th.harnessReset @@ -78,19 +88,18 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) case ChipyardClockKey => { chiptop: ChipTop => implicit val p = chiptop.p - val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters(), ClockGroupSourceParameters())) - val uncoreClockAggregator = LazyModule(new ClockGroupAggregator("uncore_clocks")) - // Aggregate only the uncoreclocks - chiptop.systemClockGroup.node := uncoreClockAggregator.node - if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) { - chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := uncoreClockAggregator.node } - } + val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) + chiptop.implicitClockSinkNode := implicitClockSourceNode - uncoreClockAggregator.node := simpleClockGroupSourceNode - chiptop.lSystem match { - case l: ChipyardSubsystem => l.tileClockGroupNode := simpleClockGroupSourceNode - case _ => throw new Exception("MultiClock assumes ChipyardSystem") + // Drive the diplomaticclock graph of the DigitalTop (if present) + val simpleClockGroupSourceNode = chiptop.lSystem match { + case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { + val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + l.asyncClockGroupsNode := n + Some(n) + } + case _ => None } InModuleBody { @@ -98,15 +107,23 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi val tile_clock = IO(Input(Clock())).suggestName("tile_clock") val reset = IO(Input(Reset())).suggestName("reset") - simpleClockGroupSourceNode.out(0)._1.member.map { o => + implicitClockSourceNode.out.unzip._1.map { o => o.clock := uncore_clock o.reset := reset } - simpleClockGroupSourceNode.out(1)._1.member.map { o => - o.clock := tile_clock - o.reset := ResetCatchAndSync(tile_clock, reset.asBool) - } + simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => + out.member.elements.map { case (name, data) => + // This is mega hacks, how are you actually supposed to do this? + if (name.contains("core")) { + data.clock := tile_clock + data.reset := ResetCatchAndSync(tile_clock, reset.asBool) + } else { + data.clock := uncore_clock + data.clock := reset + } + } + }} chiptop.harnessFunctions += ((th: HasHarnessUtils) => { uncore_clock := th.harnessClock diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index c734ac8c..66a20bce 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -10,7 +10,7 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.tilelink.BootROMParams +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.LazyModule import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} @@ -24,16 +24,16 @@ import firesim.bridges._ import firesim.configs._ class WithBootROM extends Config((site, here, up) => { - case BootROMParams => { + case BootROMLocated(x) => { val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") - val bootROMPath = if (chipyardBootROM.exists()) { + val bootROMPath = if (chipyardBootROM.exists()) { chipyardBootROM.getAbsolutePath() } else { firesimBootROM.getAbsolutePath() } - BootROMParams(contentFileName = bootROMPath) + up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMPath)) } }) @@ -188,11 +188,13 @@ class FireSimArianeConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.ArianeConfig) - +//********************************************************************************** +//* Multiclock Configurations +//*********************************************************************************/ class FireSimMulticlockRocketConfig extends Config( new WithFireSimRationalTileDomain(2, 1) ++ new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ - new chipyard.MultiClockRocketConfig) + new chipyard.DividedClockRocketConfig) diff --git a/generators/hwacha b/generators/hwacha index a989b697..e29b65db 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit a989b69759137802b4c39e9ddebb90427455fb79 +Subproject commit e29b65db86e4486ebdfd4f39d1265df83a2d7d9d diff --git a/generators/rocket-chip b/generators/rocket-chip index 653efa99..6eb1a3de 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 653efa99a27dc155bd4b4706a7e71c5c930f62b1 +Subproject commit 6eb1a3de082e27c752d9e4c1ae971c693cc192eb diff --git a/generators/testchipip b/generators/testchipip index 8b5c89a5..3bfd710c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8b5c89a5f7120e64a7ac5ce5210165426a58f3de +Subproject commit 3bfd710ce36817038aae5d11848aec9a3c0c705f diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index ca3572d7..83f6a5e4 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -12,6 +12,10 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem with CanHaveMasterAXI4MemPort { def coreMonitorBundles = Nil + val tileStatusNodes = tiles.collect { + case t: GroundTestTile => t.statusNode.makeSink() + case t: BoomTraceGenTile => t.statusNode.makeSink() + } override lazy val module = new TraceGenSystemModuleImp(this) } @@ -20,12 +24,8 @@ class TraceGenSystemModuleImp(outer: TraceGenSystem) { val success = IO(Output(Bool())) - outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U } + val status = dontTouch(DebugCombiner(outer.tileStatusNodes.map(_.bundle))) - val status = dontTouch(DebugCombiner(outer.tiles.collect { - case t: GroundTestTile => t.module.status - case t: BoomTraceGenTile => t.module.status - })) success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR } diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 1ddf0d84..63d68e50 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -3,7 +3,7 @@ package tracegen import chisel3._ import chisel3.util._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType} +import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType, BundleBridgeSource} import freechips.rocketchip.groundtest._ import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.constants.{MemoryOpConstants} @@ -206,11 +206,13 @@ class BoomTraceGenTile private( val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil) val intOutwardNode: IntOutwardNode = IntIdentityNode() val slaveNode: TLInwardNode = TLIdentityNode() + val statusNode = BundleBridgeSource(() => new GroundTestStatus) val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false)))) - val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params)) + val dcache = LazyModule(new BoomNonBlockingDCache(staticIdForMetadataUseOnly)(boom_params)) + val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node @@ -220,11 +222,11 @@ class BoomTraceGenTile private( class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) extends BaseTileModuleImp(outer){ - val status = IO(new GroundTestStatus) + val status = outer.statusNode.bundle val halt_and_catch_fire = None val tracegen = Module(new TraceGenerator(outer.params.traceParams)) - tracegen.io.hartid := constants.hartid + tracegen.io.hartid := outer.hartIdSinkNode.bundle val ptw = Module(new DummyPTW(1)) val lsu = Module(new LSU()(outer.boom_params, outer.dcache.module.edge)) diff --git a/tools/chisel3 b/tools/chisel3 index 21ea734d..cc2971fe 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit 21ea734d809395962a8d3195a76377f6e44308f3 +Subproject commit cc2971feb15d4bc8cb4a8138b5a095ccbc92dcc3 diff --git a/tools/firrtl b/tools/firrtl index 7c6f58d9..c07da8a5 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 7c6f58d986e67b3d0662a4cd6654a68f9cc52cf9 +Subproject commit c07da8a581789b88f7e6ffc98c8e810565034ad9 From 93c7fef9424a25fc8157c1ad6d504cd5cca126df Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 5 Aug 2020 09:54:07 -0700 Subject: [PATCH 092/457] We need to uppercase hex chars for bc --- common.mk | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/common.mk b/common.mk index 9d322f00..6679457e 100644 --- a/common.mk +++ b/common.mk @@ -157,6 +157,30 @@ run-binary-debug: $(output_dir) $(sim_debug) run-fast: run-asm-tests-fast run-bmark-tests-fast +######################################################################################### +# helper rules to run simulator with fast loadmem via hex files +######################################################################################### +$(binary_hex): $(output_dir) $(BINARY) + hex_bytes=$(shell readelf --segments --wide $(BINARY) | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' ' | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/0000000008/ibase=16;/' | bc);\ + power_2_bytes=`python -c "import math; print int(pow(2,math.ceil(math.log($$hex_bytes)/math.log(2))))"`;\ + elf2hex 64 $$power_2_bytes $(BINARY) $(shell echo "ibase=16;$(LOADMEM_ADDR)" | bc) > $(binary_hex) + +run-binary-hex: $(output_dir) $(sim) $(binary_hex) +run-binary-hex: run-binary +run-binary-hex: override LOADMEM_ADDR = 80000000 +run-binary-hex: override LOADMEM = $(binary_hex) +run-binary-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +run-binary-debug-hex: $(output_dir) $(sim) $(binary_hex) +run-binary-debug-hex: run-binary-debug +run-binary-debug-hex: override LOADMEM_ADDR = 80000000 +run-binary-debug-hex: override LOADMEM = $(binary_hex) +run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +run-binary-fast-hex: $(output_dir) $(sim) $(binary_hex) +run-binary-fast-hex: run-binary-fast +run-binary-fast-hex: override LOADMEM_ADDR = 80000000 +run-binary-fast-hex: override LOADMEM = $(binary_hex) +run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) + ######################################################################################### # run assembly/benchmarks rules ######################################################################################### From 5bfc289677fcff16c19a71c6b79006a0c31b09c7 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 5 Aug 2020 09:55:31 -0700 Subject: [PATCH 093/457] Bump fesvr for better loadmem impl. Fix verilator loadmem support --- .../utilities/src/main/resources/csrc/emulator.cc | 10 ++-------- toolchains/esp-tools/riscv-isa-sim | 2 +- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 0a3b46da..27a8aa4a 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -116,7 +116,6 @@ int main(int argc, char** argv) FILE * vcdfile = NULL; uint64_t start = 0; #endif - char ** htif_argv = NULL; int verilog_plusargs_legal = 1; opterr = 1; @@ -252,10 +251,6 @@ done_processing: usage(argv[0]); return 1; } - int htif_argc = 1 + argc - optind; - htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); - htif_argv[0] = argv[0]; - for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -278,8 +273,8 @@ done_processing: #endif jtag = new remote_bitbang_t(rbb_port); - dtm = new dtm_t(htif_argc, htif_argv); - tsi = new tsi_t(htif_argc, htif_argv); + dtm = new dtm_t(argc, argv); + tsi = new tsi_t(argc, argv); signal(SIGTERM, handle_sigterm); @@ -364,6 +359,5 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) free(htif_argv); return ret; } diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 13384cac..2bc65d1b 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 13384cac1e54828200067ff890f564a505a4ebb3 +Subproject commit 2bc65d1bf6605077e3740941c086724beb35db05 From edbb86ef982c08859842c923b2d7c46ef5d011c3 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 5 Aug 2020 11:17:48 -0700 Subject: [PATCH 094/457] Move elf2hex preprocessing into separate script --- common.mk | 4 +--- scripts/smartelf2hex.sh | 14 ++++++++++++++ variables.mk | 1 + 3 files changed, 16 insertions(+), 3 deletions(-) create mode 100755 scripts/smartelf2hex.sh diff --git a/common.mk b/common.mk index 6679457e..43615a92 100644 --- a/common.mk +++ b/common.mk @@ -161,9 +161,7 @@ run-fast: run-asm-tests-fast run-bmark-tests-fast # helper rules to run simulator with fast loadmem via hex files ######################################################################################### $(binary_hex): $(output_dir) $(BINARY) - hex_bytes=$(shell readelf --segments --wide $(BINARY) | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' ' | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/0000000008/ibase=16;/' | bc);\ - power_2_bytes=`python -c "import math; print int(pow(2,math.ceil(math.log($$hex_bytes)/math.log(2))))"`;\ - elf2hex 64 $$power_2_bytes $(BINARY) $(shell echo "ibase=16;$(LOADMEM_ADDR)" | bc) > $(binary_hex) + $(base_dir)/scripts/smartelf2hex.sh $(BINARY) > $(binary_hex) run-binary-hex: $(output_dir) $(sim) $(binary_hex) run-binary-hex: run-binary diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh new file mode 100755 index 00000000..782977ff --- /dev/null +++ b/scripts/smartelf2hex.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash + +# This script find the appropriate arguments to pass to elf2hex by inspecting the given RISC-V elf binary +# First and only argument is the binary to be converted. +# The output of this script should be redirected to a file (as with normal elf2hex). + +binary=$1 +segments=`readelf --segments --wide $binary` +entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]` +entry_dec=`bc <<< "ibase=16;$entry_hex"` +length_hex=`echo "$segments" | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` +length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` +power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` +elf2hex 64 $power_2_length $binary $entry_dec diff --git a/variables.mk b/variables.mk index 61602507..d7eccb49 100644 --- a/variables.mk +++ b/variables.mk @@ -173,6 +173,7 @@ override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) endif VERBOSE_FLAGS ?= +verbose sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) +binary_hex= $(sim_out_name).loadmem_hex ######################################################################################### # build output directory for compilation From caab6fb968c866c24b31c3dc6f5c3c1a3a2a87b8 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 5 Aug 2020 11:27:14 -0700 Subject: [PATCH 095/457] Add run-binary-hex docs --- docs/Simulation/Software-RTL-Simulation.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 93e4dcc6..28ae223e 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -150,6 +150,12 @@ The ``.hex`` file should be a text file with a hexadecimal number on each line. Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. +A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available. + +.. code-block:: shell + + make run-binary-hex BINARY=test.riscv + Generating Waveforms ----------------------- From 8499b769410a4d7c16e387cb0a6c200c3bf6f5d3 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 5 Aug 2020 15:36:13 -0700 Subject: [PATCH 096/457] Bump esp-spike to master --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 2bc65d1b..a1ff6b03 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 2bc65d1bf6605077e3740941c086724beb35db05 +Subproject commit a1ff6b03f7f630a06327798238256973568e3837 From 7f5b324d0639a058ee86d8066c2df0b9bd997f8e Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 5 Aug 2020 17:16:36 -0700 Subject: [PATCH 097/457] Added interrupt --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index eed11e8a..6c682077 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit eed11e8ab242d9144c3c6eb60e3fdd65218ade31 +Subproject commit 6c682077c1c541d0e66a05631483b76b6ac2d926 From abc75e9b9551c209390ef67deb2586f4c03a61a0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 5 Aug 2020 15:00:28 -0700 Subject: [PATCH 098/457] Fix Reset bug --- .../chipyard/src/main/scala/Subsystem.scala | 25 +++++++++++++++++-- .../firechip/src/main/scala/FireSim.scala | 2 +- generators/tracegen/src/main/scala/Tile.scala | 2 +- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 3184bcaa..7f089ce1 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -11,7 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.prci._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} @@ -25,10 +25,31 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile} -import testchipip.{DromajoHelper} +import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey} + +trait CanHaveHTIF { this: BaseSubsystem => + // Advertise HTIF if system can communicate with fesvr + if (this match { + case _: CanHavePeripherySerial if p(SerialKey) => true + case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true + case _ => false + }) { + ResourceBinding { + val htif = new Device { + def describe(resources: ResourceBindings): Description = { + val compat = resources("compat").map(_.value) + Description("htif", Map( + "compatible" -> compat)) + } + } + Resource(htif, "compat").bind(ResourceString("ucb,htif0")) + } + } +} class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem with HasTiles + with CanHaveHTIF { def coreMonitorBundles = tiles.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 8f1de11d..e807e840 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -120,7 +120,7 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi data.reset := ResetCatchAndSync(tile_clock, reset.asBool) } else { data.clock := uncore_clock - data.clock := reset + data.reset := reset } } }} diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 63d68e50..5ff9af56 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -210,7 +210,7 @@ class BoomTraceGenTile private( val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, - core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false)))) + core=BoomCoreParams(nPMPs=0, numLdqEntries=16, numStqEntries=16, useVM=false)))) val dcache = LazyModule(new BoomNonBlockingDCache(staticIdForMetadataUseOnly)(boom_params)) From 751215dec1cbfda4e879d77a8b7d5f1c8082fe1c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 12 Aug 2020 14:26:49 -0700 Subject: [PATCH 099/457] 5-stage core running --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 6c682077..7e7f2d4d 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 6c682077c1c541d0e66a05631483b76b6ac2d926 +Subproject commit 7e7f2d4df1b870b7a877648462b5aa6da0c7e207 From 03e50178f1f74e6f88225f3960749225f2ed0011 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 14 Aug 2020 16:00:38 -0700 Subject: [PATCH 100/457] Add misalignment detection & make M-extension test optional --- generators/chipyard/src/main/scala/TestSuites.scala | 4 ++-- generators/riscv-sodor | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 9ca2c08c..8cdfd3c9 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -92,8 +92,8 @@ class TestSuiteHelper } if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (xlen == 64) ((if (vm) rv64i else rv64pi), (if (coreParams.mulDiv.isDefined) rv64u else List(rv64ui))) + else ((if (vm) rv32i else rv32pi), (if (coreParams.mulDiv.isDefined) rv32u else List(rv32ui))) addSuites(rvi.map(_("p"))) addSuites(rvu.map(_("p"))) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 7e7f2d4d..f6d5f45e 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 7e7f2d4df1b870b7a877648462b5aa6da0c7e207 +Subproject commit f6d5f45e31cd2f8c4aad64662d7ec0d59545f344 From 700f68730b0106a82103c4b88b913a369606df30 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 14 Aug 2020 17:52:36 -0700 Subject: [PATCH 101/457] Fix verilator makefile --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3d676efd..f093fa2d 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,7 +28,7 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -WAVEFORM_FLAG=-v$(sim_out_name).vcd +WAVEFORM_FLAG=-v $(sim_out_name).vcd # If verilator seed unspecified, verilator uses srand as random seed ifdef RANDOM_SEED From f6992c61c8bff041f78ca395f61de5048b80a15b Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sat, 15 Aug 2020 00:20:47 -0700 Subject: [PATCH 102/457] 5-stage CPU passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index f6d5f45e..cdc1dad8 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit f6d5f45e31cd2f8c4aad64662d7ec0d59545f344 +Subproject commit cdc1dad8b0ef2b08ab595a198d1455cbd05a55d3 From 97f595f41582fcc961274cd2222d68fc4802b24d Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 16 Aug 2020 15:41:44 -0700 Subject: [PATCH 103/457] 1-stage passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index cdc1dad8..af19aa2f 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit cdc1dad8b0ef2b08ab595a198d1455cbd05a55d3 +Subproject commit af19aa2fc56a5a2e883b2880608f0e35a5498c49 From 84359abd19c034e42d395b5132a1dbe56ab132a2 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 16 Aug 2020 16:07:38 -0700 Subject: [PATCH 104/457] Isolated master adapter's TileLink valid signals from the core --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index af19aa2f..989c9831 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit af19aa2fc56a5a2e883b2880608f0e35a5498c49 +Subproject commit 989c98313c147b0c91614228dfc8b1dfb78c5200 From 8867c3241c9f3ddeed483f7fa6f35ac44631f42f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 17 Aug 2020 17:07:29 -0700 Subject: [PATCH 105/457] Add .swo to .gitignore | Update docs --- .gitignore | 1 + docs/Simulation/Software-RTL-Simulation.rst | 49 +++++++-------------- 2 files changed, 18 insertions(+), 32 deletions(-) diff --git a/.gitignore b/.gitignore index 35d9b2d8..a85d0dd2 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,7 @@ target *.stamp *.vcd *.swp +*.swo *.log *# *~ diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 28ae223e..ca852d36 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -40,8 +40,7 @@ For a proprietry VCS simulation, enter the ``sims/vcs`` directory # Enter VCS directory cd sims/vcs - -.. _sim-default: +.. _sw-sim-help: Simulating The Default Example ------------------------------- @@ -62,12 +61,6 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. -The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. - -.. code-block:: shell - - make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple - Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -82,6 +75,22 @@ For example: .. _sw-sim-custom: +Makefile Variables and Commands +------------------------------- +You can get a list of useful Makefile variables and commands available from the Verilator or VCS directories. simply run ``make help``: + +.. code-block:: shell + + # Enter Verilator directory + cd sims/verilator + make help + + # Enter VCS directory + cd sims/vcs + make help + +.. _sim-default: + Simulating A Custom Project ------------------------------- @@ -132,29 +141,6 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. -Fast Memory Loading -------------------- - -The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. - -.. code-block:: shell - - make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 - -The ``.hex`` file should be a text file with a hexadecimal number on each line. - -.. code-block:: text - - deadbeef - 0123 - -Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. - -A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available. - -.. code-block:: shell - - make run-binary-hex BINARY=test.riscv Generating Waveforms ----------------------- @@ -166,4 +152,3 @@ An open-source vcd-capable waveform viewer is `GTKWave Date: Mon, 17 Aug 2020 17:15:05 -0700 Subject: [PATCH 106/457] Change eval. strategy --- .circleci/config.yml | 2 +- scripts/build-toolchains.sh | 22 +++++++++---------- scripts/build-util.sh | 2 +- .../init-submodules-no-riscv-tools-nolog.sh | 16 +++++++++----- 4 files changed, 22 insertions(+), 20 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index b6556850..88a20f24 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -6,7 +6,7 @@ version: 2.1 parameters: tools-cache-version: type: string - default: "v5" + default: "v6" # default execution env.s executors: diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 62a2f74b..2685872e 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -6,8 +6,8 @@ set -e set -o pipefail -RDIR=$(pwd) -CHIPYARD_DIR="${CHIPYARD_DIR:-$(git rev-parse --show-toplevel)}" +DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")" +CHIPYARD_DIR="$(dirname "$DIR")" usage() { echo "usage: ${0} [OPTIONS] [riscv-tools | esp-tools | ec2fast]" @@ -134,18 +134,16 @@ SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=ris git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src -cd "$RDIR" - # create specific env.sh -{ - echo "# auto-generated by build-toolchains.sh" - echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" - echo "export RISCV=$(printf '%q' "$RISCV")" - echo "export PATH=\${RISCV}/bin:\${PATH}" - echo "export LD_LIBRARY_PATH=\${RISCV}/lib\${LD_LIBRARY_PATH:+":\${LD_LIBRARY_PATH}"}" -} > env-$TOOLCHAIN.sh +cat > "$CHIPYARD_DIR/env-$TOOLCHAIN.sh" <> env.sh -echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/env-$TOOLCHAIN.sh" >> env.sh +echo "source $(printf '%q' "$CHIPYARD_DIR/env-$TOOLCHAIN.sh")" >> env.sh echo "Toolchain Build Complete!" diff --git a/scripts/build-util.sh b/scripts/build-util.sh index 10a7cb7b..892b274d 100644 --- a/scripts/build-util.sh +++ b/scripts/build-util.sh @@ -15,7 +15,7 @@ case ${ncpu} in esac # Allow user to override MAKE -[ -n "${MAKE}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make) +[ -n "${MAKE:+x}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make) readonly MAKE diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index d91e89b9..cede5e47 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -17,10 +17,11 @@ if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then false fi -RDIR=$(git rev-parse --show-toplevel) +DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")" +CHIPYARD_DIR="$(dirname "$DIR")" # Ignore toolchain submodules -cd "$RDIR" +cd "$CHIPYARD_DIR" for name in toolchains/*-tools/*/ ; do git config submodule."${name%/}".update none done @@ -71,8 +72,11 @@ git config submodule.sims/firesim.update none git submodule update --init software/firemarshal # Configure firemarshal to know where our firesim installation is -if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then - echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml +if [ ! -f ./software/firemarshal/marshal-config.yaml ]; then + echo "firesim-dir: '../../sims/firesim/'" > ./software/firemarshal/marshal-config.yaml fi -echo "# line auto-generated by init-submodules-no-riscv-tools.sh" >> $RDIR/env.sh -echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh + +echo "# line auto-generated by init-submodules-no-riscv-tools.sh" >> env.sh +echo '__DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"' >> env.sh +echo "PATH=\$__DIR/bin:\$PATH" >> env.sh +echo "PATH=\$__DIR/software/firemarshal:\$PATH" >> env.sh From b007d79820c13c5e93d3cc43315879a9d577fdf7 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 17 Aug 2020 20:28:05 -0700 Subject: [PATCH 107/457] Add help section to makefiles + Reorganize --- common.mk | 55 ++++++++---- sims/vcs/Makefile | 111 +++++++++++++++++++++++-- sims/verilator/Makefile | 175 +++++++++++++++++++++++++++++---------- tools/dromajo/dromajo.mk | 3 +- variables.mk | 60 +++++++++----- 5 files changed, 316 insertions(+), 88 deletions(-) diff --git a/common.mk b/common.mk index 43615a92..87d4047c 100644 --- a/common.mk +++ b/common.mk @@ -3,22 +3,46 @@ ######################################################################################### SHELL=/bin/bash - ifndef RISCV $(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file) else $(info Running with RISCV=$(RISCV)) endif +######################################################################################### +# specify user-interface variables +######################################################################################### +HELP_COMPILATION_VARIABLES += \ +" EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ +" EXTRA_SIM_CFLAGS = CFLAGS for building simulators" \ +" EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ +" EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ +" EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ +" EXTRA_SIM_REQS = requirements to build the simulator" + +EXTRA_GENERATOR_REQS ?= +EXTRA_SIM_CXXFLAGS ?= +EXTRA_SIM_CFLAGS ?= +EXTRA_SIM_LDFLAGS ?= +EXTRA_SIM_SOURCES ?= +EXTRA_SIM_REQS ?= + +#---------------------------------------------------------------------------- +HELP_SIMULATION_VARIABLES += \ +" EXTRA_SIM_FLAGS = runtime simulation flags (passed within +permissive)" + +EXTRA_SIM_FLAGS ?= + +#---------------------------------------------------------------------------- +HELP_COMMANDS += \ +" run-binary = run [./$(shell basename $(sim))] and log instructions to file" \ +" run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ +" run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ +" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" ######################################################################################### -# extra make variables/rules from subprojects -# -# EXTRA_GENERATOR_REQS - requirements needed for the main generator -# EXTRA_SIM_FLAGS - runtime simulation flags -# EXTRA_SIM_CC_FLAGS - cc flags for simulators -# EXTRA_SIM_SOURCES - simulation sources needed for simulator -# EXTRA_SIM_REQS - requirements to build the simulator +# include additional subproject make fragments +# see HELP_COMPILATION_VARIABLES ######################################################################################### include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk @@ -55,7 +79,6 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ touch $@ - ######################################################################################### # Bloop Project Definitions ######################################################################################### @@ -139,19 +162,19 @@ verilog: $(sim_vsrcs) ######################################################################################### # helper rules to run simulations ######################################################################################### -.PHONY: run-binary run-binary-fast run-binary-debug run-fast +.PHONY: run-binary run-binary-fast +.PHONY: run-binary-debug +.PHONY: run-fast + +# run normal binary with hardware-logged insn dissassembly run-binary: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) -######################################################################################### -# helper rules to run simulator as fast as possible -######################################################################################### +# run simulator as fast as possible (no insn disassembly) run-binary-fast: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 14ebae59..46b3a267 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,7 +25,10 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -include $(base_dir)/vcs.mk +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off + +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd .PHONY: default debug default: $(sim) @@ -36,22 +39,97 @@ debug: $(sim_debug) ######################################################################################### include $(base_dir)/common.mk +######################################################################################### +# verilator-specific user-interface variables and commands +######################################################################################### +HELP_COMPILATION_VARIABLES += +HELP_COMMANDS += \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and verilator-generated files" \ +" clean-sim-debug = removes debug simulator and verilator-generated files" + ######################################################################################### # vcs binary and arguments ######################################################################################### VCS = vcs -full64 -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES) +PREPROC_DEFINES = \ + +define+VCS \ + +define+CLOCK_PERIOD=1.0 \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN + +VCS_NONCC_OPTS = \ + -notice \ + -line \ + +lint=all,noVCDE,noONGS,noUI \ + -timescale=1ns/1ps \ + -quiet \ + -q \ + +rad \ + +vcs+lic+wait \ + +vc+list \ + -error=noZMMCM \ + -error=PCWM-L \ + -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ + +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ + +incdir+$(build_dir) \ + $(PREPROC_DEFINES) \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VCS_CXXFLAGS = \ + $(CXXFLAGS) \ + $(CMODE) \ + -I$(VCS_HOME)/include \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -std=c++11 \ + $(EXTRA_SIM_CXXFLAGS) + +VCS_LDFLAGS = \ + $(LDFLAGS) \ + $(CMODE) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VCS_CC_OPTS = \ + -CFLAGS "$(VCS_CXXFLAGS)" \ + -LDFLAGS "$(VCS_LDFLAGS)" + +#---------------------------------------------------------------------------------------- +# full vcs+gcc opts +#---------------------------------------------------------------------------------------- +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) ######################################################################################### # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ + -debug_pp $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ + +define+DEBUG \ + -debug_pp ######################################################################################### # create a vcs vpd rule @@ -60,9 +138,26 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) +$(output_dir)/none.vpd: $(sim_debug) + mkdir -p $(output_dir) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) + ######################################################################################### -# general cleanup rule +# general cleanup rules ######################################################################################### -.PHONY: clean +.PHONY: clean clean-sim clean-sim-debug clean: - rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h + rm -rf $(gen_dir) $(sim_prefix)-* + +clean-sim: + rm -rf csrc/ $(sim) ucli.key vc_hdrs.h + +clean-sim-debug: + rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h + +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3d676efd..07ece1c5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -22,7 +22,7 @@ include $(base_dir)/variables.mk sim_name = verilator ######################################################################################### -# vcs simulator types and rules +# verilator simulator types and rules ######################################################################################### sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) @@ -47,67 +47,141 @@ debug: $(sim_debug) include $(base_dir)/common.mk ######################################################################################### -# verilator binary and flags +# verilator-specific user-interface variables and commands +######################################################################################### +HELP_COMPILATION_VARIABLES += \ +" VERILATOR_PROFILE = 'none' if no verilator profiling (default)" \ +" 'all' if full verilator runtime profiling" \ +" 'threads' if runtime thread profiling only" \ +" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" + +HELP_COMMANDS += \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and verilator-generated files" \ +" clean-sim-debug = removes debug simulator and verilator-generated files" + +######################################################################################### +# verilator/cxx binary and flags ######################################################################################### VERILATOR := verilator --cc --exe -CXXFLAGS := \ - $(CXXFLAGS) -O1 -std=c++11 \ - -I$(RISCV)/include \ - -I$(dramsim_dir) \ - -D__STDC_FORMAT_MACROS \ - $(EXTRA_SIM_CC_FLAGS) +#---------------------------------------------------------------------------------------- +# user configs +#---------------------------------------------------------------------------------------- +VERILATOR_PROFILE ?= none +RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,) +RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\ + --prof-threads --prof-cfuncs,\ + $(if $(filter $(VERILATOR_PROFILE),threads),\ + --prof-threads,)) -LDFLAGS := \ - $(LDFLAGS) \ - -L$(sim_dir) \ - -lpthread +VERILATOR_FST_MODE ?= 0 +TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\ + --trace,--trace-fst --trace-threads 1) +TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) -VERILATOR_CC_OPTS = \ +#---------------------------------------------------------------------------------------- +# verilation configuration/optimization +#---------------------------------------------------------------------------------------- +# we initially had --noassert for performance, but several modules use +# assertions, including dramsim, so we enable --assert by default +VMODE := \ -O3 \ - -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ - -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ - -LDFLAGS "$(LDFLAGS)" \ - $(RISCV)/lib/libfesvr.a \ - $(dramsim_lib) + --x-assign fast \ + --x-initial fast \ + --assert \ + --output-split 10000 \ + --output-split-cfuncs 10000 -# default flags added for ariane -ARIANE_VERILATOR_FLAGS = \ +# default flags added for ariane (-Wno-fatal needed for -Wall to not cause +# a crash, since 1000s of warnings are generated) +VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ - -Werror-PINMISSING \ - -Werror-IMPLICIT \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ -Wno-UNUSED \ -Wno-UNOPTFLAT \ -Wno-BLKANDNBLK \ - -Wno-style \ - -Wall + -Wno-fatal -# normal flags used for chipyard builds (that are incompatible with ariane) -CHIPYARD_VERILATOR_FLAGS = \ - --assert +# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane) +CHIPYARD_VERILATOR_FLAGS := + +# options dependent on whether ariane/NVDLA or chipyard is used +# NOTE: defer the evaluation of this until it is used! +PLATFORM_OPTS = $(shell \ + if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \ + then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ + else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) # Use --timescale to approximate timescale behavior of pre-4.034 TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }') -VERILATOR_NONCC_OPTS = \ - $(TIMESCALE_OPTS) \ - --top-module $(VLOG_MODEL) \ - --vpi \ - -Wno-fatal \ - $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ - --output-split 10000 \ - --output-split-cfuncs 100 \ - --max-num-width 1048576 \ - -f $(sim_common_files) \ - $(sim_vsrcs) -VERILATOR_DEFINES = \ +# see: https://github.com/ucb-bar/riscv-mini/issues/31 +MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }') + +PREPROC_DEFINES := \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES) +VERILATOR_NONCC_OPTS = \ + $(RUNTIME_PROFILING_VFLAGS) \ + $(VMODE) \ + $(PLATFORM_OPTS) \ + $(TIMESCALE_OPTS) \ + $(MAX_WIDTH_OPTS) \ + $(PREPROC_DEFINES) \ + --top-module $(VLOG_MODEL) \ + --vpi \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VERILATOR_CXXFLAGS = \ + $(CXXFLAGS) \ + $(RUNTIME_PROFILING_CFLAGS) \ + $(TRACING_CFLAGS) \ + $(CMODE) \ + -std=c++11 \ + -D__STDC_FORMAT_MACROS \ + -DTEST_HARNESS=V$(VLOG_MODEL) \ + -DVERILATOR \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -I$(build_dir) \ + -include $(build_dir)/$(long_name).plusArgs \ + -include $(build_dir)/verilator.h \ + $(EXTRA_SIM_CXXFLAGS) + +VERILATOR_LDFLAGS = \ + $(LDFLAGS) \ + $(RUNTIME_PROFILING_CFLAGS) \ + $(CMODE) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -lpthread \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VERILATOR_CC_OPTS = \ + -CFLAGS "$(VERILATOR_CXXFLAGS)" \ + -LDFLAGS "$(VERILATOR_LDFLAGS)" + +#---------------------------------------------------------------------------------------- +# full verilator+gcc opts +#---------------------------------------------------------------------------------------- +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) ######################################################################################### # verilator build paths and file names @@ -127,13 +201,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir) mkdir -p $(model_dir) - $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" + $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) - $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### @@ -155,8 +229,21 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### -# general cleanup rule +# general cleanup rules ######################################################################################### -.PHONY: clean +.PHONY: clean clean-sim clean-sim-debug clean: rm -rf $(gen_dir) $(sim_prefix)-* + +clean-sim: + rm -rf $(model_dir) $(sim) + +clean-sim-debug: + rm -rf $(model_dir_debug) $(sim_debug) + +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/tools/dromajo/dromajo.mk b/tools/dromajo/dromajo.mk index 067faa2f..4ac17764 100644 --- a/tools/dromajo/dromajo.mk +++ b/tools/dromajo/dromajo.mk @@ -49,7 +49,8 @@ ifdef ENABLE_DROMAJO EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) # CC flags needed for all simulations -EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR) +EXTRA_SIM_CFLAGS += -I$(DROMAJO_DIR) +EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR) # sourced needed for simulation EXTRA_SIM_SOURCES += $(DROMAJO_LIB) diff --git a/variables.mk b/variables.mk index d7eccb49..e41648d4 100644 --- a/variables.mk +++ b/variables.mk @@ -1,23 +1,45 @@ ######################################################################################### # makefile variables shared across multiple makefiles +# - to use the help text, your Makefile should have a 'help' target that just +# prints all the HELP_LINES ######################################################################################### +HELP_COMPILATION_VARIABLES = +HELP_PROJECT_VARIABLES = \ +" SUB_PROJECT = use the specific subproject default variables [$(SUB_PROJECT)]" \ +" SBT_PROJECT = the SBT project that you should find the classes/packages in [$(SBT_PROJECT)]" \ +" MODEL = the top level module of the project in Chisel (normally the harness) [$(MODEL)]" \ +" VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) [$(VLOG_MODEL)]" \ +" MODEL_PACKAGE = the scala package to find the MODEL in [$(MODEL_PACKAGE)]" \ +" CONFIG = the configuration class to give the parameters for the project [$(CONFIG)]" \ +" CONFIG_PACKAGE = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \ +" GENERATOR_PACKAGE = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \ +" TB = wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \ +" TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" -######################################################################################### -# variables to invoke the generator -# descriptions: -# SBT_PROJECT = the SBT project that you should find the classes/packages in -# MODEL = the top level module of the project in Chisel (normally the harness) -# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) -# MODEL_PACKAGE = the scala package to find the MODEL in -# CONFIG = the configuration class to give the parameters for the project -# CONFIG_PACKAGE = the scala package to find the CONFIG class -# GENERATOR_PACKAGE = the scala package to find the Generator class in -# TB = wrapper over the TestHarness needed to simulate in a verilog simulator -# TOP = top level module of the project (normally the module instantiated by the harness) -# -# project specific: -# SUB_PROJECT = use the specific subproject default variables -######################################################################################### +HELP_SIMULATION_VARIABLES = \ +" BINARY = riscv binary that the simulator will run" \ +" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" + +HELP_COMMANDS = \ +" help = display this help" + +HELP_LINES = "" \ + " design specifier variables:" \ + " ---------------------------" \ + $(HELP_PROJECT_VARIABLES) \ + "" \ + " compilation variables:" \ + " ----------------------" \ + $(HELP_COMPILATION_VARIABLES) \ + "" \ + " simulation variables:" \ + " ---------------------" \ + $(HELP_SIMULATION_VARIABLES) \ + "" \ + " some useful general commands:" \ + " -----------------" \ + $(HELP_COMMANDS) \ + "" ######################################################################################### # subproject overrides @@ -140,15 +162,15 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # 1) the sed removes a leading {file:} that sometimes needs to be # provided to SBT when a project but not for bloop. # 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the +# destined for the scala Main, however a bug in Bloop's argument parsing causes the # --nailgun-port argument to be lost in this case. Workaround this by prefixing # every main-destined argument with "--args" define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) + cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif From b0b09870ddf0ebc543383c1ee64495177d4d7c3c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 17 Aug 2020 21:11:44 -0700 Subject: [PATCH 108/457] 2-stage core passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 989c9831..602ff66b 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 989c98313c147b0c91614228dfc8b1dfb78c5200 +Subproject commit 602ff66b0ef487df1d01c176eb3c62f8443b274e From d82e7dbed5d46acce92e029d925875ebe8eaddbf Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 10:40:45 -0700 Subject: [PATCH 109/457] Cleanup more --- docs/Simulation/Software-RTL-Simulation.rst | 28 +++++++++++++++++++++ sims/vcs/Makefile | 9 +------ variables.mk | 6 ++--- 3 files changed, 32 insertions(+), 11 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index ca852d36..9219f5a3 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -61,6 +61,11 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. +The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. + +.. code-block:: shell + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -141,6 +146,29 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. +Fast Memory Loading +------------------- + +The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. + +.. code-block:: shell + + make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + +The ``.hex`` file should be a text file with a hexadecimal number on each line. + +.. code-block:: text + + deadbeef + 0123 + +Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. + +A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available. + +.. code-block:: shell + + make run-binary-hex BINARY=test.riscv Generating Waveforms ----------------------- diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 46b3a267..766350ff 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,10 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - -WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +include $(base_dir)/vcs.mk .PHONY: default debug default: $(sim) @@ -138,10 +135,6 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) -$(output_dir)/none.vpd: $(sim_debug) - mkdir -p $(output_dir) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) - ######################################################################################### # general cleanup rules ######################################################################################### diff --git a/variables.mk b/variables.mk index e41648d4..e347ccf0 100644 --- a/variables.mk +++ b/variables.mk @@ -162,15 +162,15 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # 1) the sed removes a leading {file:} that sometimes needs to be # provided to SBT when a project but not for bloop. # 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the +# destined for the scala Main, however a bug in Bloop's argument parsing causes the # --nailgun-port argument to be lost in this case. Workaround this by prefixing # every main-destined argument with "--args" define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) + cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif From c3749ce88f5f498fb0b9e19703ae2664aa4a8492 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 10:41:35 -0700 Subject: [PATCH 110/457] Add space --- docs/Simulation/Software-RTL-Simulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 9219f5a3..af568ef4 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -64,6 +64,7 @@ For instance, to run one of the riscv-tools assembly tests. The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. .. code-block:: shell + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. From 4e7b9d195fef6c036469281891403af6bfb7f4da Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 10:45:11 -0700 Subject: [PATCH 111/457] Dedup default simulation rules --- sims/vcs/Makefile | 11 ----------- sims/verilator/Makefile | 7 ------- variables.mk | 8 +++++++- 3 files changed, 7 insertions(+), 19 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 766350ff..3f0c0792 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -36,17 +36,6 @@ debug: $(sim_debug) ######################################################################################### include $(base_dir)/common.mk -######################################################################################### -# verilator-specific user-interface variables and commands -######################################################################################### -HELP_COMPILATION_VARIABLES += -HELP_COMMANDS += \ -" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ -" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ -" clean = remove all debug/non-debug simulators and intermediate files" \ -" clean-sim = removes non-debug simulator and verilator-generated files" \ -" clean-sim-debug = removes debug simulator and verilator-generated files" - ######################################################################################### # vcs binary and arguments ######################################################################################### diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 07ece1c5..e2f85495 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -55,13 +55,6 @@ HELP_COMPILATION_VARIABLES += \ " 'threads' if runtime thread profiling only" \ " VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" -HELP_COMMANDS += \ -" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ -" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ -" clean = remove all debug/non-debug simulators and intermediate files" \ -" clean-sim = removes non-debug simulator and verilator-generated files" \ -" clean-sim-debug = removes debug simulator and verilator-generated files" - ######################################################################################### # verilator/cxx binary and flags ######################################################################################### diff --git a/variables.mk b/variables.mk index e347ccf0..1522aa2e 100644 --- a/variables.mk +++ b/variables.mk @@ -20,8 +20,14 @@ HELP_SIMULATION_VARIABLES = \ " BINARY = riscv binary that the simulator will run" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" +# include default simulation rules HELP_COMMANDS = \ -" help = display this help" +" help = display this help" \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and simulator-generated files" \ +" clean-sim-debug = removes debug simulator and simulator-generated files" HELP_LINES = "" \ " design specifier variables:" \ From 3b991f3ed7c27b2d6b98fdf14ba8521263719e88 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 11:14:01 -0700 Subject: [PATCH 112/457] Move vcs flags to vcs.mk | Misc. cleanup --- common.mk | 2 -- sims/vcs/Makefile | 70 ++-------------------------------------- sims/verilator/Makefile | 1 - tools/dromajo/dromajo.mk | 1 - vcs.mk | 38 ++++++++++++++++++---- vlsi/Makefile | 10 ++++-- 6 files changed, 42 insertions(+), 80 deletions(-) diff --git a/common.mk b/common.mk index 87d4047c..be787a9d 100644 --- a/common.mk +++ b/common.mk @@ -14,7 +14,6 @@ endif ######################################################################################### HELP_COMPILATION_VARIABLES += \ " EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ -" EXTRA_SIM_CFLAGS = CFLAGS for building simulators" \ " EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ " EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ @@ -22,7 +21,6 @@ HELP_COMPILATION_VARIABLES += \ EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= -EXTRA_SIM_CFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 3f0c0792..efe0dc3c 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -41,81 +41,17 @@ include $(base_dir)/common.mk ######################################################################################### VCS = vcs -full64 -PREPROC_DEFINES = \ - +define+VCS \ - +define+CLOCK_PERIOD=1.0 \ - +define+PRINTF_COND=$(TB).printf_cond \ - +define+STOP_COND=!$(TB).reset \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN - -VCS_NONCC_OPTS = \ - -notice \ - -line \ - +lint=all,noVCDE,noONGS,noUI \ - -timescale=1ns/1ps \ - -quiet \ - -q \ - +rad \ - +vcs+lic+wait \ - +vc+list \ - -error=noZMMCM \ - -error=PCWM-L \ - -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ - +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ - +incdir+$(build_dir) \ - $(PREPROC_DEFINES) \ - -f $(sim_common_files) \ - $(sim_vsrcs) - -#---------------------------------------------------------------------------------------- -# gcc configuration/optimization -#---------------------------------------------------------------------------------------- -# -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 -fbranch-probabilities -march=native - -VCS_CXXFLAGS = \ - $(CXXFLAGS) \ - $(CMODE) \ - -I$(VCS_HOME)/include \ - -I$(RISCV)/include \ - -I$(dramsim_dir) \ - -std=c++11 \ - $(EXTRA_SIM_CXXFLAGS) - -VCS_LDFLAGS = \ - $(LDFLAGS) \ - $(CMODE) \ - -L$(RISCV)/lib \ - -Wl,-rpath,$(RISCV)/lib \ - -L$(sim_dir) \ - -L$(dramsim_dir) \ - -lfesvr \ - -ldramsim \ - $(EXTRA_SIM_LDFLAGS) - -VCS_CC_OPTS = \ - -CFLAGS "$(VCS_CXXFLAGS)" \ - -LDFLAGS "$(VCS_LDFLAGS)" - -#---------------------------------------------------------------------------------------- -# full vcs+gcc opts -#---------------------------------------------------------------------------------------- -VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) ######################################################################################### # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ - -debug_pp + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ - +define+DEBUG \ - -debug_pp + +define+DEBUG ######################################################################################### # create a vcs vpd rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index e2f85495..2cba66ab 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -157,7 +157,6 @@ VERILATOR_CXXFLAGS = \ VERILATOR_LDFLAGS = \ $(LDFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ - $(CMODE) \ -L$(RISCV)/lib \ -Wl,-rpath,$(RISCV)/lib \ -L$(sim_dir) \ diff --git a/tools/dromajo/dromajo.mk b/tools/dromajo/dromajo.mk index 4ac17764..2069b394 100644 --- a/tools/dromajo/dromajo.mk +++ b/tools/dromajo/dromajo.mk @@ -49,7 +49,6 @@ ifdef ENABLE_DROMAJO EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) # CC flags needed for all simulations -EXTRA_SIM_CFLAGS += -I$(DROMAJO_DIR) EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR) # sourced needed for simulation diff --git a/vcs.mk b/vcs.mk index 93e75c19..28ed0f51 100644 --- a/vcs.mk +++ b/vcs.mk @@ -17,9 +17,37 @@ VCS_CC_OPTS = \ -CC "-std=c++11" \ -CC "$(EXTRA_SIM_CC_FLAGS)" +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VCS_CXXFLAGS = \ + $(CXXFLAGS) \ + $(CMODE) \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -std=c++11 \ + $(EXTRA_SIM_CXXFLAGS) + +VCS_LDFLAGS = \ + $(LDFLAGS) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VCS_CC_OPTS = \ + -CFLAGS "$(VCS_CXXFLAGS)" \ + -LDFLAGS "$(VCS_LDFLAGS)" + VCS_NONCC_OPTS = \ - $(dramsim_lib) \ - $(RISCV)/lib/libfesvr.a \ + -notice \ + -line \ +lint=all,noVCDE,noONGS,noUI \ -error=PCWM-L \ -error=noZMMCM \ @@ -27,7 +55,6 @@ VCS_NONCC_OPTS = \ -quiet \ -q \ +rad \ - +v2k \ +vcs+lic+wait \ +vc+list \ -f $(sim_common_files) \ @@ -35,10 +62,9 @@ VCS_NONCC_OPTS = \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ -debug_pp \ +incdir+$(build_dir) \ - $(sim_vsrcs) \ - +libext+.v + $(sim_vsrcs) -VCS_DEFINE_OPTS = \ +PREPROC_DEFINES = \ +define+VCS \ +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ +define+RESET_DELAY=$(RESET_DELAY) \ diff --git a/vlsi/Makefile b/vlsi/Makefile index a9e3d3a5..3bbca7e0 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -115,12 +115,16 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " options_meta: 'append'" >> $@ echo " defines:" >> $@ - for x in $(subst +define+,,$(VCS_DEFINE_OPTS)); do \ + for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ echo ' - "'$$x'"' >> $@; \ done echo " defines_meta: 'append'" >> $@ - echo " compiler_opts:" >> $@ - for x in $(filter-out "",$(filter-out -CC,$(VCS_CC_OPTS))); do \ + echo " compiler_cc_opts:" >> $@ + for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " compiler_ld_opts:" >> $@ + for x in $(filter-out "",$(VCS_LDFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done echo " compiler_opts_meta: 'append'" >> $@ From 15f508bcbf9b5dda5de5db74bf0319a31221defd Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 11:36:48 -0700 Subject: [PATCH 113/457] First pass at updating hammer submodules --- vcs.mk | 6 ------ vlsi/hammer | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/vcs.mk b/vcs.mk index 28ed0f51..9367cca9 100644 --- a/vcs.mk +++ b/vcs.mk @@ -11,12 +11,6 @@ endif CLOCK_PERIOD ?= 1.0 RESET_DELAY ?= 777.7 -VCS_CC_OPTS = \ - -CC "-I$(RISCV)/include" \ - -CC "-I$(dramsim_dir)" \ - -CC "-std=c++11" \ - -CC "$(EXTRA_SIM_CC_FLAGS)" - #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- diff --git a/vlsi/hammer b/vlsi/hammer index cbc907df..56739c32 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit cbc907dfe8005a8d72f1b2fb7b414ad9dbfe14b1 +Subproject commit 56739c32a81c82bdb065613cc3aa878f1ca40d4c diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index e5ec0da8..bd0e5c90 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit e5ec0da8ad471b075de62989001b282e537416d0 +Subproject commit bd0e5c90126cb517928082517cf9af24ec27bfbb From 8743f3ab95ca65d96f9482949a2dcb8fbd04523e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 11:43:40 -0700 Subject: [PATCH 114/457] Bump hammer --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 56739c32..da9c84f3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 56739c32a81c82bdb065613cc3aa878f1ca40d4c +Subproject commit da9c84f35c1b2df0feaba11395ba4e4570ab5b67 From aca96a7f4d2e89c36f9731a6542b43fbb9744428 Mon Sep 17 00:00:00 2001 From: Jacob Gadikian Date: Wed, 19 Aug 2020 01:49:15 +0700 Subject: [PATCH 115/457] Update ubuntu-req.sh (#645) Use more cores when we can, and fewer when we can't use more --- scripts/ubuntu-req.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index f72c48f4..a4697174 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -24,4 +24,4 @@ sudo apt-get install -y device-tree-compiler git clone http://git.veripool.org/git/verilator cd verilator git checkout v4.034 -autoconf && ./configure && make -j16 && sudo make install +autoconf && ./configure && make -j$(nproc) && sudo make install From 9bc9d48fe467c67fbd558b413a022c50031605f9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 18 Aug 2020 21:23:13 -0700 Subject: [PATCH 116/457] Fix vlsi/Makefile opts meta --- vlsi/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 3bbca7e0..fe63c346 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -123,11 +123,12 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done + echo " compiler_cc_opts_meta: 'append'" >> $@ echo " compiler_ld_opts:" >> $@ for x in $(filter-out "",$(VCS_LDFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done - echo " compiler_opts_meta: 'append'" >> $@ + echo " compiler_ls_opts_meta: 'append'" >> $@ echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags:" >> $@ From d020058d1994df92e853064b1fa8c7bfa2a04c90 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 18 Aug 2020 23:35:03 -0700 Subject: [PATCH 117/457] Split up LDFLAGS into LDFLAGS and -l --- vcs.mk | 4 +++- vlsi/hammer-synopsys-plugins | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/vcs.mk b/vcs.mk index 9367cca9..daed8af4 100644 --- a/vcs.mk +++ b/vcs.mk @@ -35,9 +35,11 @@ VCS_LDFLAGS = \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) +# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate) VCS_CC_OPTS = \ -CFLAGS "$(VCS_CXXFLAGS)" \ - -LDFLAGS "$(VCS_LDFLAGS)" + -LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \ + $(filter -l%,$(VCS_LDFLAGS)) VCS_NONCC_OPTS = \ -notice \ diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index bd0e5c90..706e3f6e 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit bd0e5c90126cb517928082517cf9af24ec27bfbb +Subproject commit 706e3f6e8dbba8f2e36b009daaf6cf9596ab68e9 From d4af9e16600a67cfeb5c18b464968651ab63f432 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 10:48:43 -0700 Subject: [PATCH 118/457] Fix separator --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index 1522aa2e..be022e12 100644 --- a/variables.mk +++ b/variables.mk @@ -43,7 +43,7 @@ HELP_LINES = "" \ $(HELP_SIMULATION_VARIABLES) \ "" \ " some useful general commands:" \ - " -----------------" \ + " -----------------------------" \ $(HELP_COMMANDS) \ "" From de4e311dd341080202b43254750075abbe1a1dd6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 11:21:35 -0700 Subject: [PATCH 119/457] Remove extra CMODE flags --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 2cba66ab..f71f9de5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -136,7 +136,7 @@ VERILATOR_NONCC_OPTS = \ # gcc configuration/optimization #---------------------------------------------------------------------------------------- # -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 -fbranch-probabilities -march=native +CMODE := -O3 VERILATOR_CXXFLAGS = \ $(CXXFLAGS) \ From 0dd2197477a1e578925dcb2bebd7f65b7bdf39f4 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 21:48:19 -0700 Subject: [PATCH 120/457] Fix meta key --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index fe63c346..c0a6fdd3 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -128,7 +128,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file for x in $(filter-out "",$(VCS_LDFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done - echo " compiler_ls_opts_meta: 'append'" >> $@ + echo " compiler_ld_opts_meta: 'append'" >> $@ echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags:" >> $@ From b7d9472b4ad6a6ba3ad85b3845de812e1be3cfe7 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 22:10:18 -0700 Subject: [PATCH 121/457] Cleanup help commands --- common.mk | 22 +++++++++++++++------- sims/vcs/Makefile | 7 ------- sims/verilator/Makefile | 7 ------- variables.mk | 2 +- 4 files changed, 16 insertions(+), 22 deletions(-) diff --git a/common.mk b/common.mk index be787a9d..83b74287 100644 --- a/common.mk +++ b/common.mk @@ -13,11 +13,11 @@ endif # specify user-interface variables ######################################################################################### HELP_COMPILATION_VARIABLES += \ -" EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ -" EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ -" EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ -" EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ -" EXTRA_SIM_REQS = requirements to build the simulator" +" EXTRA_GENERATOR_REQS = additional make requirements needed for the main generator" \ +" EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ +" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ +" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ +" EXTRA_SIM_REQS = additional make requirements to build the simulator" EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= @@ -27,7 +27,7 @@ EXTRA_SIM_REQS ?= #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ -" EXTRA_SIM_FLAGS = runtime simulation flags (passed within +permissive)" +" EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)" EXTRA_SIM_FLAGS ?= @@ -36,7 +36,8 @@ HELP_COMMANDS += \ " run-binary = run [./$(shell basename $(sim))] and log instructions to file" \ " run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ " run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ -" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" +" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" \ +" run-tests = run all assembly and benchmark tests" ######################################################################################### # include additional subproject make fragments @@ -232,6 +233,13 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done + ######################################################################################### # Implicit rule handling ######################################################################################### diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index efe0dc3c..ac792e63 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -72,10 +72,3 @@ clean-sim: clean-sim-debug: rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h - -######################################################################################### -# print help text -######################################################################################### -.PHONY: help -help: - @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index f71f9de5..9965001d 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -232,10 +232,3 @@ clean-sim: clean-sim-debug: rm -rf $(model_dir_debug) $(sim_debug) - -######################################################################################### -# print help text -######################################################################################### -.PHONY: help -help: - @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/variables.mk b/variables.mk index be022e12..7f3d1eee 100644 --- a/variables.mk +++ b/variables.mk @@ -17,7 +17,7 @@ HELP_PROJECT_VARIABLES = \ " TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" HELP_SIMULATION_VARIABLES = \ -" BINARY = riscv binary that the simulator will run" \ +" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" # include default simulation rules From af61c533dab801301d00eb8afd7ebf064b64b156 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 22:15:55 -0700 Subject: [PATCH 122/457] Merge .PHONY variables --- common.mk | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common.mk b/common.mk index 83b74287..4aa0a903 100644 --- a/common.mk +++ b/common.mk @@ -161,9 +161,7 @@ verilog: $(sim_vsrcs) ######################################################################################### # helper rules to run simulations ######################################################################################### -.PHONY: run-binary run-binary-fast -.PHONY: run-binary-debug -.PHONY: run-fast +.PHONY: run-binary run-binary-fast run-binary-debug run-fast # run normal binary with hardware-logged insn dissassembly run-binary: $(output_dir) $(sim) From 4f3319dc010304c74078dead4f87d5b7b653c6cc Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 22:16:45 -0700 Subject: [PATCH 123/457] Revert make clean for VCS --- sims/vcs/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index ac792e63..a2896380 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -65,7 +65,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean-sim clean-sim-debug clean: - rm -rf $(gen_dir) $(sim_prefix)-* + rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h clean-sim: rm -rf csrc/ $(sim) ucli.key vc_hdrs.h From e5158cbe4c4d9fd7554961a1e26291a08eb4e58b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 22:32:47 -0700 Subject: [PATCH 124/457] Rename some variables --- sims/verilator/Makefile | 10 ++++++---- vcs.mk | 4 ++-- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9965001d..52c78eb6 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -80,7 +80,7 @@ TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) #---------------------------------------------------------------------------------------- # we initially had --noassert for performance, but several modules use # assertions, including dramsim, so we enable --assert by default -VMODE := \ +VERILATOR_OPT_FLAGS := \ -O3 \ --x-assign fast \ --x-initial fast \ @@ -92,6 +92,8 @@ VMODE := \ # a crash, since 1000s of warnings are generated) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ + -Werror-PINMISSING \ + -Werror-IMPLICIT \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ @@ -122,7 +124,7 @@ PREPROC_DEFINES := \ VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ - $(VMODE) \ + $(VERILATOR_OPT_FLAGS) \ $(PLATFORM_OPTS) \ $(TIMESCALE_OPTS) \ $(MAX_WIDTH_OPTS) \ @@ -136,13 +138,13 @@ VERILATOR_NONCC_OPTS = \ # gcc configuration/optimization #---------------------------------------------------------------------------------------- # -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 +CXX_OPT_FLAGS := -O3 VERILATOR_CXXFLAGS = \ $(CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ $(TRACING_CFLAGS) \ - $(CMODE) \ + $(CXX_OPT_FLAGS) \ -std=c++11 \ -D__STDC_FORMAT_MACROS \ -DTEST_HARNESS=V$(VLOG_MODEL) \ diff --git a/vcs.mk b/vcs.mk index daed8af4..ef5761df 100644 --- a/vcs.mk +++ b/vcs.mk @@ -15,11 +15,11 @@ RESET_DELAY ?= 777.7 # gcc configuration/optimization #---------------------------------------------------------------------------------------- # -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 -fbranch-probabilities -march=native +CXX_OPT_FLAGS := -O3 -fbranch-probabilities -march=native VCS_CXXFLAGS = \ $(CXXFLAGS) \ - $(CMODE) \ + $(CXX_OPT_FLAGS) \ -I$(RISCV)/include \ -I$(dramsim_dir) \ -std=c++11 \ From 9087b58cf08c722902c9c10d139f3f6db8f01db3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 22:35:02 -0700 Subject: [PATCH 125/457] Add testbench to description --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index 7f3d1eee..b187a23d 100644 --- a/variables.mk +++ b/variables.mk @@ -13,7 +13,7 @@ HELP_PROJECT_VARIABLES = \ " CONFIG = the configuration class to give the parameters for the project [$(CONFIG)]" \ " CONFIG_PACKAGE = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \ " GENERATOR_PACKAGE = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \ -" TB = wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \ +" TB = testbench wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \ " TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" HELP_SIMULATION_VARIABLES = \ From e77e610ee4920873b44398fb32e09dddcf30ebca Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 23:42:41 -0700 Subject: [PATCH 126/457] Fix Hammer Sim --- vcs.mk | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vcs.mk b/vcs.mk index ef5761df..a282aa44 100644 --- a/vcs.mk +++ b/vcs.mk @@ -14,8 +14,7 @@ RESET_DELAY ?= 777.7 #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- -# -flto slows down compilation on small-memory and breaks on firesim-manager -CXX_OPT_FLAGS := -O3 -fbranch-probabilities -march=native +CXX_OPT_FLAGS := -O3 VCS_CXXFLAGS = \ $(CXXFLAGS) \ From 9d3c14034dac9daa763ff9cad82326624d3ae5fb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 10:40:21 -0700 Subject: [PATCH 127/457] Revert Verilator external IP flags --- sims/verilator/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 52c78eb6..685b7939 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -88,8 +88,7 @@ VERILATOR_OPT_FLAGS := \ --output-split 10000 \ --output-split-cfuncs 10000 -# default flags added for ariane (-Wno-fatal needed for -Wall to not cause -# a crash, since 1000s of warnings are generated) +# default flags added for external IP (ariane/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ -Werror-PINMISSING \ @@ -100,12 +99,13 @@ VERILOG_IP_VERILATOR_FLAGS := \ -Wno-UNUSED \ -Wno-UNOPTFLAT \ -Wno-BLKANDNBLK \ - -Wno-fatal + -Wno-style \ + -Wall # normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane) CHIPYARD_VERILATOR_FLAGS := -# options dependent on whether ariane/NVDLA or chipyard is used +# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \ From 435bfac45e6fa073923eca003cb9e8236074ad2f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 16:10:14 -0700 Subject: [PATCH 128/457] Fix NVDLA/Ariane builds --- sims/verilator/Makefile | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 685b7939..10b28cb7 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -84,15 +84,12 @@ VERILATOR_OPT_FLAGS := \ -O3 \ --x-assign fast \ --x-initial fast \ - --assert \ --output-split 10000 \ --output-split-cfuncs 10000 # default flags added for external IP (ariane/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ - -Werror-PINMISSING \ - -Werror-IMPLICIT \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ @@ -102,8 +99,9 @@ VERILOG_IP_VERILATOR_FLAGS := \ -Wno-style \ -Wall -# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane) -CHIPYARD_VERILATOR_FLAGS := +# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA) +CHIPYARD_VERILATOR_FLAGS := \ + --assert # options dependent on whether external IP (ariane/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! @@ -126,6 +124,7 @@ VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ $(VERILATOR_OPT_FLAGS) \ $(PLATFORM_OPTS) \ + -Wno-fatal \ $(TIMESCALE_OPTS) \ $(MAX_WIDTH_OPTS) \ $(PREPROC_DEFINES) \ From fdda4cf8f5f6704c6814a2cdb48bfae7ec1b258d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 16:21:39 -0700 Subject: [PATCH 129/457] Update the cfuncs split --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 10b28cb7..295729b7 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -85,7 +85,7 @@ VERILATOR_OPT_FLAGS := \ --x-assign fast \ --x-initial fast \ --output-split 10000 \ - --output-split-cfuncs 10000 + --output-split-cfuncs 100 # default flags added for external IP (ariane/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ From 51d8d403be75c87e4cd20f83aac90e487f3caa88 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 23:17:25 -0700 Subject: [PATCH 130/457] bump hammer/hammer-synopsys plugins --- vlsi/hammer | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/hammer b/vlsi/hammer index da9c84f3..bed4d340 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit da9c84f35c1b2df0feaba11395ba4e4570ab5b67 +Subproject commit bed4d34094fa4c72db37a0066050c475eb5e37b2 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index 706e3f6e..f8a79222 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit 706e3f6e8dbba8f2e36b009daaf6cf9596ab68e9 +Subproject commit f8a7922220c70b6905b37ab30bda6c791b594792 From 425b8ce8503c40b3ee61af60b135134a6f322bd0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 23:37:17 -0700 Subject: [PATCH 131/457] Add support for multi-threaded verilator --- common.mk | 16 ++- docs/Simulation/Software-RTL-Simulation.rst | 15 +++ .../src/main/resources/csrc/emulator.cc | 104 +++++++++++------- scripts/numa_prefix | 67 +++++++++++ sims/verilator/Makefile | 7 +- 5 files changed, 161 insertions(+), 48 deletions(-) create mode 100755 scripts/numa_prefix diff --git a/common.mk b/common.mk index 4aa0a903..89ebbea3 100644 --- a/common.mk +++ b/common.mk @@ -27,9 +27,13 @@ EXTRA_SIM_REQS ?= #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ -" EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)" +" EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)" \ +" NUMACTL = set to '1' to wrap simulator in the appropriate numactl command" EXTRA_SIM_FLAGS ?= +NUMACTL ?= 0 + +NUMA_PREFIX = $(if $(filter $(NUMACTL),0),,$(shell $(base_dir)/scripts/numa_prefix)) #---------------------------------------------------------------------------- HELP_COMMANDS += \ @@ -165,15 +169,15 @@ verilog: $(sim_vsrcs) # run normal binary with hardware-logged insn dissassembly run-binary: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) # run simulator as fast as possible (no insn disassembly) run-binary-fast: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -209,10 +213,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% $(output_d ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index af568ef4..6d7fb2b8 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -181,3 +181,18 @@ An open-source vcd-capable waveform viewer is `GTKWave `` option enables the compiled Verilator simulator to use ```` parallel threads. +On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``numactl``. +You can also just use the ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator- ``. diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 27a8aa4a..dc8827a9 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -1,11 +1,15 @@ // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. -#include "verilated.h" #if VM_TRACE #include +#if CY_FST_TRACE +#include "verilated_fst_c.h" +#else +#include "verilated.h" #include "verilated_vcd_c.h" -#endif +#endif // CY_FST_TRACE +#endif // VM_TRACE #include #include #include "remote_bitbang.h" @@ -16,6 +20,8 @@ #include #include #include +// needed for s_vpi_vlog_info, which is needed for multithreading +#include // For option parsing, which is split across this file, Verilog, and // FESVR's HTIF, a few external files must be pulled in. The list of @@ -35,6 +41,7 @@ extern tsi_t* tsi; extern dtm_t* dtm; extern remote_bitbang_t * jtag; +extern int dramsim; static uint64_t trace_count = 0; bool verbose = false; @@ -50,6 +57,18 @@ double sc_time_stamp() return trace_count; } +// need to pull htif_argc/htif_argv out here so the thread that calls tick() +// for the HTIF device can initialize properly with the cmdline args. this +// was pulled out here for multithreading to work +static int htif_argc; +static char **htif_argv = NULL; +extern "C" int vpi_get_vlog_info(s_vpi_vlog_info *vlog_info_s) +{ + vlog_info_s->argc = htif_argc; + vlog_info_s->argv = htif_argv; + return 1; +} + static void usage(const char * program_name) { printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n", @@ -113,34 +132,34 @@ int main(int argc, char** argv) // Port numbers are 16 bit unsigned integers. uint16_t rbb_port = 0; #if VM_TRACE + const char* vcdfile_name = NULL; FILE * vcdfile = NULL; uint64_t start = 0; #endif int verilog_plusargs_legal = 1; - opterr = 1; + dramsim = 0; while (1) { static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"permissive", no_argument, 0, 'p' }, - {"permissive-off", no_argument, 0, 'o' }, + {"cycle-count", no_argument, 0, 'c' }, + {"help", no_argument, 0, 'h' }, + {"max-cycles", required_argument, 0, 'm' }, + {"seed", required_argument, 0, 's' }, + {"rbb-port", required_argument, 0, 'r' }, + {"verbose", no_argument, 0, 'V' }, + {"dramsim", no_argument, 0, 'D' }, #if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, + {"vcd", required_argument, 0, 'v' }, + {"dump-start", required_argument, 0, 'x' }, #endif HTIF_LONG_OPTIONS }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:po", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:Vpo", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index); #endif if (c == -1) break; retry: @@ -153,10 +172,10 @@ int main(int argc, char** argv) case 's': random_seed = atoi(optarg); break; case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; - case 'p': opterr = 0; break; - case 'o': opterr = 1; break; + case 'D': dramsim = 1; break; #if VM_TRACE case 'v': { + vcdfile_name = optarg; vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); if (!vcdfile) { std::cerr << "Unable to open " << optarg << " for VCD write\n"; @@ -188,10 +207,8 @@ int main(int argc, char** argv) #endif else if (arg.substr(0, 12) == "+cycle-count") c = 'c'; - else if (arg == "+permissive") - c = 'p'; - else if (arg == "+permissive-off") - c = 'o'; + else if (arg == "+dramsim") + c = 'D'; // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { @@ -223,13 +240,9 @@ int main(int argc, char** argv) } htif_option++; } - if(opterr) { - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; - } else { - c = 'p'; - } + std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" + << arg << "\"\n"; + c = '?'; } goto retry; } @@ -251,6 +264,10 @@ done_processing: usage(argv[0]); return 1; } + htif_argc = 1 + argc - optind; + htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + htif_argv[0] = argv[0]; + for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -264,17 +281,17 @@ done_processing: #if VM_TRACE Verilated::traceEverOn(true); // Verilator must compute traced signals +#if CY_FST_TRACE + std::unique_ptr tfp(new VerilatedFstC); +#else std::unique_ptr vcdfd(new VerilatedVcdFILE(vcdfile)); std::unique_ptr tfp(new VerilatedVcdC(vcdfd.get())); - if (vcdfile) { +#endif // CY_FST_TRACE + if (vcdfile_name) { tile->trace(tfp.get(), 99); // Trace 99 levels of hierarchy - tfp->open(""); + tfp->open(vcdfile_name); } -#endif - - jtag = new remote_bitbang_t(rbb_port); - dtm = new dtm_t(argc, argv); - tsi = new tsi_t(argc, argv); +#endif // VM_TRACE signal(SIGTERM, handle_sigterm); @@ -304,8 +321,7 @@ done_processing: tile->reset = 0; done_reset = true; - while (!dtm->done() && !jtag->done() && !tsi->done() && - !tile->io_success && trace_count < max_cycles) { + do { tile->clock = 0; tile->eval(); #if VM_TRACE @@ -322,6 +338,13 @@ done_processing: #endif trace_count++; } + // for verilator multithreading. need to do 1 loop before checking if + // tsi exists, since tsi is created by verilated thread on the first + // serial_tick. + while ((!dtm || !dtm->done()) && + (!jtag || !jtag->done()) && + (!tsi || !tsi->done()) && + !tile->io_success && trace_count < max_cycles); #if VM_TRACE if (tfp) @@ -330,17 +353,17 @@ done_processing: fclose(vcdfile); #endif - if (dtm->exit_code()) + if (dtm && dtm->exit_code()) { fprintf(stderr, "*** FAILED *** via dtm (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count); ret = dtm->exit_code(); } - else if (tsi->exit_code()) + else if (tsi && tsi->exit_code()) { fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", tsi->exit_code(), random_seed, trace_count); ret = tsi->exit_code(); } - else if (jtag->exit_code()) + else if (jtag && jtag->exit_code()) { fprintf(stderr, "*** FAILED *** via jtag (code = %d, seed %d) after %ld cycles\n", jtag->exit_code(), random_seed, trace_count); ret = jtag->exit_code(); @@ -359,5 +382,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; + if (htif_argv) free(htif_argv); return ret; } diff --git a/scripts/numa_prefix b/scripts/numa_prefix new file mode 100755 index 00000000..af2d2eb1 --- /dev/null +++ b/scripts/numa_prefix @@ -0,0 +1,67 @@ +#!/usr/bin/env perl + +#============================================================================ +# - really simple script, which just prints out the numactl cmd to +# prefix before your actual command. it determines this based on free +# memory size attached to every node. +# - when you run this on a machine without `numactl`, the output is empty, +# so `$(numa_prefix) ` turns in to ` `. +# - when the machine has `numactl` installed, regardless of the socket-count +# on the machine, the resulting command is: +# `numactl -m -C -- ` +# - example output from `numactl -H` on a 2 socket machine: +# available: 2 nodes (0-1) +# node 0 cpus: 0 2 4 6 8 10 12 14 16 18 20 22 +# node 0 size: 131026 MB +# node 0 free: 7934 MB +# node 1 cpus: 1 3 5 7 9 11 13 15 17 19 21 23 +# node 1 size: 65536 MB +# node 1 free: 429 MB +# node distances: +# node 0 1 +# 0: 10 20 +# 1: 20 10 +#============================================================================ + +use strict; +use warnings; + +my $path = `which numactl`; +if(length($path) > 0) { + my ($head_line, @rest) = map {chomp; $_} `numactl -H`; + + if($head_line =~ /available: (\d+) nodes/) { + my $node_count = $1; + my $best_node_id = undef + my $best_cpus = undef; + my $best_free_size = undef; + + # loop through available nodes, selecting the node with the most free mem + foreach my $num (1..$node_count) { + my $cpus_line = shift(@rest); + my $mem_size_line = shift(@rest); + my $mem_free_line = shift(@rest); + + if($cpus_line =~ /node (\d+) cpus: (\d.*\d)$/) { + my ($node_id, $cpus) = ($1, $2); + $cpus =~ s/\s+/,/g; + + if($mem_free_line =~ /node $node_id free: (\d+) \S+$/) { + my $free_size = $1; + if(!defined($best_free_size) || ($free_size > $best_free_size)) { + $best_node_id = $node_id; + $best_cpus = $cpus; + $best_free_size = $free_size; + } + } else { + die("malformed mem-free line: $mem_free_line\n"); + } + } else { + die("malformed cpus line: $cpus_line\n"); + } + } + print("numactl -m $best_node_id -C $best_cpus --"); + } else { + die("malformed head line: $head_line\n"); + } +} diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 295729b7..5ce75683 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -70,6 +70,9 @@ RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\ $(if $(filter $(VERILATOR_PROFILE),threads),\ --prof-threads,)) +VERILATOR_THREADS ?= 1 +RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all + VERILATOR_FST_MODE ?= 0 TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\ --trace,--trace-fst --trace-threads 1) @@ -122,6 +125,7 @@ PREPROC_DEFINES := \ VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ + $(RUNTIME_THREADS) \ $(VERILATOR_OPT_FLAGS) \ $(PLATFORM_OPTS) \ -Wno-fatal \ @@ -157,7 +161,6 @@ VERILATOR_CXXFLAGS = \ VERILATOR_LDFLAGS = \ $(LDFLAGS) \ - $(RUNTIME_PROFILING_CFLAGS) \ -L$(RISCV)/lib \ -Wl,-rpath,$(RISCV)/lib \ -L$(sim_dir) \ @@ -219,7 +222,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rules From 446631543b1ae93db282b20de4076d0ede54f4dd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Aug 2020 11:20:45 -0700 Subject: [PATCH 132/457] Use TRACING_OPTS in debug Verilator --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 5ce75683..f945cb01 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -203,7 +203,7 @@ $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) - $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### From c9791ccbdfda3bd9a688026a2f659422a6d09fc7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Aug 2020 12:06:18 -0700 Subject: [PATCH 133/457] Update docs | Revert/Update emulator.cc --- docs/Simulation/Software-RTL-Simulation.rst | 7 +- .../src/main/resources/csrc/emulator.cc | 69 +++++++++++-------- 2 files changed, 43 insertions(+), 33 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 6d7fb2b8..32164f6d 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -191,8 +191,9 @@ When building the verilator simulator there are some additional options: .. code-block:: shell - make VERILATOR_THREADS=8 + make VERILATOR_THREADS=8 NUMACTL=1 The ``VERILATOR_THREADS=`` option enables the compiled Verilator simulator to use ```` parallel threads. -On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``numactl``. -You can also just use the ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator- ``. +On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``NUMACTL=1`` to enable ``numactl``. +By enabling this, you will use CHipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator- ``. +Note that both these flags are mutually exclusive, you can use either independently (though it makes sense to use ``NUMACTL`` just with ``VERILATOR_THREADS=8`` during a Verilator simulation). diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index dc8827a9..e92c4688 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -41,7 +41,6 @@ extern tsi_t* tsi; extern dtm_t* dtm; extern remote_bitbang_t * jtag; -extern int dramsim; static uint64_t trace_count = 0; bool verbose = false; @@ -129,37 +128,38 @@ int main(int argc, char** argv) uint64_t max_cycles = -1; int ret = 0; bool print_cycles = false; - // Port numbers are 16 bit unsigned integers. + // Port numbers are 16 bit unsigned integers. uint16_t rbb_port = 0; #if VM_TRACE - const char* vcdfile_name = NULL; + const char* vcdfile_name = NULL; FILE * vcdfile = NULL; uint64_t start = 0; #endif int verilog_plusargs_legal = 1; - dramsim = 0; + opterr = 1; while (1) { static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"dramsim", no_argument, 0, 'D' }, + {"cycle-count", no_argument, 0, 'c' }, + {"help", no_argument, 0, 'h' }, + {"max-cycles", required_argument, 0, 'm' }, + {"seed", required_argument, 0, 's' }, + {"rbb-port", required_argument, 0, 'r' }, + {"verbose", no_argument, 0, 'V' }, + {"permissive", no_argument, 0, 'p' }, + {"permissive-off", no_argument, 0, 'o' }, #if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, + {"vcd", required_argument, 0, 'v' }, + {"dump-start", required_argument, 0, 'x' }, #endif HTIF_LONG_OPTIONS }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:po", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:Vpo", long_options, &option_index); #endif if (c == -1) break; retry: @@ -172,7 +172,8 @@ int main(int argc, char** argv) case 's': random_seed = atoi(optarg); break; case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; - case 'D': dramsim = 1; break; + case 'p': opterr = 0; break; + case 'o': opterr = 1; break; #if VM_TRACE case 'v': { vcdfile_name = optarg; @@ -207,8 +208,10 @@ int main(int argc, char** argv) #endif else if (arg.substr(0, 12) == "+cycle-count") c = 'c'; - else if (arg == "+dramsim") - c = 'D'; + else if (arg == "+permissive") + c = 'p'; + else if (arg == "+permissive-off") + c = 'o'; // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { @@ -240,9 +243,13 @@ int main(int argc, char** argv) } htif_option++; } - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; + if(opterr) { + std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" + << arg << "\"\n"; + c = '?'; + } else { + c = 'p'; + } } goto retry; } @@ -264,10 +271,10 @@ done_processing: usage(argv[0]); return 1; } - htif_argc = 1 + argc - optind; - htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); - htif_argv[0] = argv[0]; - for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; + + // set argc/v in vpi_get_vlog_info + htif_argc = argc; + htif_argv = argv; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -293,6 +300,9 @@ done_processing: } #endif // VM_TRACE + // RocketChip currently only supports RBB port 0, so this needs to stay here + jtag = new remote_bitbang_t(rbb_port); + signal(SIGTERM, handle_sigterm); bool dump; @@ -339,10 +349,10 @@ done_processing: trace_count++; } // for verilator multithreading. need to do 1 loop before checking if - // tsi exists, since tsi is created by verilated thread on the first - // serial_tick. - while ((!dtm || !dtm->done()) && - (!jtag || !jtag->done()) && + // tsi exists, since tsi is created by verilated thread on the first + // serial_tick. + while ((!dtm || !dtm->done()) && + (!jtag || !jtag->done()) && (!tsi || !tsi->done()) && !tile->io_success && trace_count < max_cycles); @@ -382,6 +392,5 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) free(htif_argv); return ret; } From 2168813da018f52a8781ee3e0e851bea5207a597 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Aug 2020 13:56:14 -0700 Subject: [PATCH 134/457] Add help string | Fix emulator CC to not conflict with --vpi --- .../src/main/resources/csrc/emulator.cc | 18 ------------------ sims/verilator/Makefile | 1 + 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index e92c4688..5e0ea38b 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -20,8 +20,6 @@ #include #include #include -// needed for s_vpi_vlog_info, which is needed for multithreading -#include // For option parsing, which is split across this file, Verilog, and // FESVR's HTIF, a few external files must be pulled in. The list of @@ -56,18 +54,6 @@ double sc_time_stamp() return trace_count; } -// need to pull htif_argc/htif_argv out here so the thread that calls tick() -// for the HTIF device can initialize properly with the cmdline args. this -// was pulled out here for multithreading to work -static int htif_argc; -static char **htif_argv = NULL; -extern "C" int vpi_get_vlog_info(s_vpi_vlog_info *vlog_info_s) -{ - vlog_info_s->argc = htif_argc; - vlog_info_s->argv = htif_argv; - return 1; -} - static void usage(const char * program_name) { printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n", @@ -272,10 +258,6 @@ done_processing: return 1; } - // set argc/v in vpi_get_vlog_info - htif_argc = argc; - htif_argv = argv; - if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index f945cb01..3cc7c18b 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -53,6 +53,7 @@ HELP_COMPILATION_VARIABLES += \ " VERILATOR_PROFILE = 'none' if no verilator profiling (default)" \ " 'all' if full verilator runtime profiling" \ " 'threads' if runtime thread profiling only" \ +" VERILATOR_THREADS = how many threads the simulator will use (default 1)" \ " VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" ######################################################################################### From fa97359516670693e2c9c1fb1c339631a2c6bbae Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Aug 2020 16:14:07 -0700 Subject: [PATCH 135/457] Cleanup VCS's csrc directory | Fix small doc typo --- docs/Simulation/Software-RTL-Simulation.rst | 2 +- sims/vcs/Makefile | 18 +++++++++++++----- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 32164f6d..d952c62c 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -195,5 +195,5 @@ When building the verilator simulator there are some additional options: The ``VERILATOR_THREADS=`` option enables the compiled Verilator simulator to use ```` parallel threads. On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``NUMACTL=1`` to enable ``numactl``. -By enabling this, you will use CHipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator- ``. +By enabling this, you will use Chipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator- ``. Note that both these flags are mutually exclusive, you can use either independently (though it makes sense to use ``NUMACTL`` just with ``VERILATOR_THREADS=8`` during a Verilator simulation). diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index a2896380..2c44ae6e 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -43,14 +43,22 @@ VCS = vcs -full64 VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) +######################################################################################### +# vcs build paths +######################################################################################### +model_dir = $(build_dir)/$(long_name) +model_dir_debug = $(build_dir)/$(long_name).debug + ######################################################################################### # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ + rm -rf $(model_dir) + $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir) $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ + rm -rf $(model_dir_debug) + $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir_debug) \ +define+DEBUG ######################################################################################### @@ -65,10 +73,10 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean-sim clean-sim-debug clean: - rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h + rm -rf $(gen_dir) $(sim_prefix)-* ucli.key clean-sim: - rm -rf csrc/ $(sim) ucli.key vc_hdrs.h + rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key clean-sim-debug: - rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h + rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key From 06747e6cffa6beec1b573d7da28735041e7def55 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Aug 2020 17:27:50 -0700 Subject: [PATCH 136/457] Dedup simulation flags --- sims/common-sim-flags.mk | 24 ++++++++++++++++++++++++ sims/verilator/Makefile | 24 ++++-------------------- vcs.mk | 21 +++------------------ 3 files changed, 31 insertions(+), 38 deletions(-) create mode 100644 sims/common-sim-flags.mk diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk new file mode 100644 index 00000000..1c73a510 --- /dev/null +++ b/sims/common-sim-flags.mk @@ -0,0 +1,24 @@ +#---------------------------------------------------------------------------------------- +# common gcc configuration/optimization +#---------------------------------------------------------------------------------------- +SIM_OPT_CXXFLAGS := -O3 + +SIM_CXXFLAGS = \ + $(CXXFLAGS) \ + $(SIM_OPT_CXXFLAGS) \ + -std=c++11 \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -I$(build_dir) \ + $(EXTRA_SIM_CXXFLAGS) + +SIM_LDFLAGS = \ + $(LDFLAGS) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -lpthread \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3cc7c18b..211b5676 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -141,35 +141,19 @@ VERILATOR_NONCC_OPTS = \ #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- -# -flto slows down compilation on small-memory and breaks on firesim-manager -CXX_OPT_FLAGS := -O3 +include $(base_dir)/sims/common-sim-flags.mk VERILATOR_CXXFLAGS = \ - $(CXXFLAGS) \ + $(SIM_CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ $(TRACING_CFLAGS) \ - $(CXX_OPT_FLAGS) \ - -std=c++11 \ -D__STDC_FORMAT_MACROS \ -DTEST_HARNESS=V$(VLOG_MODEL) \ -DVERILATOR \ - -I$(RISCV)/include \ - -I$(dramsim_dir) \ - -I$(build_dir) \ -include $(build_dir)/$(long_name).plusArgs \ - -include $(build_dir)/verilator.h \ - $(EXTRA_SIM_CXXFLAGS) + -include $(build_dir)/verilator.h -VERILATOR_LDFLAGS = \ - $(LDFLAGS) \ - -L$(RISCV)/lib \ - -Wl,-rpath,$(RISCV)/lib \ - -L$(sim_dir) \ - -L$(dramsim_dir) \ - -lfesvr \ - -lpthread \ - -ldramsim \ - $(EXTRA_SIM_LDFLAGS) +VERILATOR_LDFLAGS = $(SIM_LDFLAGS) VERILATOR_CC_OPTS = \ -CFLAGS "$(VERILATOR_CXXFLAGS)" \ diff --git a/vcs.mk b/vcs.mk index a282aa44..c3ba6da6 100644 --- a/vcs.mk +++ b/vcs.mk @@ -14,25 +14,10 @@ RESET_DELAY ?= 777.7 #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- -CXX_OPT_FLAGS := -O3 +include $(base_dir)/sims/common-sim-flags.mk -VCS_CXXFLAGS = \ - $(CXXFLAGS) \ - $(CXX_OPT_FLAGS) \ - -I$(RISCV)/include \ - -I$(dramsim_dir) \ - -std=c++11 \ - $(EXTRA_SIM_CXXFLAGS) - -VCS_LDFLAGS = \ - $(LDFLAGS) \ - -L$(RISCV)/lib \ - -Wl,-rpath,$(RISCV)/lib \ - -L$(sim_dir) \ - -L$(dramsim_dir) \ - -lfesvr \ - -ldramsim \ - $(EXTRA_SIM_LDFLAGS) +VCS_CXXFLAGS = $(SIM_CXXFLAGS) +VCS_LDFLAGS = $(SIM_LDFLAGS) # vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate) VCS_CC_OPTS = \ From 03457bf9348b6c5a6b423c55e953bf245c4c5d68 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Aug 2020 17:44:29 -0700 Subject: [PATCH 137/457] Remove unneeded libpthread in simulations --- sims/common-sim-flags.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 1c73a510..766dd0d3 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -19,6 +19,5 @@ SIM_LDFLAGS = \ -L$(sim_dir) \ -L$(dramsim_dir) \ -lfesvr \ - -lpthread \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) From 543136db8c639873de65242ab1b70b1a3307bf1f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 24 Aug 2020 11:04:28 -0700 Subject: [PATCH 138/457] Port numa_prefix to python2 [ci skip] --- scripts/numa_prefix | 85 +++++++++++++++++++++++++-------------------- 1 file changed, 47 insertions(+), 38 deletions(-) diff --git a/scripts/numa_prefix b/scripts/numa_prefix index af2d2eb1..e4cc2aec 100755 --- a/scripts/numa_prefix +++ b/scripts/numa_prefix @@ -1,4 +1,4 @@ -#!/usr/bin/env perl +#!/usr/bin/env python #============================================================================ # - really simple script, which just prints out the numactl cmd to @@ -23,45 +23,54 @@ # 1: 20 10 #============================================================================ -use strict; -use warnings; +import subprocess +import re +import sys -my $path = `which numactl`; -if(length($path) > 0) { - my ($head_line, @rest) = map {chomp; $_} `numactl -H`; +which_proc = subprocess.Popen(["which", "numactl"], stdout=subprocess.PIPE) +out, err = which_proc.communicate() - if($head_line =~ /available: (\d+) nodes/) { - my $node_count = $1; - my $best_node_id = undef - my $best_cpus = undef; - my $best_free_size = undef; +if out != "": + numactl_proc = subprocess.Popen(["numactl", "-H"], stdout=subprocess.PIPE) + out, err = numactl_proc.communicate() - # loop through available nodes, selecting the node with the most free mem - foreach my $num (1..$node_count) { - my $cpus_line = shift(@rest); - my $mem_size_line = shift(@rest); - my $mem_free_line = shift(@rest); + lines = out.split("\n") + line_idx = 0 - if($cpus_line =~ /node (\d+) cpus: (\d.*\d)$/) { - my ($node_id, $cpus) = ($1, $2); - $cpus =~ s/\s+/,/g; + head_line = lines[line_idx] + line_idx += 1 + node_match = re.match(r"^ *available: +(\d+) nodes", head_line) + if node_match: + avail_nodes = node_match.group(1) + best_node_id = "" + best_cpus = "" + best_free_size = 0 - if($mem_free_line =~ /node $node_id free: (\d+) \S+$/) { - my $free_size = $1; - if(!defined($best_free_size) || ($free_size > $best_free_size)) { - $best_node_id = $node_id; - $best_cpus = $cpus; - $best_free_size = $free_size; - } - } else { - die("malformed mem-free line: $mem_free_line\n"); - } - } else { - die("malformed cpus line: $cpus_line\n"); - } - } - print("numactl -m $best_node_id -C $best_cpus --"); - } else { - die("malformed head line: $head_line\n"); - } -} + # loop through available nodes, selecting the node with the most free mem + for i in avail_nodes: + cpu_line = lines[line_idx] + mem_size_line = lines[line_idx + 1] + mem_free_line = lines[line_idx + 2] + line_idx += 3 + + cpu_match = re.match(r"^ *node (\d+) cpus: (\d.*\d)$", cpu_line) + if cpu_match: + node_id = cpu_match.group(1) + cpus = cpu_match.group(2).replace(" ", ",") + + mem_free_match = re.match(r"^ *node " + node_id + " free: (\d+) \S+$", mem_free_line) + if mem_free_match: + free_size = mem_free_match.group(1) + if int(free_size) > int(best_free_size): + best_node_id = node_id + best_cpus = cpus + best_free_size = free_size + else: + sys.exit("[ERROR] Malformed mem free line: " + mem_free_line) + + else: + sys.exit("[ERROR] Malformed cpus line: " + cpu_line) + + sys.stdout.write("numactl -m " + best_node_id + " -C " + best_cpus + " --") + else: + sys.exit("[ERROR] Malformed head line: " + head_line) From f8a0757eee51404652b2a0432e780b88ff795b4c Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 24 Aug 2020 11:24:28 -0700 Subject: [PATCH 139/457] Remove extra mem_size line [ci skip] --- scripts/numa_prefix | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/numa_prefix b/scripts/numa_prefix index e4cc2aec..b9521cbd 100755 --- a/scripts/numa_prefix +++ b/scripts/numa_prefix @@ -49,7 +49,7 @@ if out != "": # loop through available nodes, selecting the node with the most free mem for i in avail_nodes: cpu_line = lines[line_idx] - mem_size_line = lines[line_idx + 1] + # mem. size unused. skip and use mem. free mem_free_line = lines[line_idx + 2] line_idx += 3 From e275a4589090d924e4c829c927a4fe0b87eb7335 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 24 Aug 2020 17:51:48 -0700 Subject: [PATCH 140/457] Address PR comments --- .../chipyard/src/main/scala/ChipTop.scala | 4 +- .../chipyard/src/main/scala/Clocks.scala | 12 +++--- .../src/main/scala/ConfigFragments.scala | 7 ++-- .../chipyard/src/main/scala/IOBinders.scala | 39 ++++++++++--------- .../chipyard/src/main/scala/TestHarness.scala | 12 +++--- .../src/main/scala/config/RocketConfigs.scala | 5 --- .../firechip/src/main/scala/FireSim.scala | 16 ++++---- vlsi/Makefile | 2 +- 8 files changed, 49 insertions(+), 48 deletions(-) diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index f7b94d2b..cf71987b 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -19,7 +19,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) /** * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, * named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock, - * is aggregated into the clockGroupNode. The parameterized functions controlled by ChipyardClockKey and GlobalResetSchemeKey + * is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey * drive clock and reset generation */ @@ -36,7 +36,7 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) // Generate Clocks and Reset - p(ChipyardClockKey)(this) + p(ClockingSchemeKey)(this) // NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children // of ChipTop (ex: ClockGroup) do not receive clock or reset. diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 7f181bb5..3fa349b5 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -69,7 +69,7 @@ object GenerateReset { } reset_io.suggestName("reset") chiptop.iocells ++= resetIOCell - chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { reset_io := th.dutReset Nil }) @@ -78,11 +78,11 @@ object GenerateReset { } -case object ChipyardClockKey extends Field[ChipTop => Unit](ClockDrivers.harnessClock) +case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.harnessClock) -object ClockDrivers { +object ClockingSchemeGenerators { // A simple clock provider, for testing val harnessClock: ChipTop => Unit = { chiptop => implicit val p = chiptop.p @@ -120,7 +120,7 @@ object ClockDrivers { } }} - chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { clock_io := th.harnessClock Nil }) @@ -132,6 +132,8 @@ object ClockDrivers { val harnessDividedClock: ChipTop => Unit = { chiptop => implicit val p = chiptop.p + require(false, "Divided clock is broken until we fix passing onchip clocks to TestHarness objects") + val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) chiptop.implicitClockSinkNode := implicitClockSourceNode @@ -166,7 +168,7 @@ object ClockDrivers { } }} - chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { clock_io := th.harnessClock Nil }) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 704b849a..6336c05a 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -26,7 +26,7 @@ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey, TestSuitesKey, TestSuiteHelper} +import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingSchemeKey, TestSuitesKey, TestSuiteHelper} // ----------------------- @@ -98,7 +98,7 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config( case MultiRoCCKey => { up(MultiRoCCKey, site) ++ harts.distinct.map{ i => (i -> Seq((p: Parameters) => { - val hwacha = LazyModule(new Hwacha()(p)).suggestName("hwacha") + val hwacha = LazyModule(new Hwacha()(p)) hwacha })) } @@ -160,5 +160,6 @@ class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { }) class WithTileDividedClock extends Config((site, here, up) => { - case ChipyardClockKey => ClockDrivers.harnessDividedClock + case ClockingSchemeKey => ClockingSchemeGenerators.harnessDividedClock }) + diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 84ef5269..6438801a 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -41,7 +41,7 @@ import scala.reflect.{ClassTag} // DOC include start: IOBinders // This type describes a function callable on the TestHarness instance. Its return type is unused. -type TestHarnessFunction = (chipyard.HasHarnessUtils) => Seq[Any] +type TestHarnessFunction = (chipyard.HasHarnessSignalReferences) => Seq[Any] // IOBinders will return a Seq of this tuple, which contains three fields: // 1. A Seq containing all IO ports created by the IOBinder function // 2. A Seq containing all IO cell modules created by the IOBinder function @@ -228,7 +228,7 @@ object AddIOCells { class WithGPIOTiedOff extends OverrideIOBinder({ (system: HasPeripheryGPIOModuleImp) => { val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) - val harnessFn = (th: HasHarnessUtils) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } + val harnessFn = (th: HasHarnessSignalReferences) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) } }) @@ -237,7 +237,7 @@ class WithGPIOTiedOff extends OverrideIOBinder({ class WithUARTAdapter extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { val (ports, ioCells2d) = AddIOCells.uart(system.uart) - val harnessFn = (th: HasHarnessUtils) => { UARTAdapter.connect(ports)(system.p); Nil } + val harnessFn = (th: HasHarnessSignalReferences) => { UARTAdapter.connect(ports)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) } }) @@ -245,7 +245,7 @@ class WithUARTAdapter extends OverrideIOBinder({ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ (system: HasPeripherySPIFlashModuleImp) => { val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") - val harnessFn = (th: HasHarnessUtils) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p); Nil } + val harnessFn = (th: HasHarnessSignalReferences) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) } }) @@ -253,7 +253,7 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ class WithSimBlockDevice extends OverrideIOBinder({ (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { // TODO: Using harness clock/reset will be incorrect when systemClock =/= harnessClock SimBlockDevice.connect(th.harnessClock, th.harnessReset.asBool, Some(port))(system.p) Nil @@ -265,7 +265,7 @@ class WithSimBlockDevice extends OverrideIOBinder({ class WithBlockDeviceModel extends OverrideIOBinder({ (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { BlockDeviceModel.connect(Some(port))(system.p) Nil } @@ -288,7 +288,7 @@ class WithSimAXIMem extends OverrideIOBinder({ val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") // TODO: we are inlining the connectMem method of SimAXIMem because // it takes in a dut rather than seq of axi4 ports - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { peiTuples.map { case (port, edge, ios) => val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) Module(mem.module).suggestName("mem") @@ -305,7 +305,7 @@ class WithBlackBoxSimMem extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort) => { implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { peiTuples.map { case (port, edge, ios) => val memSize = p(ExtMem).get.master.size val lineSize = p(CacheBlockBytes) @@ -325,7 +325,7 @@ class WithSimAXIMMIO extends OverrideIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem") - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)) Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") @@ -345,7 +345,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ (system: HasExtInterruptsModuleImp) => { val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) port.suggestName("interrupts") - val harnessFn = (th: HasHarnessUtils) => { port := 0.U; Nil } + val harnessFn = (th: HasHarnessSignalReferences) => { port := 0.U; Nil } Seq((Seq(port), ioCells, Some(harnessFn))) } }) @@ -353,7 +353,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ class WithTieOffL2FBusAXI extends OverrideIOBinder({ (system: CanHaveSlaveAXI4Port) => { val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus") - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => port := DontCare // tieoff doesn't completely tie-off, for some reason port.tieoff() @@ -364,18 +364,19 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ } }) +// TODO we need to rethink what "Tie-off-debug" means. The current system punches out +// excessive IOs. class WithTiedOffDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) // tieoffDebug doesn't actually tie everything off :/ debugPortOpt.foreach { d => - // TODO: Using harness clock/reset will be incorrect when systemClock =/= harnessClock d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.harnessClock }) d.dmactiveAck := DontCare - d.clock := th.harnessClock + d.clock := th.harnessClock // TODO fix: This should be driven from within the chip } Nil } @@ -383,11 +384,13 @@ class WithTiedOffDebug extends OverrideIOBinder({ } }) +// TODO we need to rethink what this does. The current system punches out excessive IOs. +// Some of the debug clock/reset should be driven from on-chip class WithSimDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { val dtm_success = Wire(Bool()) Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.harnessClock, th.harnessReset.asBool, dtm_success)(system.p) when (dtm_success) { th.success := true.B } @@ -401,7 +404,7 @@ class WithSimDebug extends OverrideIOBinder({ class WithTiedOffSerial extends OverrideIOBinder({ (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { SerialAdapter.tieoff(port) Nil } @@ -412,7 +415,7 @@ class WithTiedOffSerial extends OverrideIOBinder({ class WithSimSerial extends OverrideIOBinder({ (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) - val harnessFn = (th: HasHarnessUtils) => { + val harnessFn = (th: HasHarnessSignalReferences) => { val ser_success = SerialAdapter.connectSimSerial(port, th.harnessClock, th.harnessReset) when (ser_success) { th.success := true.B } Nil @@ -425,7 +428,7 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ (system: TraceGenSystemModuleImp) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") - val harnessFn = (th: HasHarnessUtils) => { when (successPort) { th.success := true.B }; Nil } + val harnessFn = (th: HasHarnessSignalReferences) => { when (successPort) { th.success := true.B }; Nil } Seq((Seq(successPort), ioCells, Some(harnessFn))) } }) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 70802783..b296e328 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -16,14 +16,14 @@ trait HasTestHarnessFunctions { val harnessFunctions: Seq[TestHarnessFunction] } -trait HasHarnessUtils { - val harnessClock: Clock - val harnessReset: Reset - val dutReset: Reset - val success: Bool +trait HasHarnessSignalReferences { + def harnessClock: Clock + def harnessReset: Reset + def dutReset: Reset + def success: Bool } -class TestHarness(implicit val p: Parameters) extends Module with HasHarnessUtils { +class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSignalReferences { val io = IO(new Bundle { val success = Output(Bool()) }) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e0587454..07033609 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -194,8 +194,3 @@ class DividedClockRocketConfig extends Config( new chipyard.config.AbstractConfig) -class TestClockRocketConfig extends Config( - //new chipyard.config.WithTileMultiClock ++ // Put the Tile on its own clock domain - new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(8, 3) ++ // Add rational crossings between RocketTile and uncore - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index e807e840..158674a0 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} -import chipyard.{BuildSystem, BuildTop, HasHarnessUtils, ChipyardSubsystem, ChipyardClockKey, ChipTop} +import chipyard.{BuildSystem, BuildTop, HasHarnessSignalReferences, ChipyardSubsystem, ClockingSchemeKey, ChipTop} import chipyard.iobinders.{IOBinders} // Determines the number of times to instantiate the DUT in the harness. @@ -43,7 +43,7 @@ object NodeIdx { } class WithFireSimSimpleClocks extends Config((site, here, up) => { - case ChipyardClockKey => { chiptop: ChipTop => + case ClockingSchemeKey => { chiptop: ChipTop => implicit val p = chiptop.p val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) @@ -75,7 +75,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { } }} - chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { clock := th.harnessClock reset := th.harnessReset Nil @@ -86,7 +86,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) - case ChipyardClockKey => { chiptop: ChipTop => + case ClockingSchemeKey => { chiptop: ChipTop => implicit val p = chiptop.p val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) @@ -125,7 +125,7 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi } }} - chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { uncore_clock := th.harnessClock reset := th.harnessReset th match { @@ -138,15 +138,15 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi } }) -class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessUtils { +class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSignalReferences { freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) val harnessClock = clockBridge.io.clocks.head // This is the reference clock val additionalClocks = clockBridge.io.clocks.tail val harnessReset = WireInit(false.B) val peekPokeBridge = PeekPokeBridge(harnessClock, harnessReset) - val dutReset = false.B // unused (if used, its a bug) - val success = false.B // unused (if used, its a bug) + def dutReset = { require(false, "dutReset should not be used in Firesim"); false.B } + def success = { require(false, "success should not be used in Firesim"); false.B } // Instantiate multiple instances of the DUT to implement supernode for (i <- 0 until p(NumNodes)) { diff --git a/vlsi/Makefile b/vlsi/Makefile index a9e3d3a5..da9f2193 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -34,7 +34,7 @@ INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ example-asap7.yml) HAMMER_EXEC ?= example-vlsi VLSI_TOP ?= $(TOP) -VLSI_HARNESS_DUT_NAME ?= dut +VLSI_HARNESS_DUT_NAME ?= chiptop VLSI_OBJ_DIR ?= $(vlsi_dir)/build ifneq ($(CUSTOM_VLOG),) OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) From 5a25ee5206d44a7794aacf4540088fec52248dfa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 27 Aug 2020 08:08:08 +0000 Subject: [PATCH 141/457] Bump Firesim for new AGFIs --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index b13e7529..05edd6be 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b13e75296c44b1f3fa987d15df6a595668842dfe +Subproject commit 05edd6be8c0464ea53a664a2164d3eba6a7f62aa From 239b6b6e095aff7075b25c91c45f35a9bb9a113f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 27 Aug 2020 13:00:43 -0700 Subject: [PATCH 142/457] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index add28f0b..1e7373f6 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit add28f0b61dd337c1d4fa36b48569166743cb1d5 +Subproject commit 1e7373f6398c198e2dee2bcf692917ec2ac21b53 From 933df4e05c284a127a743f6fc81865939bfaee49 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 27 Aug 2020 23:27:24 -0700 Subject: [PATCH 143/457] Whitelist firemarshal's dev branch for commit-on-master check --- .circleci/check-commit.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 98c770ad..7824b943 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -82,7 +82,12 @@ search submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017") dir="software" -branches=("master") +if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +then + branches=("master") +else + branches=("master" "dev") +fi search submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "firrtl-interpreter" "torture" "treadle") From 27b78f4de21d390cbe6deb24cc2743a63b4a10ca Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 27 Aug 2020 23:48:01 -0700 Subject: [PATCH 144/457] Only punch realistic subset of DebugIO through chiptop --- .../chipyard/src/main/scala/IOBinders.scala | 131 ++++++++++++------ 1 file changed, 90 insertions(+), 41 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 6438801a..1c81f535 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -7,6 +7,7 @@ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} @@ -163,30 +164,65 @@ object AddIOCells { } /** - * Add IO cells to a debug module and name the IO ports. - * @param psd A PSDIO bundle + * Add IO cells to a debug module and name the IO ports, for debug IO which must go off-chip + * For on-chip debug IO, drive them appropriately + * @param system A BaseSubsystem that might have a debug module * @param resetctrlOpt An optional ResetCtrlIO bundle * @param debugOpt An optional DebugIO bundle - * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references) + * @return Returns a tuple2 of (Generated debug io ports, Generated IOCells) */ - def debug(psd: PSDIO, resetctrlOpt: Option[ResetCtrlIO], debugOpt: Option[DebugIO])(implicit p: Parameters): - (PSDIO, Option[ResetCtrlIO], Option[DebugIO], Seq[IOCell]) = { - val (psdPort, psdIOs) = IOCell.generateIOFromSignal( - psd, Some("iocell_psd"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) - val debugTuple = debugOpt.map(d => - IOCell.generateIOFromSignal(d, Some("iocell_debug"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)) - val debugPortOpt: Option[DebugIO] = debugTuple.map(_._1) - val debugIOs: Seq[IOCell] = debugTuple.map(_._2).toSeq.flatten - debugPortOpt.foreach(_.suggestName("debug")) + def debug(system: HasPeripheryDebugModuleImp)(implicit p: Parameters): (Seq[Bundle], Seq[IOCell]) = { + system.debug.map { debug => - val resetctrlTuple = resetctrlOpt.map(d => - IOCell.generateIOFromSignal(d, Some("iocell_resetctrl"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)) - val resetctrlPortOpt: Option[ResetCtrlIO] = resetctrlTuple.map(_._1) - val resetctrlIOs: Seq[IOCell] = resetctrlTuple.map(_._2).toSeq.flatten - resetctrlPortOpt.foreach(_.suggestName("resetctrl")) + // We never use the PSDIO, so tie it off on-chip + system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } - psdPort.suggestName("psd") - (psdPort, resetctrlPortOpt, debugPortOpt, psdIOs ++ debugIOs ++ resetctrlIOs) + // Set resetCtrlOpt with the system reset + system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := system.reset.asBool } } + + system.debug.map { d => + // Tie off extTrigger + d.extTrigger.foreach { t => + t.in.req := false.B + t.out.ack := t.out.req + } + + // Tie off disableDebug + d.disableDebug.foreach { d => d := false.B } + + // Drive JTAG on-chip IOs + d.systemjtag.map { j => + j.reset := system.reset + j.mfr_id := system.p(JtagDTMKey).idcodeManufId.U(11.W) + j.part_number := system.p(JtagDTMKey).idcodePartNum.U(16.W) + j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W) + } + } + + + // Connect DebugClockAndReset to system implicit clock. TODO this should use the clock of the bus the debug module is attached to + Debug.connectDebugClockAndReset(Some(debug), system.clock)(system.p) + + // Add IOCells for the DMI/JTAG/APB ports + + val dmiTuple = debug.clockeddmi.map { d => + IOCell.generateIOFromSignal(d, Some("iocell_dmi"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + } + dmiTuple.map(_._1).foreach(_.suggestName("dmi")) + + val jtagTuple = debug.systemjtag.map { j => + IOCell.generateIOFromSignal(j.jtag, Some("iocell_jtag"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + } + jtagTuple.map(_._1).foreach(_.suggestName("jtag")) + + val apbTuple = debug.apb.map { a => + IOCell.generateIOFromSignal(a, Some("iocell_apb"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + } + apbTuple.map(_._1).foreach(_.suggestName("apb")) + + val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq + (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq) + }.getOrElse((Nil, Nil)) } /** @@ -364,40 +400,53 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ } }) -// TODO we need to rethink what "Tie-off-debug" means. The current system punches out -// excessive IOs. -class WithTiedOffDebug extends OverrideIOBinder({ +class WithSimDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = - AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) + val (ports, iocells) = AddIOCells.debug(system)(system.p) val harnessFn = (th: HasHarnessSignalReferences) => { - Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) - // tieoffDebug doesn't actually tie everything off :/ - debugPortOpt.foreach { d => - d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.harnessClock }) - d.dmactiveAck := DontCare - d.clock := th.harnessClock // TODO fix: This should be driven from within the chip + val dtm_success = Wire(Bool()) + when (dtm_success) { th.success := true.B } + ports.map { + case d: ClockedDMIIO => + val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success) + case j: JTAGIO => + val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + case _ => + require(false, "We only support DMI or JTAG simulated debug connections") } Nil } - Seq((Seq(psdPort) ++ resetctrlOpt ++ debugPortOpt.toSeq, Nil, Some(harnessFn))) + Seq((ports, iocells, Some(harnessFn))) } }) -// TODO we need to rethink what this does. The current system punches out excessive IOs. -// Some of the debug clock/reset should be driven from on-chip -class WithSimDebug extends OverrideIOBinder({ +class WithTiedOffDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = - AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) + val (ports, iocells) = AddIOCells.debug(system)(system.p) val harnessFn = (th: HasHarnessSignalReferences) => { - val dtm_success = Wire(Bool()) - Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.harnessClock, th.harnessReset.asBool, dtm_success)(system.p) - when (dtm_success) { th.success := true.B } - th.dutReset := th.harnessReset.asBool | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B) + ports.map { + case d: ClockedDMIIO => + d.dmi.req.valid := false.B + d.dmi.req.bits := DontCare + d.dmi.resp.ready := true.B + d.dmiClock := th.harnessClock + d.dmiReset := th.harnessReset + case j: JTAGIO => + j.TCK := true.B.asClock + j.TMS := true.B + j.TDI := true.B + j.TRSTn.foreach { r => r := true.B } + case a: ClockedAPBBundle => + a.tieoff() + a.clock := false.B.asClock + a.reset := true.B.asAsyncReset + a.psel := false.B + a.penable := false.B + case _ => require(false) + } Nil } - Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) + Seq((ports, iocells, Some(harnessFn))) } }) From 5705f2645fac94a4cb416594d3cd4c85d5d56f7e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 28 Aug 2020 14:21:03 -0700 Subject: [PATCH 145/457] Bump toolchains --- toolchains/esp-tools/riscv-isa-sim | 2 +- toolchains/esp-tools/riscv-tests | 2 +- toolchains/riscv-tools/riscv-isa-sim | 2 +- toolchains/riscv-tools/riscv-openocd | 2 +- toolchains/riscv-tools/riscv-tests | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index a1ff6b03..aa332c6a 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit a1ff6b03f7f630a06327798238256973568e3837 +Subproject commit aa332c6a9a5ec77a9b97cdb4a1978ad394b17f1e diff --git a/toolchains/esp-tools/riscv-tests b/toolchains/esp-tools/riscv-tests index f1370d05..e116930c 160000 --- a/toolchains/esp-tools/riscv-tests +++ b/toolchains/esp-tools/riscv-tests @@ -1 +1 @@ -Subproject commit f1370d054389fc83974fc820985b5c51693b8f9d +Subproject commit e116930c7d4a30fc2a1378417089a089e9e4cad0 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 8d860c19..acd953af 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 8d860c190640e19e0f23a21d2479b4a36d13d342 +Subproject commit acd953afd2f52d64e2264c2c7c713dc0ad614406 diff --git a/toolchains/riscv-tools/riscv-openocd b/toolchains/riscv-tools/riscv-openocd index 7c82a7b9..cbb15587 160000 --- a/toolchains/riscv-tools/riscv-openocd +++ b/toolchains/riscv-tools/riscv-openocd @@ -1 +1 @@ -Subproject commit 7c82a7b9d5b7d8b71e0a66826705ec141db718c3 +Subproject commit cbb15587dc782ac8ade7ae252e7b760cfba4a178 diff --git a/toolchains/riscv-tools/riscv-tests b/toolchains/riscv-tools/riscv-tests index 249796ce..19bfdab4 160000 --- a/toolchains/riscv-tools/riscv-tests +++ b/toolchains/riscv-tools/riscv-tests @@ -1 +1 @@ -Subproject commit 249796cec94d75ff10ca034153e206a319e87158 +Subproject commit 19bfdab48c2a6da4a2c67d5779757da7b073811d From 20013d1348ba67f30c4dc6421f675516726e5a8e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 28 Aug 2020 14:21:24 -0700 Subject: [PATCH 146/457] Add DTM based bringup to regressions --- .circleci/config.yml | 38 +++++++++++++++++++------------------- .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 3 +++ 3 files changed, 23 insertions(+), 19 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 88a20f24..eac8504a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -199,6 +199,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-rocket" + prepare-chipyard-dmirocket: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-dmirocket" prepare-chipyard-sha3: executor: main-env steps: @@ -225,11 +230,6 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-boom" - prepare-rocketchip: - executor: main-env - steps: - - prepare-rtl: - project-key: "rocketchip" prepare-chipyard-blkdev: executor: main-env steps: @@ -297,6 +297,11 @@ jobs: steps: - run-tests: project-key: "chipyard-rocket" + chipyard-dmirocket-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-dmirocket" chipyard-sha3-run-tests: executor: main-env steps: @@ -323,11 +328,6 @@ jobs: steps: - run-tests: project-key: "chipyard-boom" - rocketchip-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "rocketchip" chipyard-hwacha-run-tests: executor: main-env steps: @@ -451,6 +451,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-dmirocket: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-sha3: requires: - install-riscv-toolchain @@ -476,11 +481,6 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-rocketchip: - requires: - - install-riscv-toolchain - - install-verilator - - prepare-chipyard-blkdev: requires: - install-riscv-toolchain @@ -547,6 +547,10 @@ workflows: requires: - prepare-chipyard-rocket + - chipyard-dmirocket-run-tests: + requires: + - prepare-chipyard-dmirocket + - chipyard-sha3-run-tests: requires: - prepare-chipyard-sha3 @@ -567,10 +571,6 @@ workflows: requires: - prepare-chipyard-boom - - rocketchip-run-tests: - requires: - - prepare-rocketchip - - chipyard-hwacha-run-tests: requires: - prepare-chipyard-hwacha diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 7cb8c1e2..7ffb1d3c 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -48,6 +48,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build strings declare -A mapping mapping["chipyard-rocket"]="" +mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 08b95e68..3e7b0285 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -32,6 +32,9 @@ case $1 in chipyard-rocket) run_bmark ${mapping[$1]} ;; + chipyard-dmirocket) + run_bmark ${mapping[$1]} + ;; chipyard-boom) run_bmark ${mapping[$1]} ;; From 17239c56f80aa6b2f9c2b8407a09ea22769da7ab Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 28 Aug 2020 14:36:09 -0700 Subject: [PATCH 147/457] Update AddIOCells.debug comment --- generators/chipyard/src/main/scala/IOBinders.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1c81f535..7f4daea3 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -167,8 +167,6 @@ object AddIOCells { * Add IO cells to a debug module and name the IO ports, for debug IO which must go off-chip * For on-chip debug IO, drive them appropriately * @param system A BaseSubsystem that might have a debug module - * @param resetctrlOpt An optional ResetCtrlIO bundle - * @param debugOpt An optional DebugIO bundle * @return Returns a tuple2 of (Generated debug io ports, Generated IOCells) */ def debug(system: HasPeripheryDebugModuleImp)(implicit p: Parameters): (Seq[Bundle], Seq[IOCell]) = { From 5c5af7bfaded370e08bede3514a557be5841f532 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 28 Aug 2020 18:37:47 -0700 Subject: [PATCH 148/457] Stage 3 passed all tests --- generators/riscv-sodor | 2 +- sims/verilator/Makefile | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 602ff66b..f2f87953 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 602ff66b0ef487df1d01c176eb3c62f8443b274e +Subproject commit f2f879533325964670c3086dfdfa1660e722551b diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3d676efd..531c2dd3 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -150,9 +150,8 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) ######################################################################################### .PRECIOUS: $(output_dir)/%.vpd %.vcd $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - rm -f $@.vcd && mkfifo $@.vcd - vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + touch $@.vpd + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v $@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule From c8448cc3e105c38eac54d1fc78545b8897cbad44 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 30 Aug 2020 18:10:52 -0700 Subject: [PATCH 149/457] Bore out a bus clock to drive DebugIO from ChipTop --- .../chipyard/src/main/scala/IOBinders.scala | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 7f4daea3..f13a6882 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -2,6 +2,7 @@ package chipyard package object iobinders { import chisel3._ +import chisel3.util.experimental.{BoringUtils} import chisel3.experimental.{Analog, IO} import freechips.rocketchip.config.{Field, Config, Parameters} @@ -171,12 +172,19 @@ object AddIOCells { */ def debug(system: HasPeripheryDebugModuleImp)(implicit p: Parameters): (Seq[Bundle], Seq[IOCell]) = { system.debug.map { debug => + val tlbus = system.outer.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere) + val debug_clock = Wire(Clock()).suggestName("debug_clock") + val debug_reset = Wire(Reset()).suggestName("debug_reset") + debug_clock := false.B.asClock + debug_reset := false.B + BoringUtils.bore(tlbus.module.clock, Seq(debug_clock)) + BoringUtils.bore(tlbus.module.reset, Seq(debug_reset)) // We never use the PSDIO, so tie it off on-chip system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } // Set resetCtrlOpt with the system reset - system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := system.reset.asBool } } + system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := debug_reset.asBool } } system.debug.map { d => // Tie off extTrigger @@ -190,7 +198,7 @@ object AddIOCells { // Drive JTAG on-chip IOs d.systemjtag.map { j => - j.reset := system.reset + j.reset := debug_reset j.mfr_id := system.p(JtagDTMKey).idcodeManufId.U(11.W) j.part_number := system.p(JtagDTMKey).idcodePartNum.U(16.W) j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W) @@ -199,7 +207,9 @@ object AddIOCells { // Connect DebugClockAndReset to system implicit clock. TODO this should use the clock of the bus the debug module is attached to - Debug.connectDebugClockAndReset(Some(debug), system.clock)(system.p) + + + Debug.connectDebugClockAndReset(Some(debug), debug_clock)(system.p) // Add IOCells for the DMI/JTAG/APB ports From bb1d0a10ae12299de5872e93fbc0b76d0fd0f71b Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 31 Aug 2020 18:00:40 -0700 Subject: [PATCH 150/457] Stage 3 (single port) passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index f2f87953..477f9a4e 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit f2f879533325964670c3086dfdfa1660e722551b +Subproject commit 477f9a4eb9209cfc8eaae2f8e9f80f951c057342 From a8834c77669e978658f24610e0743306bc4ce1cd Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 2 Sep 2020 12:48:44 -0700 Subject: [PATCH 151/457] First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build. --- .gitmodules | 3 + build.sbt | 7 + fpga/Makefile.e300artydevkit | 23 +++ fpga/bootrom/xip/Makefile | 45 ++++++ fpga/bootrom/xip/xip.S | 16 ++ fpga/common.mk | 119 +++++++++++++++ fpga/fpga-shells | 1 + fpga/src/main/scala/arty/Config.scala | 65 ++++++++ fpga/src/main/scala/arty/FPGAChip.scala | 193 ++++++++++++++++++++++++ fpga/src/main/scala/arty/Platform.scala | 178 ++++++++++++++++++++++ fpga/src/main/scala/arty/System.scala | 51 +++++++ 11 files changed, 701 insertions(+) create mode 100644 fpga/Makefile.e300artydevkit create mode 100644 fpga/bootrom/xip/Makefile create mode 100644 fpga/bootrom/xip/xip.S create mode 100644 fpga/common.mk create mode 160000 fpga/fpga-shells create mode 100644 fpga/src/main/scala/arty/Config.scala create mode 100644 fpga/src/main/scala/arty/FPGAChip.scala create mode 100644 fpga/src/main/scala/arty/Platform.scala create mode 100644 fpga/src/main/scala/arty/System.scala diff --git a/.gitmodules b/.gitmodules index aab9a8f7..ea3cb2c7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -128,3 +128,6 @@ [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/riscv-boom/dromajo.git +[submodule "fpga/fpga-shells"] + path = fpga/fpga-shells + url = git@github.com:sifive/fpga-shells.git diff --git a/build.sbt b/build.sbt index 5d642c1d..31bb3f88 100644 --- a/build.sbt +++ b/build.sbt @@ -217,3 +217,10 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testGrouping in Test := isolateAllTests( (definedTests in Test).value ), testOptions in Test += Tests.Argument("-oF") ) +lazy val fpgaShells = (project in file("./fpga/fpga-shells")) + .dependsOn(rocketchip, sifive_blocks) + .settings(commonSettings) + +lazy val freedomPlatforms = (project in file("./fpga")) + .dependsOn(chipyard, fpgaShells) + .settings(commonSettings) diff --git a/fpga/Makefile.e300artydevkit b/fpga/Makefile.e300artydevkit new file mode 100644 index 00000000..5f5c595b --- /dev/null +++ b/fpga/Makefile.e300artydevkit @@ -0,0 +1,23 @@ +# See LICENSE for license details. +base_dir=$(abspath ..) +BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit +FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx +MODEL := E300ArtyDevKitFPGAChip +PROJECT := sifive.freedom.everywhere.e300artydevkit +export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit +export CONFIG := E300ArtyDevKitConfig +export BOARD := arty +export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip + +rocketchip_dir := $(base_dir)/generators/rocket-chip +sifiveblocks_dir := $(base_dir)/generators/sifive-blocks +VSRCS := \ + $(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \ + $(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \ + $(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \ + $(sifiveblocks_dir)/vsrc/SRLatch.v \ + $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \ + $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \ + $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v + +include common.mk diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile new file mode 100644 index 00000000..57f94d49 --- /dev/null +++ b/fpga/bootrom/xip/Makefile @@ -0,0 +1,45 @@ +# RISCV environment variable must be set + +CC=$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy +CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g +LFLAGS=-static -nostdlib + +dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb +$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts + dtc -I dts -O dtb -o $@ $< + +.PHONY: dtb +dtb: $(dtb) + +elf := $(BUILD_DIR)/xip.elf +$(elf): xip.S $(dtb) + $(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $< + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/xip.bin +$(bin): $(elf) + $(OBJCOPY) -O binary $< $@ + +.PHONY: bin +bin: $(bin) + +hex := $(BUILD_DIR)/xip.hex +$(hex): $(bin) + od -t x4 -An -w4 -v $< > $@ + +.PHONY: hex +hex: $(hex) + +romgen := $(BUILD_DIR)/rom.v +$(romgen): $(hex) + $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ + +.PHONY: romgen +romgen: $(romgen) + +.PHONY: clean +clean:: + rm -rf $(hex) $(elf) diff --git a/fpga/bootrom/xip/xip.S b/fpga/bootrom/xip/xip.S new file mode 100644 index 00000000..7445f4c9 --- /dev/null +++ b/fpga/bootrom/xip/xip.S @@ -0,0 +1,16 @@ +// See LICENSE for license details. +// Execute in place +// Jump directly to XIP_TARGET_ADDR + + .section .text.init + .option norvc + .globl _start +_start: + csrr a0, mhartid + la a1, dtb + li t0, XIP_TARGET_ADDR + jr t0 + + .section .rodata +dtb: + .incbin DEVICE_TREE diff --git a/fpga/common.mk b/fpga/common.mk new file mode 100644 index 00000000..5466ed7b --- /dev/null +++ b/fpga/common.mk @@ -0,0 +1,119 @@ +# See LICENSE for license details. + +# Required variables: +# - MODEL +# - PROJECT +# - CONFIG_PROJECT +# - CONFIG +# - BUILD_DIR +# - FPGA_DIR + +# Optional variables: +# - EXTRA_FPGA_VSRCS + +# export to bootloader +export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf + +# export to fpga-shells +export FPGA_TOP_SYSTEM=$(MODEL) +export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM) +export fpga_common_script_dir=$(FPGA_DIR)/common/tcl +export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl + +export BUILD_DIR + +EXTRA_FPGA_VSRCS ?= +PATCHVERILOG ?= "" +BOOTROM_DIR ?= "" + +base_dir=$(abspath ..) +export rocketchip_dir := $(base_dir)/generators/rocket-chip +SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10 +SBT_PROJECT ?= chipyard +firrtl_dir := $(base_dir)/tools/firrtl + +# Build firrtl.jar and put it where chisel3 can find it. +FIRRTL_JAR := $(base_dir)/lib/firrtl.jar +FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver + +$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala") + $(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala + mkdir -p $(base_dir)/lib + cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR) + +# Build .fir +long_name := $(CONFIG_PROJECT).$(CONFIG) +firrtl := $(BUILD_DIR)/$(long_name).fir +$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR) + mkdir -p $(dir $@) + cd $(base_dir) && $(SBT) "project freedomPlatforms" \ + "runMain chipyard.Generator \ + --target-dir $(BUILD_DIR) \ + --name $(long_name) \ + --top-module $(PROJECT).$(MODEL) \ + --legacy-configs $(CONFIG_PROJECT).$(CONFIG)" + +.PHONY: firrtl +firrtl: $(firrtl) + +# Build .v +verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v +$(verilog): $(firrtl) $(FIRRTL_JAR) + $(FIRRTL) -i $(firrtl) -o $@ -X verilog +ifneq ($(PATCHVERILOG),"") + $(PATCHVERILOG) +endif + +.PHONY: verilog +verilog: $(verilog) + +romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v +$(romgen): $(verilog) +ifneq ($(BOOTROM_DIR),"") + $(MAKE) -C $(BOOTROM_DIR) romgen + mv $(BUILD_DIR)/rom.v $@ +endif + +.PHONY: romgen +romgen: $(romgen) + +f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F +$(f): + echo $(VSRCS) > $@ + +bit := $(BUILD_DIR)/obj/$(MODEL).bit +$(bit): $(romgen) $(f) + cd $(BUILD_DIR); vivado \ + -nojournal -mode batch \ + -source $(fpga_common_script_dir)/vivado.tcl \ + -tclargs \ + -top-module "$(MODEL)" \ + -F "$(f)" \ + -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" + + +# Build .mcs +mcs := $(BUILD_DIR)/obj/$(MODEL).mcs +$(mcs): $(bit) + cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< + +.PHONY: mcs +mcs: $(mcs) + +# Build Libero project +prjx := $(BUILD_DIR)/libero/$(MODEL).prjx +$(prjx): $(verilog) + cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" + +.PHONY: prjx +prjx: $(prjx) + +# Clean +.PHONY: clean +clean: +ifneq ($(BOOTROM_DIR),"") + $(MAKE) -C $(BOOTROM_DIR) clean +endif + $(MAKE) -C $(FPGA_DIR) clean + rm -rf $(BUILD_DIR) diff --git a/fpga/fpga-shells b/fpga/fpga-shells new file mode 160000 index 00000000..e8e7f8a3 --- /dev/null +++ b/fpga/fpga-shells @@ -0,0 +1 @@ +Subproject commit e8e7f8a321ebde213ebc79db06422278d9aa477f diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala new file mode 100644 index 00000000..45f83036 --- /dev/null +++ b/fpga/src/main/scala/arty/Config.scala @@ -0,0 +1,65 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +import freechips.rocketchip.system._ +import freechips.rocketchip.tile._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ + +// Default FreedomEConfig +class DefaultFreedomEConfig extends Config ( + new WithNBreakpoints(2) ++ + new WithNExtTopInterrupts(0) ++ + new WithJtagDTM ++ + new TinyConfig +) + +// Freedom E300 Arty Dev Kit Peripherals +class E300DevKitPeripherals extends Config((site, here, up) => { + case PeripheryGPIOKey => List( + GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) + case PeripheryPWMKey => List( + PWMParams(address = 0x10015000, cmpWidth = 8), + PWMParams(address = 0x10025000, cmpWidth = 16), + PWMParams(address = 0x10035000, cmpWidth = 16)) + case PeripherySPIKey => List( + SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), + SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) + case PeripherySPIFlashKey => List( + SPIFlashParams( + fAddress = 0x20000000, + rAddress = 0x10014000, + defaultSampleDel = 3)) + case PeripheryUARTKey => List( + UARTParams(address = 0x10013000), + UARTParams(address = 0x10023000)) + case PeripheryI2CKey => List( + I2CParams(address = 0x10016000)) + case PeripheryMockAONKey => + MockAONParams(address = 0x10000000) + case PeripheryMaskROMKey => List( + MaskROMParams(address = 0x10000, name = "BootROM")) +}) + +// Freedom E300 Arty Dev Kit Peripherals +class E300ArtyDevKitConfig extends Config( + new E300DevKitPeripherals ++ + new DefaultFreedomEConfig().alter((site,here,up) => { + case DTSTimebase => BigInt(32768) + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = 2, + idcodePartNum = 0x000, + idcodeManufId = 0x489, + debugIdleCycles = 5) + }) +) diff --git a/fpga/src/main/scala/arty/FPGAChip.scala b/fpga/src/main/scala/arty/FPGAChip.scala new file mode 100644 index 00000000..e0b0634c --- /dev/null +++ b/fpga/src/main/scala/arty/FPGAChip.scala @@ -0,0 +1,193 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import Chisel._ +import chisel3.core.{attach} +import chisel3.experimental.{withClockAndReset} + +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy.{LazyModule} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.spi._ + +import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + +//------------------------------------------------------------------------- +// E300ArtyDevKitFPGAChip +//------------------------------------------------------------------------- + +class E300ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell { + + //----------------------------------------------------------------------- + // Clock divider + //----------------------------------------------------------------------- + val slow_clock = Wire(Bool()) + + // Divide clock by 256, used to generate 32.768 kHz clock for AON block + withClockAndReset(clock_8MHz, ~mmcm_locked) { + val clockToggleReg = RegInit(false.B) + val (_, slowTick) = Counter(true.B, 256) + when (slowTick) {clockToggleReg := ~clockToggleReg} + slow_clock := clockToggleReg + } + + //----------------------------------------------------------------------- + // DUT + //----------------------------------------------------------------------- + + withClockAndReset(clock_32MHz, ck_rst) { + val dut = Module(new E300ArtyDevKitPlatform) + + //--------------------------------------------------------------------- + // SPI flash IOBUFs + //--------------------------------------------------------------------- + + IOBUF(qspi_sck, dut.io.pins.qspi.sck) + IOBUF(qspi_cs, dut.io.pins.qspi.cs(0)) + + IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0)) + IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1)) + IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2)) + IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3)) + + //--------------------------------------------------------------------- + // JTAG IOBUFs + //--------------------------------------------------------------------- + + dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt + + IOBUF(jd_5, dut.io.pins.jtag.TMS) + PULLUP(jd_5) + + IOBUF(jd_4, dut.io.pins.jtag.TDI) + PULLUP(jd_4) + + IOBUF(jd_0, dut.io.pins.jtag.TDO) + + // mimic putting a pullup on this line (part of reset vote) + SRST_n := IOBUF(jd_6) + PULLUP(jd_6) + + // jtag reset + val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz) + dut.io.jtag_reset := jtag_power_on_reset + + // debug reset + dut_ndreset := dut.io.ndreset + + //--------------------------------------------------------------------- + // Assignment to package pins + //--------------------------------------------------------------------- + // Pins IO0-IO13 + // + // FTDI UART TX/RX are not connected to ck_io[0,1] + // the way they are on Arduino boards. We copy outgoing + // data to both places, switch 3 (sw[3]) determines whether + // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) + + val iobuf_ck0 = Module(new IOBUF()) + iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval + iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe + attach(iobuf_ck0.io.IO, ck_io(0)) // UART0 RX + + val iobuf_uart_txd = Module(new IOBUF()) + iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval + iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe + attach(iobuf_uart_txd.io.IO, uart_txd_in) + + // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] + val sw_3_in = IOBUF(sw_3) + dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in, + iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie, + iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie) + + IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17)) + + // Shield header row 0: PD2-PD7 + IOBUF(ck_io(2), dut.io.pins.gpio.pins(18)) + IOBUF(ck_io(3), dut.io.pins.gpio.pins(19)) // PWM1(1) + IOBUF(ck_io(4), dut.io.pins.gpio.pins(20)) // PWM1(0) + IOBUF(ck_io(5), dut.io.pins.gpio.pins(21)) // PWM1(2) + IOBUF(ck_io(6), dut.io.pins.gpio.pins(22)) // PWM1(3) + IOBUF(ck_io(7), dut.io.pins.gpio.pins(23)) + + // Header row 1: PB0-PB5 + IOBUF(ck_io(8), dut.io.pins.gpio.pins(0)) // PWM0(0) + IOBUF(ck_io(9), dut.io.pins.gpio.pins(1)) // PWM0(1) + IOBUF(ck_io(10), dut.io.pins.gpio.pins(2)) // SPI CS(0) / PWM0(2) + IOBUF(ck_io(11), dut.io.pins.gpio.pins(3)) // SPI MOSI / PWM0(3) + IOBUF(ck_io(12), dut.io.pins.gpio.pins(4)) // SPI MISO + IOBUF(ck_io(13), dut.io.pins.gpio.pins(5)) // SPI SCK + + dut.io.pins.gpio.pins(6).i.ival := 0.U + dut.io.pins.gpio.pins(7).i.ival := 0.U + dut.io.pins.gpio.pins(8).i.ival := 0.U + + // Header row 3: A0-A5 (we don't support using them as analog inputs) + // just treat them as regular digital GPIOs + IOBUF(ck_io(15), dut.io.pins.gpio.pins(9)) // A1 = CS(2) + IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0) + IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1) + IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA + IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL + + // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty + // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active + IOBUF(led0_r, dut.io.pins.gpio.pins(1)) + IOBUF(led0_g, dut.io.pins.gpio.pins(2)) + IOBUF(led0_b, dut.io.pins.gpio.pins(3)) + + // Note that this is the one which is actually connected on the HiFive/Crazy88 + // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active + IOBUF(led1_r, dut.io.pins.gpio.pins(19)) + IOBUF(led1_g, dut.io.pins.gpio.pins(21)) + IOBUF(led1_b, dut.io.pins.gpio.pins(22)) + + // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active + IOBUF(led2_r, dut.io.pins.gpio.pins(11)) + IOBUF(led2_g, dut.io.pins.gpio.pins(12)) + IOBUF(led2_b, dut.io.pins.gpio.pins(13)) + + // Only 19 out of 20 shield pins connected to GPIO pins + // Shield pin A5 (pin 14) left unconnected + // The buttons are connected to some extra GPIO pins not connected on the + // HiFive1 board + IOBUF(btn_0, dut.io.pins.gpio.pins(15)) + IOBUF(btn_1, dut.io.pins.gpio.pins(30)) + IOBUF(btn_2, dut.io.pins.gpio.pins(31)) + + val iobuf_btn_3 = Module(new IOBUF()) + iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval + iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe + attach(btn_3, iobuf_btn_3.io.IO) + dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie + + // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 + IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX + IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX + + // SPI2 pins mapped to 6 pin ICSP connector (standard on later + // arduinos) These are connected to some extra GPIO pins not connected + // on the HiFive1 board + IOBUF(ck_ss, dut.io.pins.gpio.pins(26)) + IOBUF(ck_mosi, dut.io.pins.gpio.pins(27)) + IOBUF(ck_miso, dut.io.pins.gpio.pins(28)) + IOBUF(ck_sck, dut.io.pins.gpio.pins(29)) + + // Use the LEDs for some more useful debugging things + IOBUF(led_0, ck_rst) + IOBUF(led_1, SRST_n) + IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival) + IOBUF(led_3, dut.io.pins.gpio.pins(14)) + + //--------------------------------------------------------------------- + // Unconnected inputs + //--------------------------------------------------------------------- + + dut.io.pins.aon.erst_n.i.ival := ~reset_periph + dut.io.pins.aon.lfextclk.i.ival := slow_clock + dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U + } +} diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala new file mode 100644 index 00000000..0f76cb15 --- /dev/null +++ b/fpga/src/main/scala/arty/Platform.scala @@ -0,0 +1,178 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import Chisel._ + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util.ResetCatchAndSync +import freechips.rocketchip.system._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.pinctrl._ + +//------------------------------------------------------------------------- +// PinGen +//------------------------------------------------------------------------- + +object PinGen { + def apply(): BasePin = { + val pin = new BasePin() + pin + } +} + +//------------------------------------------------------------------------- +// E300ArtyDevKitPlatformIO +//------------------------------------------------------------------------- + +class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { + val pins = new Bundle { + val jtag = new JTAGPins(() => PinGen(), false) + val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0)) + val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0)) + val aon = new MockAONWrapperPins() + } + val jtag_reset = Bool(INPUT) + val ndreset = Bool(OUTPUT) +} + +//------------------------------------------------------------------------- +// E300ArtyDevKitPlatform +//------------------------------------------------------------------------- + +class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { + val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) + val io = new E300ArtyDevKitPlatformIO + + // This needs to be de-asserted synchronously to the coreClk. + val async_corerst = sys.aon.rsts.corerst + // Add in debug-controlled reset. + sys.reset := ResetCatchAndSync(clock, async_corerst, 20) + Debug.connectDebugClockAndReset(sys.debug, clock) + + //----------------------------------------------------------------------- + // Check for unsupported rocket-chip connections + //----------------------------------------------------------------------- + + require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); + + //----------------------------------------------------------------------- + // Build GPIO Pin Mux + //----------------------------------------------------------------------- + // Pin Mux for UART, SPI, PWM + // First convert the System outputs into "IOF" using the respective *GPIOPort + // converters. + + val sys_uart = sys.uart + val sys_pwm = sys.pwm + val sys_spi = sys.spi + val sys_i2c = sys.i2c + + val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} + val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} + val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} + val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} + + (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } + (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + + //----------------------------------------------------------------------- + // Default Pin connections before attaching pinmux + + for (iof_0 <- sys.gpio(0).iof_0.get) { + iof_0.default() + } + + for (iof_1 <- sys.gpio(0).iof_1.get) { + iof_1.default() + } + + //----------------------------------------------------------------------- + + val iof_0 = sys.gpio(0).iof_0.get + val iof_1 = sys.gpio(0).iof_1.get + + // SPI1 (0 is the dedicated) + BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) + BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) + BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) + BasePinToIOF(spi_pins(0).sck, iof_0(5)) + BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) + BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) + BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) + BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) + BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) + + // SPI2 + BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) + BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) + BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) + BasePinToIOF(spi_pins(1).sck, iof_0(29)) + BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) + BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) + + // I2C + if (p(PeripheryI2CKey).length == 1) { + BasePinToIOF(i2c_pins(0).sda, iof_0(12)) + BasePinToIOF(i2c_pins(0).scl, iof_0(13)) + } + + // UART0 + BasePinToIOF(uart_pins(0).rxd, iof_0(16)) + BasePinToIOF(uart_pins(0).txd, iof_0(17)) + + // UART1 + BasePinToIOF(uart_pins(1).rxd, iof_0(24)) + BasePinToIOF(uart_pins(1).txd, iof_0(25)) + + //PWM + BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) + BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) + BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) + BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) + + BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) + BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) + BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) + BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) + + BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) + BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) + BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) + BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) + + //----------------------------------------------------------------------- + // Drive actual Pads + //----------------------------------------------------------------------- + + // Result of Pin Mux + GPIOPinsFromPort(io.pins.gpio, sys.gpio(0)) + + // Dedicated SPI Pads + SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3) + + // JTAG Debug Interface + val sjtag = sys.debug.get.systemjtag.get + JTAGPinsFromPort(io.pins.jtag, sjtag.jtag) + sjtag.reset := io.jtag_reset + sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + + io.ndreset := sys.debug.get.ndreset + + // AON Pads -- direct connection is OK because + // EnhancedPin is hard-coded in MockAONPads + // and thus there is no .fromPort method. + io.pins.aon <> sys.aon.pins +} diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala new file mode 100644 index 00000000..f614c06c --- /dev/null +++ b/fpga/src/main/scala/arty/System.scala @@ -0,0 +1,51 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import Chisel._ + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.system._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ + +//------------------------------------------------------------------------- +// E300ArtyDevKitSystem +//------------------------------------------------------------------------- + +class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem + with HasPeripheryDebug + with HasPeripheryMockAON + with chipyard.example.CanHavePeripheryGCD + with HasPeripheryUART + with HasPeripherySPIFlash + with HasPeripherySPI + with HasPeripheryGPIO + with HasPeripheryPWM + with HasPeripheryI2C { + override lazy val module = new E300ArtyDevKitSystemModule(this) +} + +class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L) + extends RocketSubsystemModuleImp(_outer) + with HasPeripheryDebugModuleImp + with chipyard.example.CanHavePeripheryGCDModuleImp + with HasPeripheryUARTModuleImp + with HasPeripherySPIModuleImp + with HasPeripheryGPIOModuleImp + with HasPeripherySPIFlashModuleImp + with HasPeripheryMockAONModuleImp + with HasPeripheryPWMModuleImp + with HasPeripheryI2CModuleImp { + // Reset vector is set to the location of the mask rom + val maskROMParams = p(PeripheryMaskROMKey) + global_reset_vector := maskROMParams(0).address.U +} From 3b6d5846729bd4ed2c8f75869251558fd6340f0c Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 2 Sep 2020 13:27:31 -0700 Subject: [PATCH 152/457] Adding submodule update script for FPGA tools. --- scripts/init-fpga.sh | 11 +++++++++++ scripts/init-submodules-no-riscv-tools-nolog.sh | 2 ++ 2 files changed, 13 insertions(+) create mode 100755 scripts/init-fpga.sh diff --git a/scripts/init-fpga.sh b/scripts/init-fpga.sh new file mode 100755 index 00000000..08203259 --- /dev/null +++ b/scripts/init-fpga.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +# exit script if any command fails +set -e +set -o pipefail + +# Enable submodule update for FPGA tools. +git config --unset submodule.fpga/fpga-shells.update +# Initialize local FPGA tools. +git submodule update --init --recursive fpga/fpga-shells +# Disable submodule update for FPGA tools. +git config submodule.fpga/fpga-shells.update none diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index cede5e47..c243a86f 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -39,6 +39,8 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.software/firemarshal.update none +# Disable updates to the local FPGA tools +git config submodule.fpga/fpga-shells.update none git submodule update --init --recursive #--jobs 8 # Un-ignore toolchain submodules From 4b304623208b4c0b55f4c2f0f280f2c30011acf4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 2 Sep 2020 20:19:27 -0700 Subject: [PATCH 153/457] Change default IO set to JTAG+Serial, instead of JTAG+DMI --- docs/Advanced-Concepts/Chip-Communication.rst | 33 +------------------ .../src/main/scala/ConfigFragments.scala | 9 ++++- .../chipyard/src/main/scala/IOBinders.scala | 22 ++++--------- .../main/scala/config/AbstractConfig.scala | 3 +- .../src/main/scala/config/ArianeConfigs.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 12 ++----- .../main/scala/config/TutorialConfigs.scala | 19 ++++++++--- 7 files changed, 34 insertions(+), 66 deletions(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index e36805ec..84bfc5fb 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -130,38 +130,7 @@ Using the JTAG Interface ------------------------ The main way to use JTAG with a Rocket Chip based system is to instantiate the Debug Transfer Module (DTM) -and configure it to use a JTAG interface (by default the DTM is setup to use the DMI interface mentioned above). - -Creating a DTM+JTAG Config -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -First, a DTM config must be created for the system that you want to create. -This step is similar to the DMI simulation section within the :ref:`Starting the TSI or DMI Simulation` section. -The configuration is very similar to a DMI-based configuration. The main difference -is the addition of the ``WithJtagDTM`` config fragment that configures the instantiated DTM to use the JTAG protocol as the -bringup method. - -.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala - :language: scala - :start-after: DOC include start: JtagRocket - :end-before: DOC include end: JtagRocket - -Building a DTM+JTAG Simulator -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -After creating the config, call the ``make`` command like the following to build a simulator for your RTL: - -.. code-block:: bash - - cd sims/verilator - # or - cd sims/vcs - - make CONFIG=jtagRocketConfig - -In this example, the simulation will use the config that you previously specified, as well as set -the other parameters that are needed to satisfy the build system. After that point, you -should have a JTAG enabled simulator that you can attach to using OpenOCD and GDB! +and configure it to use a JTAG interface. The default Chipyard designs configure the DTM to use JTAG. you may attach OpenOCD and GDB to any of the default JTAG-enabled designs. Debugging with JTAG ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 6336c05a..cfa465e7 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.config.{Field, Parameters, Config} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.{BootROMLocated} -import freechips.rocketchip.devices.debug.{Debug} +import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.groundtest.{GroundTestSubsystem} import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} @@ -163,3 +163,10 @@ class WithTileDividedClock extends Config((site, here, up) => { case ClockingSchemeKey => ClockingSchemeGenerators.harnessDividedClock }) +class WithDMIDTM extends Config((site, here, up) => { + case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) +}) + +class WithNoDebug extends Config((site, here, up) => { + case DebugModuleKey => None +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index f13a6882..54a0d1dc 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -167,6 +167,7 @@ object AddIOCells { /** * Add IO cells to a debug module and name the IO ports, for debug IO which must go off-chip * For on-chip debug IO, drive them appropriately + * Mostly copied from rocket-chip/src/main/scala/devices/debug/Periphery.scala * @param system A BaseSubsystem that might have a debug module * @return Returns a tuple2 of (Generated debug io ports, Generated IOCells) */ @@ -175,27 +176,22 @@ object AddIOCells { val tlbus = system.outer.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere) val debug_clock = Wire(Clock()).suggestName("debug_clock") val debug_reset = Wire(Reset()).suggestName("debug_reset") - debug_clock := false.B.asClock - debug_reset := false.B + debug_clock := false.B.asClock // must provide default assignment to avoid firrtl unassigned error + debug_reset := false.B // must provide default assignment to avoid firrtl unassigned error BoringUtils.bore(tlbus.module.clock, Seq(debug_clock)) BoringUtils.bore(tlbus.module.reset, Seq(debug_reset)) // We never use the PSDIO, so tie it off on-chip system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } - - // Set resetCtrlOpt with the system reset system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := debug_reset.asBool } } - system.debug.map { d => // Tie off extTrigger d.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } - // Tie off disableDebug d.disableDebug.foreach { d => d := false.B } - // Drive JTAG on-chip IOs d.systemjtag.map { j => j.reset := debug_reset @@ -204,15 +200,9 @@ object AddIOCells { j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W) } } - - - // Connect DebugClockAndReset to system implicit clock. TODO this should use the clock of the bus the debug module is attached to - - Debug.connectDebugClockAndReset(Some(debug), debug_clock)(system.p) // Add IOCells for the DMI/JTAG/APB ports - val dmiTuple = debug.clockeddmi.map { d => IOCell.generateIOFromSignal(d, Some("iocell_dmi"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) } @@ -412,7 +402,7 @@ class WithSimDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { val (ports, iocells) = AddIOCells.debug(system)(system.p) val harnessFn = (th: HasHarnessSignalReferences) => { - val dtm_success = Wire(Bool()) + val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } ports.map { case d: ClockedDMIIO => @@ -437,8 +427,8 @@ class WithTiedOffDebug extends OverrideIOBinder({ d.dmi.req.valid := false.B d.dmi.req.bits := DontCare d.dmi.resp.ready := true.B - d.dmiClock := th.harnessClock - d.dmiReset := th.harnessReset + d.dmiClock := false.B.asClock + d.dmiReset := true.B case j: JTAGIO => j.TCK := true.B.asClock j.TMS := true.B diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 2b9473ed..a925ec56 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -11,13 +11,14 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimDebug ++ // attach SimJTAG new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks + new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 7bc985aa..6bc7cf69 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -14,6 +14,6 @@ class ArianeConfig extends Config( class dmiArianeConfig extends Config( new chipyard.iobinders.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial - new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation, override default tie-off debug + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 07033609..420ba192 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -23,18 +23,10 @@ class GemminiRocketConfig extends Config( new chipyard.config.AbstractConfig) // DOC include end: GemminiRocketConfig -// DOC include start: JtagRocket -class jtagRocketConfig extends Config( - new chipyard.iobinders.WithSimDebug ++ // add SimDebug, in addition to default SimSerial - new freechips.rocketchip.subsystem.WithJtagDTM ++ // sets DTM communication interface to JTAG - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) -// DOC include end: JtagRocket - // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.iobinders.WithTiedOffSerial ++ // tie-off serial, override default add SimSerial - new chipyard.iobinders.WithSimDebug ++ // add SimDebug, override default tie-off debug + new chipyard.iobinders.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: DmiRocket diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index 8872ed5e..d501b6c0 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -23,7 +23,7 @@ class TutorialStarterConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // Connect a SimUART adapter to display UART on stdout new chipyard.iobinders.WithBlackBoxSimMem ++ // Connect simulated external memory new chipyard.iobinders.WithTieOffInterrupts ++ // Do not simulate external interrupts - new chipyard.iobinders.WithTiedOffDebug ++ // Disconnect the debug module, since we use TSI for bring-up + new chipyard.iobinders.WithSimDebug ++ // Connect SimJTAG (or SimDTM) widgets to debug ios new chipyard.iobinders.WithSimSerial ++ // Connect external SimSerial widget to drive TSI // Config fragments below this line affect hardware generation @@ -43,13 +43,19 @@ class TutorialStarterConfig extends Config( // Uncomment this line, and specify a size if you want to have a L2 // new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++ + // Set the debug module to expose an external JTAG port + new freechips.rocketchip.subsystem.WithJtagDTM ++ + // For simpler designs, we want to minimize IOs on // our Top. These config fragments remove unnecessary // ports new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + + // Use the standard hierarchical bus topology including mbus+l2 + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + // BaseConfig configures "bare" rocketchip system new freechips.rocketchip.system.BaseConfig ) @@ -60,7 +66,7 @@ class TutorialMMIOConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -76,6 +82,7 @@ class TutorialMMIOConfig extends Config( // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ @@ -88,7 +95,7 @@ class TutorialSha3Config extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -101,6 +108,7 @@ class TutorialSha3Config extends Config( // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ @@ -114,7 +122,7 @@ class TutorialSha3BlackBoxConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -128,6 +136,7 @@ class TutorialSha3BlackBoxConfig extends Config( // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ From 0995f1b04b86d167578925d95da41f79f82fdd23 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 2 Sep 2020 21:25:36 -0700 Subject: [PATCH 154/457] UCode passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 477f9a4e..4c3bab58 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 477f9a4eb9209cfc8eaae2f8e9f80f951c057342 +Subproject commit 4c3bab5885b7d9f3ce0d621c0c2918aa853e879c From 23e4c22a44963f03c05eb1687865ca9490c71d25 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 2 Sep 2020 23:52:55 -0700 Subject: [PATCH 155/457] Don't run find in base_dir to avoid slow filesystem search --- common.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 89ebbea3..f8bd4cf4 100644 --- a/common.mk +++ b/common.mk @@ -62,7 +62,8 @@ SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstoo SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources -SBT_SOURCES = $(call lookup_srcs,$(base_dir),sbt) +SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) +SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt ######################################################################################### # jar creation variables and rules From 0656c5da4f0e99e0be5a4a18626a96c6462f5006 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Sep 2020 20:29:19 -0700 Subject: [PATCH 156/457] First pass on using CY make system --- fpga/Makefile | 93 +++++++++++++++++++++++++ fpga/src/main/scala/arty/Config.scala | 4 +- fpga/src/main/scala/arty/Platform.scala | 1 + fpga/src/main/scala/arty/System.scala | 12 +++- 4 files changed, 105 insertions(+), 5 deletions(-) create mode 100644 fpga/Makefile diff --git a/fpga/Makefile b/fpga/Makefile new file mode 100644 index 00000000..dcafb930 --- /dev/null +++ b/fpga/Makefile @@ -0,0 +1,93 @@ +######################################################################################### +# fpga prototype makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### +base_dir=$(abspath ..) +sim_dir=$(abspath .) + +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/variables.mk + +export SUB_PROJECT=fpga +export SBT_PROJECT=freedomPlatforms +export MODEL=E300ArtyDevKitFPGAChip +export VLOG_MODEL=E300ArtyDevKitFPGAChip +export MODEL_PACKAGE=sifive.freedom.everywhere.e300artydevkit +export CONFIG=E300ArtyDevKitConfig +export CONFIG_PACKAGE=sifive.freedom.everywhere.e300artydevkit +export GENERATOR_PACKAGE=chipyard +export TB=none +export TOP=E300ArtyDevKitPlatform +export BOARD=arty + +export bootrom_dir := $(base_dir)/fpga/bootrom/xip +fpga_dir=$(base_dir)/fpga/fpga-shells/xilinx + +sim_name = verilator # unused + +######################################################################################### +# import other necessary rules and variables +######################################################################################### +include $(base_dir)/common.mk + +######################################################################################### +# copy from other directory +######################################################################################### +romgen := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).rom.v +$(romgen): $(verilog) +ifneq ($(bootrom_dir),"") + $(MAKE) -C $(bootrom_dir) romgen + mv $(build_dir)/rom.v $@ +endif + +.PHONY: romgen +romgen: $(romgen) + +f := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F +$(f): + echo $(VSRCS) > $@ + +bit := $(build_dir)/obj/$(MODEL).bit +$(bit): $(romgen) $(f) + cd $(build_dir); vivado \ + -nojournal -mode batch \ + -source $(fpga_common_script_dir)/vivado.tcl \ + -tclargs \ + -top-module "$(MODEL)" \ + -F "$(f)" \ + -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" + + +# Build .mcs +mcs := $(build_dir)/obj/$(MODEL).mcs +$(mcs): $(bit) + cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< + +.PHONY: mcs +mcs: $(mcs) + +# Build Libero project +prjx := $(build_dir)/libero/$(MODEL).prjx +$(prjx): $(verilog) + cd $(build_dir); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(build_dir) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" + +.PHONY: prjx +prjx: $(prjx) + + +######################################################################################### +# general cleanup rules +######################################################################################### +.PHONY: clean +clean: + rm -rf $(gen_dir) +ifneq ($(bootrom_dir),"") + $(MAKE) -C $(bootrom_dir) clean +endif + $(MAKE) -C $(FPGA_DIR) clean diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala index 45f83036..11642164 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/Config.scala @@ -47,8 +47,8 @@ class E300DevKitPeripherals extends Config((site, here, up) => { I2CParams(address = 0x10016000)) case PeripheryMockAONKey => MockAONParams(address = 0x10000000) - case PeripheryMaskROMKey => List( - MaskROMParams(address = 0x10000, name = "BootROM")) + case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM")) + case BootROMLocated(InSubsystem) => None }) // Freedom E300 Arty Dev Kit Peripherals diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala index 0f76cb15..14c31628 100644 --- a/fpga/src/main/scala/arty/Platform.scala +++ b/fpga/src/main/scala/arty/Platform.scala @@ -51,6 +51,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { //------------------------------------------------------------------------- class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { + //val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop? val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) val io = new E300ArtyDevKitPlatformIO diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala index f614c06c..46e5c34e 100644 --- a/fpga/src/main/scala/arty/System.scala +++ b/fpga/src/main/scala/arty/System.scala @@ -31,6 +31,12 @@ class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem with HasPeripheryGPIO with HasPeripheryPWM with HasPeripheryI2C { + val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } + val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } + + val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]() + tileResetVectorNexusNode := maskROMResetVectorSourceNode + override lazy val module = new E300ArtyDevKitSystemModule(this) } @@ -45,7 +51,7 @@ class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L) with HasPeripheryMockAONModuleImp with HasPeripheryPWMModuleImp with HasPeripheryI2CModuleImp { - // Reset vector is set to the location of the mask rom - val maskROMParams = p(PeripheryMaskROMKey) - global_reset_vector := maskROMParams(0).address.U + + // connect reset vector to 1st MaskROM + _outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U } From 5a885fdcfd621fffe6b1ad7c9a92d0dbbdf5db9c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Sep 2020 21:28:05 -0700 Subject: [PATCH 157/457] Delete old makefiles | Full switch to CY make system --- fpga/.gitignore | 3 + fpga/Makefile | 73 +++++++---- fpga/Makefile.e300artydevkit | 23 ---- fpga/bootrom/xip/Makefile | 13 +- fpga/common.mk | 119 ------------------ .../utilities/src/main/scala/Simulator.scala | 50 ++++---- 6 files changed, 93 insertions(+), 188 deletions(-) create mode 100644 fpga/.gitignore delete mode 100644 fpga/Makefile.e300artydevkit delete mode 100644 fpga/common.mk diff --git a/fpga/.gitignore b/fpga/.gitignore new file mode 100644 index 00000000..a0991ff4 --- /dev/null +++ b/fpga/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!Makefile diff --git a/fpga/Makefile b/fpga/Makefile index dcafb930..837902bc 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -8,27 +8,35 @@ base_dir=$(abspath ..) sim_dir=$(abspath .) +# do not generate simulation files +sim_name := none + ######################################################################################### # include shared variables ######################################################################################### include $(base_dir)/variables.mk -export SUB_PROJECT=fpga -export SBT_PROJECT=freedomPlatforms -export MODEL=E300ArtyDevKitFPGAChip -export VLOG_MODEL=E300ArtyDevKitFPGAChip -export MODEL_PACKAGE=sifive.freedom.everywhere.e300artydevkit -export CONFIG=E300ArtyDevKitConfig -export CONFIG_PACKAGE=sifive.freedom.everywhere.e300artydevkit -export GENERATOR_PACKAGE=chipyard -export TB=none -export TOP=E300ArtyDevKitPlatform -export BOARD=arty +# default variables to build the arty example +SUB_PROJECT := fpga +SBT_PROJECT := freedomPlatforms +MODEL := E300ArtyDevKitFPGAChip +VLOG_MODEL := E300ArtyDevKitFPGAChip +MODEL_PACKAGE := sifive.freedom.everywhere.e300artydevkit +CONFIG := E300ArtyDevKitConfig +CONFIG_PACKAGE := sifive.freedom.everywhere.e300artydevkit +GENERATOR_PACKAGE := chipyard +TB := none # unused +TOP := E300ArtyDevKitPlatform -export bootrom_dir := $(base_dir)/fpga/bootrom/xip -fpga_dir=$(base_dir)/fpga/fpga-shells/xilinx +# setup the board to use +BOARD ?= arty -sim_name = verilator # unused +######################################################################################### +# misc. directories +######################################################################################### +bootrom_dir := $(base_dir)/fpga/bootrom/xip +fpga_common_script_dir := $(FPGA_DIR)/common/tcl +fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx ######################################################################################### # import other necessary rules and variables @@ -38,8 +46,23 @@ include $(base_dir)/common.mk ######################################################################################### # copy from other directory ######################################################################################### -romgen := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).rom.v -$(romgen): $(verilog) +all_vsrcs := \ + $(sim_vsrcs) \ + $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ + $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v \ + $(build_dir)/$(long_name).rom.v + +######################################################################################### +# build rom for the fpga +######################################################################################### +# needed for bootrom makefile +export BUILD_DIR=$(build_dir) +export ROCKETCHIP_DIR +export LONG_NAME=$(long_name) +export ROMCONF=$(build_dir)/$(long_name).rom.conf + +romgen := $(build_dir)/$(long_name).rom.v +$(romgen): $(sim_vsrcs) ifneq ($(bootrom_dir),"") $(MAKE) -C $(bootrom_dir) romgen mv $(build_dir)/rom.v $@ @@ -48,9 +71,14 @@ endif .PHONY: romgen romgen: $(romgen) -f := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F -$(f): - echo $(VSRCS) > $@ +######################################################################################### +# vivado rules +######################################################################################### +# combine all sources into single .F +f := $(build_dir)/$(long_name).vsrcs.F +$(f): $(sim_common_files) $(all_vsrcs) + $(foreach file,$(all_vsrcs),echo "$(file)" >> $@;) + cat $(sim_common_files) >> $@ bit := $(build_dir)/obj/$(MODEL).bit $(bit): $(romgen) $(f) @@ -63,6 +91,8 @@ $(bit): $(romgen) $(f) -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ -board "$(BOARD)" +.PHONY: bit +bit: $(bit) # Build .mcs mcs := $(build_dir)/obj/$(MODEL).mcs @@ -72,6 +102,9 @@ $(mcs): $(bit) .PHONY: mcs mcs: $(mcs) +######################################################################################### +# mircosemi rules +######################################################################################### # Build Libero project prjx := $(build_dir)/libero/$(MODEL).prjx $(prjx): $(verilog) @@ -80,7 +113,6 @@ $(prjx): $(verilog) .PHONY: prjx prjx: $(prjx) - ######################################################################################### # general cleanup rules ######################################################################################### @@ -90,4 +122,3 @@ clean: ifneq ($(bootrom_dir),"") $(MAKE) -C $(bootrom_dir) clean endif - $(MAKE) -C $(FPGA_DIR) clean diff --git a/fpga/Makefile.e300artydevkit b/fpga/Makefile.e300artydevkit deleted file mode 100644 index 5f5c595b..00000000 --- a/fpga/Makefile.e300artydevkit +++ /dev/null @@ -1,23 +0,0 @@ -# See LICENSE for license details. -base_dir=$(abspath ..) -BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit -FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx -MODEL := E300ArtyDevKitFPGAChip -PROJECT := sifive.freedom.everywhere.e300artydevkit -export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit -export CONFIG := E300ArtyDevKitConfig -export BOARD := arty -export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip - -rocketchip_dir := $(base_dir)/generators/rocket-chip -sifiveblocks_dir := $(base_dir)/generators/sifive-blocks -VSRCS := \ - $(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \ - $(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \ - $(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \ - $(sifiveblocks_dir)/vsrc/SRLatch.v \ - $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \ - $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \ - $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v - -include common.mk diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile index 57f94d49..e51fd9c5 100644 --- a/fpga/bootrom/xip/Makefile +++ b/fpga/bootrom/xip/Makefile @@ -1,12 +1,17 @@ # RISCV environment variable must be set +# needs the following variables +# LONG_NAME +# BUILD_DIR +# ROCKETCHIP_DIR +# ROMCONF CC=$(RISCV)/bin/riscv64-unknown-elf-gcc OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g LFLAGS=-static -nostdlib -dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb -$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts +dtb := $(BUILD_DIR)/$(LONG_NAME).dtb +$(dtb): $(BUILD_DIR)/$(LONG_NAME).dts dtc -I dts -O dtb -o $@ $< .PHONY: dtb @@ -35,11 +40,11 @@ hex: $(hex) romgen := $(BUILD_DIR)/rom.v $(romgen): $(hex) - $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ + $(ROCKETCHIP_DIR)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ .PHONY: romgen romgen: $(romgen) .PHONY: clean clean:: - rm -rf $(hex) $(elf) + rm -rf $(hex) $(elf) diff --git a/fpga/common.mk b/fpga/common.mk deleted file mode 100644 index 5466ed7b..00000000 --- a/fpga/common.mk +++ /dev/null @@ -1,119 +0,0 @@ -# See LICENSE for license details. - -# Required variables: -# - MODEL -# - PROJECT -# - CONFIG_PROJECT -# - CONFIG -# - BUILD_DIR -# - FPGA_DIR - -# Optional variables: -# - EXTRA_FPGA_VSRCS - -# export to bootloader -export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf - -# export to fpga-shells -export FPGA_TOP_SYSTEM=$(MODEL) -export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM) -export fpga_common_script_dir=$(FPGA_DIR)/common/tcl -export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl - -export BUILD_DIR - -EXTRA_FPGA_VSRCS ?= -PATCHVERILOG ?= "" -BOOTROM_DIR ?= "" - -base_dir=$(abspath ..) -export rocketchip_dir := $(base_dir)/generators/rocket-chip -SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10 -SBT_PROJECT ?= chipyard -firrtl_dir := $(base_dir)/tools/firrtl - -# Build firrtl.jar and put it where chisel3 can find it. -FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver - -$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala") - $(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala - mkdir -p $(base_dir)/lib - cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR) - -# Build .fir -long_name := $(CONFIG_PROJECT).$(CONFIG) -firrtl := $(BUILD_DIR)/$(long_name).fir -$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR) - mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "project freedomPlatforms" \ - "runMain chipyard.Generator \ - --target-dir $(BUILD_DIR) \ - --name $(long_name) \ - --top-module $(PROJECT).$(MODEL) \ - --legacy-configs $(CONFIG_PROJECT).$(CONFIG)" - -.PHONY: firrtl -firrtl: $(firrtl) - -# Build .v -verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v -$(verilog): $(firrtl) $(FIRRTL_JAR) - $(FIRRTL) -i $(firrtl) -o $@ -X verilog -ifneq ($(PATCHVERILOG),"") - $(PATCHVERILOG) -endif - -.PHONY: verilog -verilog: $(verilog) - -romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v -$(romgen): $(verilog) -ifneq ($(BOOTROM_DIR),"") - $(MAKE) -C $(BOOTROM_DIR) romgen - mv $(BUILD_DIR)/rom.v $@ -endif - -.PHONY: romgen -romgen: $(romgen) - -f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F -$(f): - echo $(VSRCS) > $@ - -bit := $(BUILD_DIR)/obj/$(MODEL).bit -$(bit): $(romgen) $(f) - cd $(BUILD_DIR); vivado \ - -nojournal -mode batch \ - -source $(fpga_common_script_dir)/vivado.tcl \ - -tclargs \ - -top-module "$(MODEL)" \ - -F "$(f)" \ - -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \ - -board "$(BOARD)" - - -# Build .mcs -mcs := $(BUILD_DIR)/obj/$(MODEL).mcs -$(mcs): $(bit) - cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< - -.PHONY: mcs -mcs: $(mcs) - -# Build Libero project -prjx := $(BUILD_DIR)/libero/$(MODEL).prjx -$(prjx): $(verilog) - cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" - -.PHONY: prjx -prjx: $(prjx) - -# Clean -.PHONY: clean -clean: -ifneq ($(BOOTROM_DIR),"") - $(MAKE) -C $(BOOTROM_DIR) clean -endif - $(MAKE) -C $(FPGA_DIR) clean - rm -rf $(BUILD_DIR) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index b2982db7..43edd33a 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -11,6 +11,7 @@ case class GenerateSimConfig( sealed trait Simulator object VerilatorSimulator extends Simulator object VCSSimulator extends Simulator +object NotSimulator extends Simulator trait HasGenerateSimConfig { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { @@ -22,15 +23,16 @@ trait HasGenerateSimConfig { .action((x, c) => x match { case "verilator" => c.copy(simulator = VerilatorSimulator) case "vcs" => c.copy(simulator = VCSSimulator) + case "none" => c.copy(simulator = NotSimulator) case _ => throw new Exception(s"Unrecognized simulator $x") }) - .text("Name of simulator to generate files for (verilator, vcs)") + .text("Name of simulator to generate files for (verilator, vcs, none)") opt[String]("target-dir") .abbr("td") .valueName("") .action((x, c) => c.copy(targetDir = x)) - .text("Target director to put files") + .text("Target directory to put files") opt[String]("dotFName") .abbr("df") @@ -50,6 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case VerilatorSimulator => s"-FI ${fname}" // vcs pulls headers in with +incdir, doesn't have anything like verilator.h case VCSSimulator => "" + case _ => "" } } else { // do nothing otherwise fname @@ -82,26 +85,31 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { out.close() } def resources(sim: Simulator): Seq[String] = Seq( - "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/SimDRAM.cc", - "/testchipip/csrc/mm.h", - "/testchipip/csrc/mm.cc", - "/testchipip/csrc/mm_dramsim2.h", - "/testchipip/csrc/mm_dramsim2.cc", - "/csrc/SimDTM.cc", - "/csrc/SimJTAG.cc", - "/csrc/remote_bitbang.h", - "/csrc/remote_bitbang.cc", "/vsrc/EICG_wrapper.v", - ) ++ (sim match { // simulator specific files to include - case VerilatorSimulator => Seq( - "/csrc/emulator.cc", - "/csrc/verilator.h", - ) - case VCSSimulator => Seq( - "/vsrc/TestDriver.v", - ) - }) + ) ++ (sim match { + case NotSimulator => Seq() + case _ => Seq( + "/testchipip/csrc/SimSerial.cc", + "/testchipip/csrc/SimDRAM.cc", + "/testchipip/csrc/mm.h", + "/testchipip/csrc/mm.cc", + "/testchipip/csrc/mm_dramsim2.h", + "/testchipip/csrc/mm_dramsim2.cc", + "/csrc/SimDTM.cc", + "/csrc/SimJTAG.cc", + "/csrc/remote_bitbang.h", + "/csrc/remote_bitbang.cc", + ) + }) ++ (sim match { // simulator specific files to include + case VerilatorSimulator => Seq( + "/csrc/emulator.cc", + "/csrc/verilator.h", + ) + case VCSSimulator => Seq( + "/vsrc/TestDriver.v", + ) + case _ => Seq() + }) def writeBootrom(): Unit = { firrtl.FileUtils.makeDirectory("./bootrom/") From 3258fd8db8021407d24abb37f303e1d2a3dd34d6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 3 Sep 2020 23:53:51 -0700 Subject: [PATCH 158/457] Remove JTAG from firesim comfigs due to @(posedge ~clk) issue --- docs/Advanced-Concepts/Chip-Communication.rst | 3 ++- generators/firechip/src/main/scala/TargetConfigs.scala | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 84bfc5fb..8d63992a 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -130,7 +130,8 @@ Using the JTAG Interface ------------------------ The main way to use JTAG with a Rocket Chip based system is to instantiate the Debug Transfer Module (DTM) -and configure it to use a JTAG interface. The default Chipyard designs configure the DTM to use JTAG. you may attach OpenOCD and GDB to any of the default JTAG-enabled designs. +and configure it to use a JTAG interface. The default Chipyard designs instantiate the DTM and configure it +to use JTAG. You may attach OpenOCD and GDB to any of the default JTAG-enabled designs. Debugging with JTAG ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 66a20bce..0d8cd367 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -88,7 +88,9 @@ class WithFireSimConfigTweaks extends Config( // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ // Required*: Scale default baud rate with periphery bus frequency - new chipyard.config.WithUART(BigInt(3686400L)) + new chipyard.config.WithUART(BigInt(3686400L)) ++ + // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock) + new chipyard.config.WithNoDebug ) /******************************************************************************* From 990362933db4c3b5c40ff0f762ecc1bb6eaa2f79 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 4 Sep 2020 14:16:42 -0700 Subject: [PATCH 159/457] Simple makefile variable fix to allow make mcs --- fpga/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/Makefile b/fpga/Makefile index 837902bc..ab538116 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -35,8 +35,8 @@ BOARD ?= arty # misc. directories ######################################################################################### bootrom_dir := $(base_dir)/fpga/bootrom/xip -fpga_common_script_dir := $(FPGA_DIR)/common/tcl fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx +fpga_common_script_dir := $(fpga_dir)/common/tcl ######################################################################################### # import other necessary rules and variables From 0f50e4d1186323c3de008de55892695039019add Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 4 Sep 2020 13:35:05 -0700 Subject: [PATCH 160/457] Split IOBinders into IOBinders and Harness Binders | punch out clocks to harness for simwidgets and bridges --- build.sbt | 2 +- .../chipyard/src/main/scala/ChipTop.scala | 18 +- .../chipyard/src/main/scala/Clocks.scala | 5 +- .../chipyard/src/main/scala/DigitalTop.scala | 1 - .../src/main/scala/HarnessBinders.scala | 274 ++++++++++ .../chipyard/src/main/scala/IOBinders.scala | 489 +++++++----------- .../chipyard/src/main/scala/TestHarness.scala | 17 +- .../main/scala/config/AbstractConfig.scala | 36 +- .../src/main/scala/config/ArianeConfigs.scala | 2 +- .../src/main/scala/config/BoomConfigs.scala | 4 +- .../src/main/scala/config/RocketConfigs.scala | 17 +- .../main/scala/config/TracegenConfigs.scala | 30 +- .../main/scala/config/TutorialConfigs.scala | 96 +--- .../src/main/scala/BridgeBinders.scala | 150 +++--- .../firechip/src/main/scala/FireSim.scala | 18 +- generators/icenet | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- tools/barstools | 2 +- 19 files changed, 643 insertions(+), 524 deletions(-) create mode 100644 generators/chipyard/src/main/scala/HarnessBinders.scala diff --git a/build.sbt b/build.sbt index 5d642c1d..3ca021a7 100644 --- a/build.sbt +++ b/build.sbt @@ -211,7 +211,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) - .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(chipyard, midasTargetUtils, midas, iocell, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ), diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index cf71987b..6ae63d57 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGr import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike} import freechips.rocketchip.util.{ResetCatchAndSync} -import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple} +import chipyard.iobinders._ import barstools.iocell.chisel._ @@ -26,11 +26,9 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions { // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) val iocells = ArrayBuffer.empty[IOCell] - // A list of functions to call in the test harness - val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction] // The system module specified by BuildSystem - val lSystem = LazyModule(p(BuildSystem)(p)).suggestName("system") + val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") // The implicitClockSinkNode provides the implicit clock and reset for the System val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) @@ -50,15 +48,13 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc // The implicit clock and reset for the system is also, by convention, used for all the IOBinders // TODO: This may not be the right thing to do in all cases - withClockAndReset(implicit_clock, implicit_reset) { - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(lSystem.module)).unzip3 - // We ignore _ports for now... - iocells ++= _iocells.flatten - harnessFunctions ++= _harnessFunctions.flatten - } + val (_ports, _iocells, _portMap) = ApplyIOBinders(lazySystem, p(IOBinders)) + // We ignore _ports for now... + iocells ++= _iocells + portMap ++= _portMap // Connect the implicit clock/reset, if present - lSystem.module match { case l: LazyModuleImp => { + lazySystem.module match { case l: LazyModuleImp => { l.clock := implicit_clock l.reset := implicit_reset }} diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 3fa349b5..d6b19e8d 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -91,7 +91,7 @@ object ClockingSchemeGenerators { chiptop.implicitClockSinkNode := implicitClockSourceNode // Drive the diplomaticclock graph of the DigitalTop (if present) - val simpleClockGroupSourceNode = chiptop.lSystem match { + val simpleClockGroupSourceNode = chiptop.lazySystem match { case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) l.asyncClockGroupsNode := n @@ -120,6 +120,7 @@ object ClockingSchemeGenerators { } }} + chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { clock_io := th.harnessClock Nil @@ -137,7 +138,7 @@ object ClockingSchemeGenerators { val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) chiptop.implicitClockSinkNode := implicitClockSourceNode - val simpleClockGroupSourceNode = chiptop.lSystem match { + val simpleClockGroupSourceNode = chiptop.lazySystem match { case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) l.asyncClockGroupsNode := n diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 81d0003d..ddcf66f3 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -33,7 +33,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp - with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala new file mode 100644 index 00000000..54c99042 --- /dev/null +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -0,0 +1,274 @@ +package chipyard.harness + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.jtag.{JTAGIO} +import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.subsystem._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ + +import barstools.iocell.chisel._ + +import testchipip._ + +import chipyard.HasHarnessSignalReferences + +import tracegen.{TraceGenSystemModuleImp} +import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} + +import scala.reflect.{ClassTag} + +case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]]]( + Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]]().withDefaultValue((t: Any, th: HasHarnessSignalReferences, d: Seq[Data]) => Nil) +) + + +object ApplyHarnessBinders { + def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { + val pm = portMap.withDefaultValue(Nil) + map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + } +} + +class OverrideHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> + ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + t match { + case system: T => fn(system, th, ports) + case _ => Nil + } + }) + ) +}) + +class ComposeHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> + ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + t match { + case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, ports) ++ fn(system, th, ports) + case _ => Nil + } + }) + ) +}) + +class WithGPIOTiedOff extends OverrideHarnessBinder({ + (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { case p: GPIOPortIO => p <> AnalogConst(0) } + Nil + } +}) + +class WithUARTAdapter extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + UARTAdapter.connect(ports.map(_.asInstanceOf[UARTPortIO]))(system.p) + Nil + } +}) + +class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ + (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + SimSPIFlashModel.connect(ports.map(_.asInstanceOf[SPIChipIO]), th.harnessReset, rdOnly)(system.p) + Nil + } +}) + +class WithSimBlockDevice extends OverrideHarnessBinder({ + (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val clock = WireInit(false.B.asClock) + ports.map { + case p: BlockDeviceIO => SimBlockDevice.connect(clock, th.harnessReset.asBool, Some(p))(system.p) + case c: Clock => clock := c + } + Nil + } +}) + +class WithBlockDeviceModel extends OverrideHarnessBinder({ + (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val clock = WireInit(false.B.asClock) + ports.map { + case p: BlockDeviceIO => withClockAndReset(clock, th.harnessReset) { BlockDeviceModel.connect(Some(p))(system.p) } + case c: Clock => clock := c + } + Nil + } +}) + +class WithLoopbackNIC extends OverrideHarnessBinder({ + (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val clock = WireInit(false.B.asClock) + ports.map { + case p: NICIOvonly => withClockAndReset(clock, th.harnessReset) { + NicLoopback.connect(Some(p), system.p(NICKey)) + } + case c: Clock => clock := c + } + Nil + } +}) + +class WithSimNetwork extends OverrideHarnessBinder({ + (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val clock = WireInit(false.B.asClock) + ports.map { + case p: NICIOvonly => SimNetwork.connect(Some(p), clock, th.harnessReset.asBool) + case c: Clock => clock := c + } + Nil + } +}) + +class WithSimAXIMem extends OverrideHarnessBinder({ + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val p: Parameters = chipyard.iobinders.GetSystemParameters(system) + val clock = WireInit(false.B.asClock) + ports.filter(_.isInstanceOf[Clock]).map { case p: Clock => clock := p } + val axi4_ports = ports.filter(_.isInstanceOf[AXI4Bundle]) + (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => + val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) + withClockAndReset(clock, th.harnessReset) { + Module(mem.module).suggestName("mem") + } + mem.io_axi4.head <> port + } + Nil + } +}) + +class WithBlackBoxSimMem extends OverrideHarnessBinder({ + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val p: Parameters = chipyard.iobinders.GetSystemParameters(system) + val clock = WireInit(false.B.asClock) + ports.filter(_.isInstanceOf[Clock]).map { case p: Clock => clock := p } + val axi4_ports = ports.collect { case p: AXI4Bundle => p } + (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => + val memSize = p(ExtMem).get.master.size + val lineSize = p(CacheBlockBytes) + val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)).suggestName("simdram") + mem.io.axi <> port + mem.io.clock := clock + mem.io.reset := th.harnessReset + } + Nil + } +}) + +class WithSimAXIMMIO extends OverrideHarnessBinder({ + (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val p: Parameters = chipyard.iobinders.GetSystemParameters(system) + val clock = WireInit(false.B.asClock) + ports.filter(_.isInstanceOf[Clock]).map { case p: Clock => clock := p } + (ports zip system.mmioAXI4Node.edges.in).zipWithIndex.map { case ((port: AXI4Bundle, edge), i) => + val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)(p)) + withClockAndReset(clock, th.harnessReset) { + Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") + } + mmio_mem.io_axi4.head <> port + } + Nil + } +}) + +class WithTieOffInterrupts extends OverrideHarnessBinder({ + (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { case p: UInt => p := 0.U } + Nil + } +}) + +class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ + (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { case p: AXI4Bundle => + p := DontCare + p.tieoff() + } + Nil + } +}) + +class WithSimDebug extends OverrideHarnessBinder({ + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + if (!ports.isEmpty) { + val dtm_success = Wire(Bool()) + when (dtm_success) { th.success := true.B } + ports.map { + case d: ClockedDMIIO => + val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success) + case j: JTAGIO => + val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + case _ => + require(false, "We only support DMI or JTAG simulated debug connections") + } + } + Nil + } +}) + +class WithTiedOffDebug extends OverrideHarnessBinder({ + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { + case d: ClockedDMIIO => + d.dmi.req.valid := false.B + d.dmi.req.bits := DontCare + d.dmi.resp.ready := true.B + d.dmiClock := false.B.asClock + d.dmiReset := true.B + case j: JTAGIO => + j.TCK := true.B.asClock + j.TMS := true.B + j.TDI := true.B + j.TRSTn.foreach { r => r := true.B } + case a: ClockedAPBBundle => + a.tieoff() + a.clock := false.B.asClock + a.reset := true.B.asAsyncReset + a.psel := false.B + a.penable := false.B + case _ => require(false) + } + Nil + } +}) + +class WithTiedOffSerial extends OverrideHarnessBinder({ + (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { case p: SerialIO => SerialAdapter.tieoff(Some(p)) } + Nil + } +}) + +class WithSimSerial extends OverrideHarnessBinder({ + (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val serial_clock = WireInit(false.B.asClock) + ports.map { + case p: SerialIO => + val ser_success = SerialAdapter.connectSimSerial(p, serial_clock, th.harnessReset) + when (ser_success) { th.success := true.B } + case c: Clock => + serial_clock := c + } + Nil + } +}) + +class WithTraceGenSuccess extends OverrideHarnessBinder({ + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { case p: Bool => when (p) { th.success := true.B } } + Nil + } +}) + +class WithSimDromajoBridge extends ComposeHarnessBinder({ + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } + Nil + } +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 54a0d1dc..0dad7e21 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -1,9 +1,8 @@ -package chipyard -package object iobinders { +package chipyard.iobinders import chisel3._ import chisel3.util.experimental.{BoringUtils} -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.{Analog, IO, DataMirror} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -23,7 +22,9 @@ import tracegen.{TraceGenSystemModuleImp} import barstools.iocell.chisel._ import testchipip._ -import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey} +import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} + +import chipyard.GlobalResetSchemeKey import scala.reflect.{ClassTag} @@ -43,17 +44,22 @@ import scala.reflect.{ClassTag} // DOC include start: IOBinders // This type describes a function callable on the TestHarness instance. Its return type is unused. -type TestHarnessFunction = (chipyard.HasHarnessSignalReferences) => Seq[Any] -// IOBinders will return a Seq of this tuple, which contains three fields: -// 1. A Seq containing all IO ports created by the IOBinder function -// 2. A Seq containing all IO cell modules created by the IOBinder function -// 3. An optional function to call inside the test harness (e.g. to connect the IOs) -type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction]) -case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]]( - Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil) + + +case object IOBinders extends Field[Map[String, (Any) => (Seq[Data], Seq[IOCell])]]( + Map[String, (Any) => (Seq[Data], Seq[IOCell])]().withDefaultValue((Any) => (Nil, Nil)) ) +object ApplyIOBinders { + def apply(sys: LazyModule, map: Map[String, (Any) => (Seq[Data], Seq[IOCell])]): + (Iterable[Data], Iterable[IOCell], Map[String, Seq[Data]]) = { + val r = map.map({ case (s,f) => (f(sys), s) }) ++ map.map({ case (s,f) => (f(sys.module), s) }) + (r.flatMap(_._1._1), r.flatMap(_._1._2), r.map { t => t._2 -> t._1._1 }) + } +} + + // Note: The parameters instance is accessible only through LazyModule // or LazyModuleImpLike. The self-type requirement in traits like // CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder @@ -71,12 +77,12 @@ object GetSystemParameters { // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { case system: T => fn(system) - case _ => Nil + case _ => (Nil, Nil) } }) ) @@ -84,32 +90,44 @@ class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassT // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { - case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system) - ++ fn(system)) - case _ => Nil + case system: T => + val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) + val h = fn(system) + (r._1 ++ h._1, r._2 ++ h._2) + case _ => (Nil, Nil) } }) ) }) +object BoreHelper { + def apply(name: String, source: Clock): Clock = { + val clock_io = IO(Output(Clock())).suggestName(name) + val clock_wire = Wire(Clock()).suggestName(s"chiptop_${name}") + dontTouch(clock_wire) + clock_wire := false.B.asClock // necessary for BoringUtils to work properly + BoringUtils.bore(source, Seq(clock_wire)) + clock_io := clock_wire + clock_io + } +} + // DOC include end: IOBinders -object AddIOCells { - /** - * Add IO cells to a SiFive GPIO devices and name the IO ports. - * @param gpios A Seq of GPIO port bundles - * @param genFn A callable function to generate a DigitalGPIOCell module to use - * @return Returns a tuple of (a 2D Seq of Analog IOs corresponding to individual GPIO pins; a 2D Seq of IOCell module references) - */ - def gpio(gpios: Seq[GPIOPortIO], genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[Seq[Analog]], Seq[Seq[IOCell]]) = { - gpios.zipWithIndex.map({ case (gpio, i) => + +case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) + + +class WithGPIOCells extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp) => { + val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) => gpio.pins.zipWithIndex.map({ case (pin, j) => val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}") - val iocell = genFn().suggestName(s"iocell_gpio_${i}_${j}") + val iocell = system.p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}") iocell.io.o := pin.o.oval iocell.io.oe := pin.o.oe iocell.io.ie := pin.o.ie @@ -118,40 +136,35 @@ object AddIOCells { (g, iocell) }).unzip }).unzip + (ports2d.flatten, cells2d.flatten) } +}) - /** - * Add IO cells to a SiFive UART devices and name the IO ports. - * @param uartPins A Seq of UART port bundles - * @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references) - */ - def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = { - uartPins.zipWithIndex.map({ case (u, i) => - val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}")) + +class WithUARTIOCells extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val (ports, cells2d) = system.uart.zipWithIndex.map({ case (u, i) => + val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}"), system.p(IOCellKey)) port.suggestName(s"uart_${i}") (port, ios) }).unzip + (ports, cells2d.flatten) } +}) - /** - * Add IO cells to a SiFive SPI devices and name the IO ports. - * @param spiPins A Seq of SPI port bundles - * @param basename The base name for this port (defaults to "spi") - * @param genFn A callable function to generate a DigitalGPIOCell module to use - * @return Returns a tuple of (A Seq of top-level SPIChipIO IOs; a 2D Seq of IOCell module references) - */ - def spi(spiPins: Seq[SPIPortIO], basename: String = "spi", genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[SPIChipIO], Seq[Seq[IOCell]]) = { - spiPins.zipWithIndex.map({ case (s, i) => - val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"${basename}_${i}") - val iocellBase = s"iocell_${basename}_${i}" +class WithSPIIOCells extends OverrideIOBinder({ + (system: HasPeripherySPIFlashModuleImp) => { + val (ports, cells2d) = system.qspi.zipWithIndex.map({ case (s, i) => + val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"spi_${i}") + val iocellBase = s"iocell_spi_${i}" // SCK and CS are unidirectional outputs - val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck")) - val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs")) + val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey)) + val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey)) // DQ are bidirectional, so then need special treatment val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) => - val iocell = genFn().suggestName(s"${iocellBase}_dq_${j}") + val iocell = system.p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}") iocell.io.o := pin.o iocell.io.oe := pin.oe iocell.io.ie := true.B @@ -162,17 +175,27 @@ object AddIOCells { (port, dqIOs ++ csIOs ++ sckIOs) }).unzip + (ports, cells2d.flatten) } +}) - /** - * Add IO cells to a debug module and name the IO ports, for debug IO which must go off-chip - * For on-chip debug IO, drive them appropriately - * Mostly copied from rocket-chip/src/main/scala/devices/debug/Periphery.scala - * @param system A BaseSubsystem that might have a debug module - * @return Returns a tuple2 of (Generated debug io ports, Generated IOCells) - */ - def debug(system: HasPeripheryDebugModuleImp)(implicit p: Parameters): (Seq[Bundle], Seq[IOCell]) = { - system.debug.map { debug => +class WithExtInterruptIOCells extends OverrideIOBinder({ + (system: HasExtInterruptsModuleImp) => { + if (system.outer.nExtInterrupts > 0) { + val (port, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey)) + port.suggestName("ext_interrupts") + (Seq(port), cells) + } else { + (Nil, Nil) + } + } +}) + + +class WithDebugIOCells extends OverrideIOBinder({ + (system: HasPeripheryDebugModuleImp) => { + system.debug.map({ debug => + val p = system.p val tlbus = system.outer.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere) val debug_clock = Wire(Clock()).suggestName("debug_clock") val debug_reset = Wire(Reset()).suggestName("debug_reset") @@ -204,288 +227,130 @@ object AddIOCells { // Add IOCells for the DMI/JTAG/APB ports val dmiTuple = debug.clockeddmi.map { d => - IOCell.generateIOFromSignal(d, Some("iocell_dmi"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(d, Some("iocell_dmi"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) } dmiTuple.map(_._1).foreach(_.suggestName("dmi")) val jtagTuple = debug.systemjtag.map { j => - IOCell.generateIOFromSignal(j.jtag, Some("iocell_jtag"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(j.jtag, Some("iocell_jtag"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) } jtagTuple.map(_._1).foreach(_.suggestName("jtag")) val apbTuple = debug.apb.map { a => - IOCell.generateIOFromSignal(a, Some("iocell_apb"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(a, Some("iocell_apb"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) } apbTuple.map(_._1).foreach(_.suggestName("apb")) val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq) - }.getOrElse((Nil, Nil)) + }).getOrElse((Nil, Nil)) } +}) - /** - * Add IO cells to a serial module and name the IO ports. - * @param serial A SerialIO bundle - * @return Returns a tuple of (Top-level SerialIO IO; a list of IOCell module references) - */ - def serial(serial: SerialIO): (SerialIO, Seq[IOCell]) = { - val (port, ios) = IOCell.generateIOFromSignal(serial, Some("iocell_serial")) +class WithSerialIOCells extends OverrideIOBinder({ + (system: CanHavePeripherySerial) => system.serial.map({ s => + val sys = system.asInstanceOf[BaseSubsystem] + val (port, cells) = IOCell.generateIOFromSignal(s, Some("iocell_serial"), sys.p(IOCellKey)) + val serial_clock = Wire(Output(Clock())).suggestName("chiptop_serial_clock") + serial_clock := false.B.asClock // necessary for BoringUtils to work properly + dontTouch(serial_clock) + BoringUtils.bore(sys.fbus.module.clock, Seq(serial_clock)) + val (serial_clock_io, serial_clock_cell) = IOCell.generateIOFromSignal(serial_clock, Some("serial_clock"), sys.p(IOCellKey)) + serial_clock_io.suggestName("serial_clock") port.suggestName("serial") - (port, ios) - } - - def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { - io.zip(node.edges.in).zipWithIndex.map{ case ((mem_axi4, edge), i) => { - val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_slave_${i}")) - port.suggestName(s"${name}_axi4_slave_${i}") - (port, edge, ios) - }} - } - def axi4(io: Seq[AXI4Bundle], node: AXI4MasterNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { - io.zip(node.edges.out).zipWithIndex.map{ case ((mem_axi4, edge), i) => { - //val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_master_${i}")) - val port = IO(Flipped(AXI4Bundle(edge.bundle))) - val ios = IOCell.generateFromSignal(mem_axi4, port, Some(s"iocell_${name}_axi4_master_${i}")) - port.suggestName(s"${name}_axi4_master_${i}") - (port, edge, ios) - }} - } - - def blockDev(bdev: BlockDeviceIO): (BlockDeviceIO, Seq[IOCell]) = { - val (port, ios) = IOCell.generateIOFromSignal(bdev, Some("iocell_bdev")) - port.suggestName("bdev") - (port, ios) - } -} - -// DOC include start: WithGPIOTiedOff -class WithGPIOTiedOff extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => { - val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) - val harnessFn = (th: HasHarnessSignalReferences) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } - Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) - } -}) -// DOC include end: WithGPIOTiedOff - -class WithUARTAdapter extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { - val (ports, ioCells2d) = AddIOCells.uart(system.uart) - val harnessFn = (th: HasHarnessSignalReferences) => { UARTAdapter.connect(ports)(system.p); Nil } - Seq((ports, ioCells2d.flatten, Some(harnessFn))) - } + (Seq(port, serial_clock_io), cells ++ serial_clock_cell) + }).getOrElse((Nil, Nil)) }) -class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ - (system: HasPeripherySPIFlashModuleImp) => { - val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") - val harnessFn = (th: HasHarnessSignalReferences) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p); Nil } - Seq((ports, ioCells2d.flatten, Some(harnessFn))) - } -}) -class WithSimBlockDevice extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => - val (port, ios) = AddIOCells.blockDev(bdev) - val harnessFn = (th: HasHarnessSignalReferences) => { - // TODO: Using harness clock/reset will be incorrect when systemClock =/= harnessClock - SimBlockDevice.connect(th.harnessClock, th.harnessReset.asBool, Some(port))(system.p) - Nil - } - Seq((Seq(port), ios, Some(harnessFn))) - }.getOrElse(Nil) -}) - -class WithBlockDeviceModel extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => - val (port, ios) = AddIOCells.blockDev(bdev) - val harnessFn = (th: HasHarnessSignalReferences) => { - BlockDeviceModel.connect(Some(port))(system.p) - Nil - } - Seq((Seq(port), ios, Some(harnessFn))) - }.getOrElse(Nil) -}) - -class WithLoopbackNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil -}) - -class WithSimNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil -}) - -// DOC include start: WithSimAXIMem -class WithSimAXIMem extends OverrideIOBinder({ +class WithAXI4MemPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort) => { - implicit val p: Parameters = GetSystemParameters(system) - val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") - // TODO: we are inlining the connectMem method of SimAXIMem because - // it takes in a dut rather than seq of axi4 ports - val harnessFn = (th: HasHarnessSignalReferences) => { - peiTuples.map { case (port, edge, ios) => - val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) - Module(mem.module).suggestName("mem") - mem.io_axi4.head <> port - } - Nil + val clock = if (!system.mem_axi4.isEmpty) { + Some(BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock)) + } else { + None } - Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) - } -}) -// DOC include end: WithSimAXIMem - -class WithBlackBoxSimMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort) => { - implicit val p: Parameters = GetSystemParameters(system) - val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") - val harnessFn = (th: HasHarnessSignalReferences) => { - peiTuples.map { case (port, edge, ios) => - val memSize = p(ExtMem).get.master.size - val lineSize = p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) - mem.io.axi <> port - // TODO: Using harness clock/reset will be incorrect when systemClock =/= harnessClock - mem.io.clock := th.harnessClock - mem.io.reset := th.harnessReset - } - Nil - } - Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) + val ports = system.mem_axi4.map({ m => + val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mem") + p <> m + p + }) + (ports ++ clock, Nil) } }) -class WithSimAXIMMIO extends OverrideIOBinder({ +class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { - implicit val p: Parameters = GetSystemParameters(system) - val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem") - val harnessFn = (th: HasHarnessSignalReferences) => { - peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => - val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)) - Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") - mmio_mem.io_axi4.head <> port - } - Nil + val clock = if (!system.mmio_axi4.isEmpty) { + Some(BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock)) + } else { + None } - Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) + val ports = system.mmio_axi4.map({ m => + val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mmio") + p <> m + p + }) + (ports ++ clock, Nil) } }) +class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({ + (system: CanHaveSlaveAXI4Port) => { + val port = system.l2_frontend_bus_axi4.map { m => + val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_fbus") + p <> m + p + } + (port, Nil) + } +}) + +class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({ + (system: CanHavePeripheryBlockDeviceModuleImp) => { + val ports = system.bdev.map({ bdev => + val p = IO(new BlockDeviceIO()(system.p)).suggestName("blockdev") + val clock = BoreHelper("blkdev_clk", system.outer.controller.get.module.clock) + p <> bdev + Seq(p, clock) + }).getOrElse(Nil) + (ports, Nil) + } +}) + +class WithNICIOPunchthrough extends OverrideIOBinder({ + (system: CanHavePeripheryIceNICModuleImp) => { + val port = system.net.map({ n => + val p = IO(new NICIOvonly).suggestName("nic") + val clock = BoreHelper("nic_clk", system.outer.icenicOpt.get.module.clock) + p <> n + Seq(p, clock) + }).getOrElse(Nil) + (port.toSeq, Nil) + } +}) + +class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({ + (system: TraceGenSystemModuleImp) => { + val success = IO(Output(Bool())).suggestName("success") + success := system.success + (Seq(success), Nil) + } +}) + +class WithTraceIOPunchthrough extends OverrideIOBinder({ + (system: CanHaveTraceIOModuleImp) => { + val ports = system.traceIO.map { t => + val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace") + trace <> t + trace + } + (ports.toSeq, Nil) + } +}) + + class WithDontTouchPorts extends OverrideIOBinder({ - (system: DontTouch) => system.dontTouchPorts(); Nil + (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) }) -class WithTieOffInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp) => { - val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) - port.suggestName("interrupts") - val harnessFn = (th: HasHarnessSignalReferences) => { port := 0.U; Nil } - Seq((Seq(port), ioCells, Some(harnessFn))) - } -}) - -class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4Port) => { - val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus") - val harnessFn = (th: HasHarnessSignalReferences) => { - peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => - port := DontCare // tieoff doesn't completely tie-off, for some reason - port.tieoff() - } - Nil - } - Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) - } -}) - -class WithSimDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { - val (ports, iocells) = AddIOCells.debug(system)(system.p) - val harnessFn = (th: HasHarnessSignalReferences) => { - val dtm_success = WireInit(false.B) - when (dtm_success) { th.success := true.B } - ports.map { - case d: ClockedDMIIO => - val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success) - case j: JTAGIO => - val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) - case _ => - require(false, "We only support DMI or JTAG simulated debug connections") - } - Nil - } - Seq((ports, iocells, Some(harnessFn))) - } -}) - -class WithTiedOffDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { - val (ports, iocells) = AddIOCells.debug(system)(system.p) - val harnessFn = (th: HasHarnessSignalReferences) => { - ports.map { - case d: ClockedDMIIO => - d.dmi.req.valid := false.B - d.dmi.req.bits := DontCare - d.dmi.resp.ready := true.B - d.dmiClock := false.B.asClock - d.dmiReset := true.B - case j: JTAGIO => - j.TCK := true.B.asClock - j.TMS := true.B - j.TDI := true.B - j.TRSTn.foreach { r => r := true.B } - case a: ClockedAPBBundle => - a.tieoff() - a.clock := false.B.asClock - a.reset := true.B.asAsyncReset - a.psel := false.B - a.penable := false.B - case _ => require(false) - } - Nil - } - Seq((ports, iocells, Some(harnessFn))) - } -}) - -class WithTiedOffSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => - val (port, ioCells) = AddIOCells.serial(serial) - val harnessFn = (th: HasHarnessSignalReferences) => { - SerialAdapter.tieoff(port) - Nil - } - Seq((Seq(port), ioCells, Some(harnessFn))) - }).getOrElse(Nil) -}) - -class WithSimSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => - val (port, ioCells) = AddIOCells.serial(serial) - val harnessFn = (th: HasHarnessSignalReferences) => { - val ser_success = SerialAdapter.connectSimSerial(port, th.harnessClock, th.harnessReset) - when (ser_success) { th.success := true.B } - Nil - } - Seq((Seq(port), ioCells, Some(harnessFn))) - }).getOrElse(Nil) -}) - -class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp) => { - val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) - successPort.suggestName("success") - val harnessFn = (th: HasHarnessSignalReferences) => { when (successPort) { th.success := true.B }; Nil } - Seq((Seq(successPort), ioCells, Some(harnessFn))) - } -}) - -class WithSimDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => { - system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } - Nil - } -}) - - -} /* end package object */ diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index b296e328..67cf03bf 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -1,19 +1,22 @@ package chipyard import chisel3._ - +import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} -import chipyard.iobinders.{TestHarnessFunction} + +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} // ------------------------------- // Chipyard Test Harness // ------------------------------- -case object BuildTop extends Field[Parameters => LazyModule with HasTestHarnessFunctions]((p: Parameters) => new ChipTop()(p)) +case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p)) trait HasTestHarnessFunctions { - val harnessFunctions: Seq[TestHarnessFunction] + val lazySystem: LazyModule + val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] + val portMap = scala.collection.mutable.Map[String, Seq[Data]]() } trait HasHarnessSignalReferences { @@ -39,7 +42,9 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) - ldut.harnessFunctions.foreach(_(this)) - + ldut match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index a925ec56..950cb4b4 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -5,14 +5,40 @@ import freechips.rocketchip.config.{Config} // -------------- // Chipyard abstract ("base") configuration // NOTE: This configuration is NOT INSTANTIABLE, as it defines a empty system with no tiles +// +// The default set of IOBinders instantiate IOcells and ChipTop IOs for digital IO bundles. +// The default set of HarnessBinders instantiate TestHarness hardware for interacting with ChipTop IOs // -------------- class AbstractConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model - new chipyard.iobinders.WithSimDebug ++ // attach SimJTAG - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + // The HarnessBinders control generation of hardware in the TestHarness + new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present + new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled + new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled + new chipyard.harness.WithSimSerial ++ // add SimSerial adapter for HTIF, if serial port is present + new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present + new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled + new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled + new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present + new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present + + // The IOBinders instantiate ChipTop IOs to match desired digital IOs + // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ + new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ + new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ + new chipyard.iobinders.WithNICIOPunchthrough ++ + new chipyard.iobinders.WithSerialIOCells ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ + new chipyard.iobinders.WithGPIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ + new chipyard.iobinders.WithSPIIOCells ++ + new chipyard.iobinders.WithTraceIOPunchthrough ++ + new chipyard.iobinders.WithExtInterruptIOCells ++ + + new testchipip.WithTSI ++ // use testchipip serial offchip link new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 6bc7cf69..47e7c15b 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -13,7 +13,7 @@ class ArianeConfig extends Config( new chipyard.config.AbstractConfig) class dmiArianeConfig extends Config( - new chipyard.iobinders.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 575e1f98..9e1f558a 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -33,13 +33,13 @@ class HwachaLargeBoomConfig extends Config( new chipyard.config.AbstractConfig) class LoopbackNICLargeBoomConfig extends Config( - new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback new icenet.WithIceNIC ++ // build a NIC new boom.common.WithNLargeBooms(1) ++ new chipyard.config.AbstractConfig) class DromajoBoomConfig extends Config( - new chipyard.iobinders.WithSimDromajoBridge ++ // attach Dromajo + new chipyard.harness.WithSimDromajoBridge ++ // attach Dromajo new chipyard.config.WithTraceIO ++ // enable the traceio new boom.common.WithNSmallBooms(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 420ba192..a8686961 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config( // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.iobinders.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.harness.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -46,37 +46,36 @@ class GCDAXI4BlackBoxRocketConfig extends Config( // DOC include end: GCDAXI4BlackBoxRocketConfig class LargeSPIFlashROMRocketConfig extends Config( - new chipyard.iobinders.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) + new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) new chipyard.config.WithSPIFlash ++ // add the SPI flash controller new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class SmallSPIFlashRocketConfig extends Config( - new chipyard.iobinders.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) + new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class SimAXIRocketConfig extends Config( - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM + new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class SimBlockDeviceRocketConfig extends Config( - new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice + new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice new testchipip.WithBlockDevice ++ // add block-device module to peripherybus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class BlockDeviceModelRocketConfig extends Config( - new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel + new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel new testchipip.WithBlockDevice ++ // add block-device module to periphery bus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: GPIORocketConfig class GPIORocketConfig extends Config( - new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -111,7 +110,7 @@ class InitZeroRocketConfig extends Config( // DOC include end: InitZeroRocketConfig class LoopbackNICRocketConfig extends Config( - new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback new icenet.WithIceNIC ++ // add an IceNIC new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -170,8 +169,6 @@ class LargeNVDLARocketConfig extends Config( new chipyard.config.AbstractConfig) class MMIORocketConfig extends Config( - new chipyard.iobinders.WithTieOffL2FBusAXI ++ // Tie-off the incoming MMIO port - new chipyard.iobinders.WithSimAXIMMIO ++ // Attach a simulated memory to the outwards MMIO port new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 47d567fb..28bc5dcd 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -4,8 +4,10 @@ import freechips.rocketchip.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} class TraceGenConfig extends Config( - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.harness.WithBlackBoxSimMem ++ + new chipyard.harness.WithTraceGenSuccess ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ @@ -13,8 +15,10 @@ class TraceGenConfig extends Config( new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenConfig extends Config( - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.harness.WithBlackBoxSimMem ++ + new chipyard.harness.WithTraceGenSuccess ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ @@ -22,8 +26,10 @@ class NonBlockingTraceGenConfig extends Config( new freechips.rocketchip.groundtest.GroundTestBaseConfig) class BoomTraceGenConfig extends Config( - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.harness.WithBlackBoxSimMem ++ + new chipyard.harness.WithTraceGenSuccess ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ @@ -32,8 +38,10 @@ class BoomTraceGenConfig extends Config( new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2Config extends Config( - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.harness.WithBlackBoxSimMem ++ + new chipyard.harness.WithTraceGenSuccess ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ @@ -42,8 +50,10 @@ class NonBlockingTraceGenL2Config extends Config( new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2RingConfig extends Config( - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.harness.WithBlackBoxSimMem ++ + new chipyard.harness.WithTraceGenSuccess ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index d501b6c0..e7adbdc1 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -12,27 +12,16 @@ import freechips.rocketchip.config.{Config} // This file was originally developed for the cancelled ASPLOS-2020 // Chipyard tutorial. While the configs here work, the corresponding -// slideware has not yet been created +// slideware has not yet been created. // NOTE: Configs should be read bottom-up, since they are applied bottom-up +// NOTE: The TutorialConfigs build off of the AbstractConfig defined in AbstractConfig.scala +// Users should try to understand the functionality of the AbstractConfig before proceeding +// with the TutorialConfigs below + // Tutorial Phase 1: Configure the cores, caches class TutorialStarterConfig extends Config( - // IOBinders specify how to connect to IOs in our TestHarness - // These config fragments do not affect - new chipyard.iobinders.WithUARTAdapter ++ // Connect a SimUART adapter to display UART on stdout - new chipyard.iobinders.WithBlackBoxSimMem ++ // Connect simulated external memory - new chipyard.iobinders.WithTieOffInterrupts ++ // Do not simulate external interrupts - new chipyard.iobinders.WithSimDebug ++ // Connect SimJTAG (or SimDTM) widgets to debug ios - new chipyard.iobinders.WithSimSerial ++ // Connect external SimSerial widget to drive TSI - - // Config fragments below this line affect hardware generation - // of the Top - new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core - new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM - new chipyard.config.WithUART ++ // Add a UART - new chipyard.config.WithNoSubsystemDrivenClocks ++ // Don't drive the subsystem clocks from within the subsystem - // CUSTOMIZE THE CORE // Uncomment out one (or multiple) of the lines below, and choose // how many cores you want. @@ -43,36 +32,11 @@ class TutorialStarterConfig extends Config( // Uncomment this line, and specify a size if you want to have a L2 // new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++ - // Set the debug module to expose an external JTAG port - new freechips.rocketchip.subsystem.WithJtagDTM ++ - - // For simpler designs, we want to minimize IOs on - // our Top. These config fragments remove unnecessary - // ports - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - - // Use the standard hierarchical bus topology including mbus+l2 - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - - // BaseConfig configures "bare" rocketchip system - new freechips.rocketchip.system.BaseConfig + new chipyard.config.AbstractConfig ) - // Tutorial Phase 2: Integrate a TileLink or AXI4 MMIO device class TutorialMMIOConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimDebug ++ - new chipyard.iobinders.WithSimSerial ++ - - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ // Attach either a TileLink or AXI4 version of GCD // Uncomment one of the below lines @@ -81,66 +45,26 @@ class TutorialMMIOConfig extends Config( // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig + new chipyard.config.AbstractConfig ) -// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator +// // Tutorial Phase 3: Integrate a SHA3 RoCC accelerator class TutorialSha3Config extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimDebug ++ - new chipyard.iobinders.WithSimSerial ++ - - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo // new sha3.WithSha3Accel ++ // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig + new chipyard.config.AbstractConfig ) // Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator class TutorialSha3BlackBoxConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimDebug ++ - new chipyard.iobinders.WithSimSerial ++ - - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - // Uncomment these lines once SHA3 is integrated // new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl // new sha3.WithSha3Accel ++ // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig + new chipyard.config.AbstractConfig ) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index b59d477d..0eb61a05 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -8,13 +8,13 @@ import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.amba.axi4.{AXI4Bundle} import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp} import freechips.rocketchip.tile.{RocketTile} -import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp -import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} +import sifive.blocks.devices.uart._ -import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} -import icenet.CanHavePeripheryIceNICModuleImp +import testchipip._ +import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} @@ -25,73 +25,116 @@ import tracegen.{TraceGenSystemModuleImp} import ariane.ArianeTile import boom.common.{BoomTile} - -import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters} -import testchipip.{CanHaveTraceIOModuleImp} +import barstools.iocell.chisel._ +import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} +import chipyard.{HasHarnessSignalReferences} +import chipyard.harness._ object MainMemoryConsts { val regionNamePrefix = "MainMemory" def globalName = s"${regionNamePrefix}_${NodeIdx()}" } -class WithSerialBridge extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => - system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil +trait Unsupported { + require(false, "We do not support this IOCell type") +} + +class FireSimAnalogIOCell extends RawModule with AnalogIOCell with Unsupported +class FireSimDigitalGPIOCell extends RawModule with DigitalGPIOCell with Unsupported +class FireSimDigitalInIOCell extends RawModule with DigitalInIOCell { io.i := io.pad } +class FireSimDigitalOutIOCell extends RawModule with DigitalOutIOCell { io.pad := io.o } + +case class FireSimIOCellParams() extends IOCellTypeParams { + def analog() = Module(new FireSimAnalogIOCell) + def gpio() = Module(new FireSimDigitalGPIOCell) + def input() = Module(new FireSimDigitalInIOCell) + def output() = Module(new FireSimDigitalOutIOCell) +} + +class WithFireSimIOCellModels extends Config((site, here, up) => { + case IOCellKey => FireSimIOCellParams() }) -class WithNICBridge extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => - system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil +class WithSerialBridge extends OverrideHarnessBinder({ + (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val clock = ports.collectFirst({case c: Clock => c}) + val p: Parameters = chipyard.iobinders.GetSystemParameters(system) + ports.filter(_.isInstanceOf[SerialIO]).map { + case s: SerialIO => withClockAndReset(clock.get, th.harnessReset) { + SerialBridge(clock.get, s, MainMemoryConsts.globalName)(p) + } + case _ => + } + Nil + } }) -class WithUARTBridge extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => - system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil +class WithNICBridge extends OverrideHarnessBinder({ + (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val clock = ports.collectFirst({case c: Clock => c}) + ports.map { + case p: NICIOvonly => withClockAndReset(clock.get, th.harnessReset) { NICBridge(clock.get, p)(system.p) } + case _ => + } + Nil + } }) -class WithBlockDeviceBridge extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => - system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil +class WithUARTBridge extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => + ports.map { case p: UARTPortIO => UARTBridge(th.harnessClock, p)(system.p) }; Nil }) +class WithBlockDeviceBridge extends OverrideHarnessBinder({ + (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val clock = ports.collectFirst({case c: Clock => c}) + ports.map { + case p: BlockDeviceIO => BlockDevBridge(clock.get, p, th.harnessReset.toBool)(system.p) + case _ => + } + Nil + } +}) -class WithFASEDBridge extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort) => { +class WithFASEDBridge extends OverrideHarnessBinder({ + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { implicit val p: Parameters = GetSystemParameters(system) - (system.mem_axi4 zip system.memAXI4Node.edges.in).foreach({ case (axi4, edge) => + val clock = ports.collectFirst({case c: Clock => c}) + val axi4_ports = ports.collect { case p: AXI4Bundle => p } + (axi4_ports zip system.memAXI4Node.edges.in).map { case (axi4: AXI4Bundle, edge) => val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, axi4.ar.bits.addr.getWidth, axi4.ar.bits.id.getWidth) system match { - case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool, + case s: BaseSubsystem => FASEDBridge(clock.get, axi4, th.harnessReset.asBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)), Some(MainMemoryConsts.globalName))) case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design") } - }) + } Nil } }) -class WithTracerVBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => - system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil -}) - - - -class WithDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => { - system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil +class WithTracerVBridge extends ComposeHarnessBinder({ + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => + withClockAndReset(tileTrace.clock, tileTrace.reset) { TracerVBridge(tileTrace)(system.p) } + )} } }) +class WithDromajoBridge extends ComposeHarnessBinder({ + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => + ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil +}) -class WithTraceGenBridge extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp) => - GroundTestBridge(system.clock, system.success)(system.p); Nil + +class WithTraceGenBridge extends OverrideHarnessBinder({ + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => + ports.map { case p: Bool => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ @@ -105,52 +148,25 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ val core = b.module.core core.iregfile match { case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) - case _ => Nil } if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile)) - case _ => Nil } } case _ => } - Nil + (Nil, Nil) } }) -class WithTiedOffSystemGPIO extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => - system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil -}) - -class WithTiedOffSystemDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { - Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) - // tieoffDebug doesn't actually tie everything off :/ - system.debug.foreach { d => - d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) - d.dmactiveAck := DontCare - } - Nil - } -}) - -class WithTiedOffSystemInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp) => - system.interrupts := 0.U; Nil -}) - - // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new WithTiedOffSystemGPIO ++ - new WithTiedOffSystemDebug ++ - new WithTiedOffSystemInterrupts ++ new WithSerialBridge ++ new WithNICBridge ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ new WithFASEDBridge ++ new WithFireSimMultiCycleRegfile ++ - new WithTracerVBridge + new WithTracerVBridge ++ + new WithFireSimIOCellModels ) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 158674a0..d2ef4e60 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -13,8 +13,9 @@ import freechips.rocketchip.util.{ResetCatchAndSync} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} -import chipyard.{BuildSystem, BuildTop, HasHarnessSignalReferences, ChipyardSubsystem, ClockingSchemeKey, ChipTop} -import chipyard.iobinders.{IOBinders} +import chipyard._ +import chipyard.harness._ +import chipyard.iobinders._ // Determines the number of times to instantiate the DUT in the harness. // Subsumes legacy supernode support @@ -50,7 +51,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { chiptop.implicitClockSinkNode := implicitClockSourceNode // Drive the diplomaticclock graph of the DigitalTop (if present) - val simpleClockGroupSourceNode = chiptop.lSystem match { + val simpleClockGroupSourceNode = chiptop.lazySystem match { case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) l.asyncClockGroupsNode := n @@ -93,7 +94,7 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi chiptop.implicitClockSinkNode := implicitClockSourceNode // Drive the diplomaticclock graph of the DigitalTop (if present) - val simpleClockGroupSourceNode = chiptop.lSystem match { + val simpleClockGroupSourceNode = chiptop.lazySystem match { case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) l.asyncClockGroupsNode := n @@ -159,8 +160,13 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy }))) val module = Module(lazyModule.module) - require(lazyModule.harnessFunctions.size == 1, "There should only be 1 harness function to connect clock+reset") - lazyModule.harnessFunctions.foreach(_(this)) + lazyModule match { case d: HasTestHarnessFunctions => + require(d.harnessFunctions.size == 1, "There should only be 1 harness function to connect clock+reset") + d.harnessFunctions.foreach(_(this)) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } + + NodeIdx.increment() } } diff --git a/generators/icenet b/generators/icenet index 705ca506..bb23c81f 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 705ca50690383aa589dc560a5e7c152af04c46ad +Subproject commit bb23c81fcfbdfde6767c5b7daa95f8f9436fb7db diff --git a/generators/testchipip b/generators/testchipip index 1e7373f6..6f4e7ae2 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 1e7373f6398c198e2dee2bcf692917ec2ac21b53 +Subproject commit 6f4e7ae2c94e867f08cd0d408a106fba2f389de2 diff --git a/sims/firesim b/sims/firesim index 05edd6be..069c3c11 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 05edd6be8c0464ea53a664a2164d3eba6a7f62aa +Subproject commit 069c3c111d46a3f3d20b4bd6f17aaa9b23487cc7 diff --git a/tools/barstools b/tools/barstools index aa1c90c4..ba681676 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit aa1c90c4ccb73c2c379550f3296892cc81e8a195 +Subproject commit ba681676f338af158023c99b4c802009aa0b601b From 8eb807a2fdc4b2cf3397ac2ff7a1cbf316e6421a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 4 Sep 2020 18:55:56 -0700 Subject: [PATCH 161/457] Use DigitalTop in Platform | Use Chipyard BootRom --- fpga/Makefile | 30 +--------- fpga/bootrom/xip/Makefile | 50 ---------------- fpga/bootrom/xip/xip.S | 16 ------ fpga/src/main/scala/arty/Config.scala | 47 ++++++++------- fpga/src/main/scala/arty/FPGAChip.scala | 2 +- fpga/src/main/scala/arty/Platform.scala | 7 ++- fpga/src/main/scala/arty/System.scala | 57 ------------------- .../chipyard/src/main/scala/DigitalTop.scala | 8 +++ 8 files changed, 39 insertions(+), 178 deletions(-) delete mode 100644 fpga/bootrom/xip/Makefile delete mode 100644 fpga/bootrom/xip/xip.S delete mode 100644 fpga/src/main/scala/arty/System.scala diff --git a/fpga/Makefile b/fpga/Makefile index ab538116..835ffb59 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -21,9 +21,9 @@ SUB_PROJECT := fpga SBT_PROJECT := freedomPlatforms MODEL := E300ArtyDevKitFPGAChip VLOG_MODEL := E300ArtyDevKitFPGAChip -MODEL_PACKAGE := sifive.freedom.everywhere.e300artydevkit +MODEL_PACKAGE := chipyard.fpga CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := sifive.freedom.everywhere.e300artydevkit +CONFIG_PACKAGE := chipyard.fpga GENERATOR_PACKAGE := chipyard TB := none # unused TOP := E300ArtyDevKitPlatform @@ -34,7 +34,6 @@ BOARD ?= arty ######################################################################################### # misc. directories ######################################################################################### -bootrom_dir := $(base_dir)/fpga/bootrom/xip fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx fpga_common_script_dir := $(fpga_dir)/common/tcl @@ -49,27 +48,7 @@ include $(base_dir)/common.mk all_vsrcs := \ $(sim_vsrcs) \ $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ - $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v \ - $(build_dir)/$(long_name).rom.v - -######################################################################################### -# build rom for the fpga -######################################################################################### -# needed for bootrom makefile -export BUILD_DIR=$(build_dir) -export ROCKETCHIP_DIR -export LONG_NAME=$(long_name) -export ROMCONF=$(build_dir)/$(long_name).rom.conf - -romgen := $(build_dir)/$(long_name).rom.v -$(romgen): $(sim_vsrcs) -ifneq ($(bootrom_dir),"") - $(MAKE) -C $(bootrom_dir) romgen - mv $(build_dir)/rom.v $@ -endif - -.PHONY: romgen -romgen: $(romgen) + $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v ######################################################################################### # vivado rules @@ -119,6 +98,3 @@ prjx: $(prjx) .PHONY: clean clean: rm -rf $(gen_dir) -ifneq ($(bootrom_dir),"") - $(MAKE) -C $(bootrom_dir) clean -endif diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile deleted file mode 100644 index e51fd9c5..00000000 --- a/fpga/bootrom/xip/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# RISCV environment variable must be set -# needs the following variables -# LONG_NAME -# BUILD_DIR -# ROCKETCHIP_DIR -# ROMCONF - -CC=$(RISCV)/bin/riscv64-unknown-elf-gcc -OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy -CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g -LFLAGS=-static -nostdlib - -dtb := $(BUILD_DIR)/$(LONG_NAME).dtb -$(dtb): $(BUILD_DIR)/$(LONG_NAME).dts - dtc -I dts -O dtb -o $@ $< - -.PHONY: dtb -dtb: $(dtb) - -elf := $(BUILD_DIR)/xip.elf -$(elf): xip.S $(dtb) - $(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $< - -.PHONY: elf -elf: $(elf) - -bin := $(BUILD_DIR)/xip.bin -$(bin): $(elf) - $(OBJCOPY) -O binary $< $@ - -.PHONY: bin -bin: $(bin) - -hex := $(BUILD_DIR)/xip.hex -$(hex): $(bin) - od -t x4 -An -w4 -v $< > $@ - -.PHONY: hex -hex: $(hex) - -romgen := $(BUILD_DIR)/rom.v -$(romgen): $(hex) - $(ROCKETCHIP_DIR)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ - -.PHONY: romgen -romgen: $(romgen) - -.PHONY: clean -clean:: - rm -rf $(hex) $(elf) diff --git a/fpga/bootrom/xip/xip.S b/fpga/bootrom/xip/xip.S deleted file mode 100644 index 7445f4c9..00000000 --- a/fpga/bootrom/xip/xip.S +++ /dev/null @@ -1,16 +0,0 @@ -// See LICENSE for license details. -// Execute in place -// Jump directly to XIP_TARGET_ADDR - - .section .text.init - .option norvc - .globl _start -_start: - csrr a0, mhartid - la a1, dtb - li t0, XIP_TARGET_ADDR - jr t0 - - .section .rodata -dtb: - .incbin DEVICE_TREE diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala index 11642164..73fb8b31 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/Config.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit +package chipyard.fpga import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,16 +16,7 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ -// Default FreedomEConfig -class DefaultFreedomEConfig extends Config ( - new WithNBreakpoints(2) ++ - new WithNExtTopInterrupts(0) ++ - new WithJtagDTM ++ - new TinyConfig -) - -// Freedom E300 Arty Dev Kit Peripherals -class E300DevKitPeripherals extends Config((site, here, up) => { +class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) case PeripheryPWMKey => List( @@ -47,19 +38,27 @@ class E300DevKitPeripherals extends Config((site, here, up) => { I2CParams(address = 0x10016000)) case PeripheryMockAONKey => MockAONParams(address = 0x10000000) - case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM")) - case BootROMLocated(InSubsystem) => None + case DTSTimebase => BigInt(32768) + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = 2, + idcodePartNum = 0x000, + idcodeManufId = 0x489, + debugIdleCycles = 5) }) -// Freedom E300 Arty Dev Kit Peripherals class E300ArtyDevKitConfig extends Config( - new E300DevKitPeripherals ++ - new DefaultFreedomEConfig().alter((site,here,up) => { - case DTSTimebase => BigInt(32768) - case JtagDTMKey => new JtagDTMConfig ( - idcodeVersion = 2, - idcodePartNum = 0x000, - idcodeManufId = 0x489, - debugIdleCycles = 5) - }) -) + new E300DevKitExtra ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.With1TinyCore ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/arty/FPGAChip.scala b/fpga/src/main/scala/arty/FPGAChip.scala index e0b0634c..26e75500 100644 --- a/fpga/src/main/scala/arty/FPGAChip.scala +++ b/fpga/src/main/scala/arty/FPGAChip.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit +package chipyard.fpga import Chisel._ import chisel3.core.{attach} diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala index 14c31628..514ff74c 100644 --- a/fpga/src/main/scala/arty/Platform.scala +++ b/fpga/src/main/scala/arty/Platform.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit +package chipyard.fpga import Chisel._ @@ -20,6 +20,8 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.pinctrl._ +import chipyard.{DigitalTop} + //------------------------------------------------------------------------- // PinGen //------------------------------------------------------------------------- @@ -51,8 +53,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { //------------------------------------------------------------------------- class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { - //val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop? - val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) + val sys = Module(LazyModule(new DigitalTop).module) val io = new E300ArtyDevKitPlatformIO // This needs to be de-asserted synchronously to the coreClk. diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala deleted file mode 100644 index 46e5c34e..00000000 --- a/fpga/src/main/scala/arty/System.scala +++ /dev/null @@ -1,57 +0,0 @@ -// See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit - -import Chisel._ - -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.system._ - -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ - -//------------------------------------------------------------------------- -// E300ArtyDevKitSystem -//------------------------------------------------------------------------- - -class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem - with HasPeripheryDebug - with HasPeripheryMockAON - with chipyard.example.CanHavePeripheryGCD - with HasPeripheryUART - with HasPeripherySPIFlash - with HasPeripherySPI - with HasPeripheryGPIO - with HasPeripheryPWM - with HasPeripheryI2C { - val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } - val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - - val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]() - tileResetVectorNexusNode := maskROMResetVectorSourceNode - - override lazy val module = new E300ArtyDevKitSystemModule(this) -} - -class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L) - extends RocketSubsystemModuleImp(_outer) - with HasPeripheryDebugModuleImp - with chipyard.example.CanHavePeripheryGCDModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryGPIOModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp - with HasPeripheryPWMModuleImp - with HasPeripheryI2CModuleImp { - - // connect reset vector to 1st MaskROM - _outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U -} diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 81d0003d..160e6acf 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,6 +13,10 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem + with sifive.blocks.devices.mockaon.HasPeripheryMockAON + with sifive.blocks.devices.spi.HasPeripherySPI + with sifive.blocks.devices.pwm.HasPeripheryPWM + with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -31,6 +35,10 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) + with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp From 1fa1b6d57f1bc5dc0e2a1cbe248501af843f7e82 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 4 Sep 2020 19:03:26 -0700 Subject: [PATCH 162/457] Small makefile cleanup --- fpga/Makefile | 34 +++++++++++++--------------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index 835ffb59..e0882e63 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -31,6 +31,9 @@ TOP := E300ArtyDevKitPlatform # setup the board to use BOARD ?= arty +.PHONY: default +default: $(mcs) + ######################################################################################### # misc. directories ######################################################################################### @@ -53,44 +56,33 @@ all_vsrcs := \ ######################################################################################### # vivado rules ######################################################################################### -# combine all sources into single .F -f := $(build_dir)/$(long_name).vsrcs.F -$(f): $(sim_common_files) $(all_vsrcs) +# combine all sources into single .f +synth_list_f := $(build_dir)/$(long_name).vsrcs.f +$(synth_list_f): $(sim_common_files) $(all_vsrcs) $(foreach file,$(all_vsrcs),echo "$(file)" >> $@;) cat $(sim_common_files) >> $@ -bit := $(build_dir)/obj/$(MODEL).bit -$(bit): $(romgen) $(f) +BIT_FILE := $(build_dir)/obj/$(MODEL).bit +$(BIT_FILE): $(synth_list_f) cd $(build_dir); vivado \ -nojournal -mode batch \ -source $(fpga_common_script_dir)/vivado.tcl \ -tclargs \ -top-module "$(MODEL)" \ - -F "$(f)" \ + -F "$(synth_list_f)" \ -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ -board "$(BOARD)" .PHONY: bit -bit: $(bit) +bit: $(BIT_FILE) # Build .mcs -mcs := $(build_dir)/obj/$(MODEL).mcs -$(mcs): $(bit) +MCS_FILE := $(build_dir)/obj/$(MODEL).mcs +$(MCS_FILE): $(BIT_FILE) cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< .PHONY: mcs -mcs: $(mcs) - -######################################################################################### -# mircosemi rules -######################################################################################### -# Build Libero project -prjx := $(build_dir)/libero/$(MODEL).prjx -$(prjx): $(verilog) - cd $(build_dir); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(build_dir) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" - -.PHONY: prjx -prjx: $(prjx) +mcs: $(MCS_FILE) ######################################################################################### # general cleanup rules From b613c14f1c4cee96ee5abf181ee19df54494fd29 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 4 Sep 2020 20:03:12 -0700 Subject: [PATCH 163/457] Fix remaining HarnessBinders bugs --- .circleci/defaults.sh | 4 ++-- .../chipyard/src/main/scala/HarnessBinders.scala | 5 ++++- .../chipyard/src/main/scala/IOBinders.scala | 16 ++++++++-------- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 7ffb1d3c..703737cd 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -61,8 +61,8 @@ mapping["chipyard-ariane"]=" CONFIG=ArianeConfig" mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig" mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" -mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" -mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" +mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" +mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 54c99042..89017172 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -240,7 +240,10 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ class WithTiedOffSerial extends OverrideHarnessBinder({ (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { case p: SerialIO => SerialAdapter.tieoff(Some(p)) } + ports.map { + case p: SerialIO => SerialAdapter.tieoff(Some(p)) + case _ => + } Nil } }) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 0dad7e21..acd57207 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -270,8 +270,8 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({ } else { None } - val ports = system.mem_axi4.map({ m => - val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mem") + val ports = system.mem_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mem_${i}") p <> m p }) @@ -286,8 +286,8 @@ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ } else { None } - val ports = system.mmio_axi4.map({ m => - val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mmio") + val ports = system.mmio_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mmio_${i}") p <> m p }) @@ -297,11 +297,11 @@ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({ (system: CanHaveSlaveAXI4Port) => { - val port = system.l2_frontend_bus_axi4.map { m => - val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_fbus") - p <> m + val port = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_fbus_${i}") + m <> p p - } + }) (port, Nil) } }) From 9eb88c55fca24af5bcc8e1c63647e545fbde006b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 4 Sep 2020 23:07:23 -0700 Subject: [PATCH 164/457] Fix FireSim submodule --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 069c3c11..7cb10dcb 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 069c3c111d46a3f3d20b4bd6f17aaa9b23487cc7 +Subproject commit 7cb10dcb5eac4f2dc35ca8ee2bb0e1629fedd19b From ab21c53a42a4bd313c86a84b9c67abe7c77ee69d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 4 Sep 2020 23:49:40 -0700 Subject: [PATCH 165/457] Add documentation on HarnessBinders --- docs/Advanced-Concepts/Debugging-BOOM.rst | 13 +++-- docs/Advanced-Concepts/Top-Testharness.rst | 6 +- docs/Customization/IOBinders.rst | 58 ++++++++++--------- .../src/main/scala/HarnessBinders.scala | 2 + .../chipyard/src/main/scala/IOBinders.scala | 13 +---- 5 files changed, 46 insertions(+), 46 deletions(-) diff --git a/docs/Advanced-Concepts/Debugging-BOOM.rst b/docs/Advanced-Concepts/Debugging-BOOM.rst index 1e61804c..fd41a9d7 100644 --- a/docs/Advanced-Concepts/Debugging-BOOM.rst +++ b/docs/Advanced-Concepts/Debugging-BOOM.rst @@ -12,11 +12,14 @@ to verify functionality. Setting up Dromajo Co-simulation -------------------------------------- -Dromajo co-simulation is setup to work when two config fragments are added to a BOOM config. -First, a ``chipyard.config.WithTraceIO`` config fragment must be added so that BOOM's traceport is enabled. -Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config fragment must be added to -connect the Dromajo co-simulator to the traceport. -Once both config fragments are added Dromajo should be enabled. +Dromajo co-simulation is setup to work when three config fragments are added to a BOOM config. + + * A ``chipyard.config.WithTraceIO`` config fragment must be added so that BOOM's traceport is enabled. + * A ``chipyard.iobinders.WithTraceIOPunchthrough`` config fragment must be added to add the ``TraceIO`` to the ``ChipTop`` + * A ``chipyard.harness.WithSimDromajoBridge`` config fragment must be added to instantiate a Dromajo cosimulator in the ``TestHarness`` and connect it to the ``ChipTop``'s ``TraceIO`` + + +Once all config fragments are added Dromajo should be enabled. To build/run Dromajo with a BOOM design, run your configuration the following make commands: diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index ebd5b370..43a8a338 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -14,9 +14,9 @@ ChipTop/DUT ``ChipTop`` is the top-level module that instantiates the ``System`` submodule, usually an instance of the concrete class ``DigitalTop``. The vast majority of the design resides in the ``System``. Other components that exist inside the ``ChipTop`` layer are generally IO cells, clock receivers and multiplexers, reset synchronizers, and other analog IP that needs to exist outside of the ``System``. -The ``IOBinders`` are responsible for instantiating the IO cells and defining the test harness collateral that connects to the top-level ports. -Most of these types of devices can be instantiated using custom ``IOBinders``, so the provided ``ChipTop`` and ``ChipTopCaughtReset`` classes are sufficient. -However, if needed, the ``BaseChipTop`` abstract class can be extended for building more custom ``ChipTop`` designs. +The ``IOBinders`` are responsible for instantiating the IO cells for ``ChipTop`` IO that correspond to IO of the ``System``. +The ``HarnessBinders`` are responsible for instantiating test harness collateral that connects to the ``ChipTop`` ports. +Most types of devices and testing collateral can be instantiated using custom ``IOBinders`` and ``HarnessBinders``. System/DigitalTop diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 6332d07a..55920cd3 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -1,41 +1,45 @@ +IOBinders and HarnessBinders +============================ + +In Chipyard we use special ``Parameters`` keys, ``IOBinders`` and ``HarnessBinders`` to bridge the gap between digital system IOs and TestHarness collateral. + IOBinders ========= -In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to instantiate IO cells in the ``ChipTop`` layer and determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. +The ``IOBinder`` functions are responsible for instantiating IO cells and IOPorts in the ``ChipTop`` layer. + +``IOBinders`` are typically defined using the ``OverrideIOBinder`` or ``ComposeIOBinder`` macros. An ``IOBInder`` consists of a function matching ``Systems`` with a given trait that generates IO ports and IOCells, and returns a list of generated ports and cells. + +For example, the ``WithUARTIOCells`` IOBinder specifies will, for any ``System`` that might have UART ports (``HasPeripheryUARTModuleIMP``, generate ports within the ``ChipTop`` (``ports``) as well as IOCells with the appropriate type and direction (``cells2d``). This function returns a the list of generated ports, and the list of generate IOCells. The list of generated ports is passed to the ``HarnessBinders`` such that they can be connected to ``TestHarness`` devices. + .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala :language: scala - :start-after: DOC include start: IOBinders - :end-before: DOC include end: IOBinders + :start-after: DOC include start: WithUARTIOCells + :end-before: DOC include end: WithUARTIOCells +HarnessBinders +============== -This special key solves the problem of duplicating test-harnesses for each different ``System`` type. -You could just as well create a custom harness module that attaches IOs explicitly. -Instead, the ``IOBinders`` key provides a map from Scala traits to attachment behaviors. -Each ``IOBinder`` returns a tuple of three values: the list of ``ChipTop`` ports created by the ``IOBinder``, the list of all IO cell modules instantiated by the ``IOBinder``, and an optional function to be called inside the test harness. -This function is responsible for instantiating logic inside the ``TestHarness`` to appropriately drive the ``ChipTop`` IO ports created by the ``IOBinder``. -Conveniently, because the ``IOBinder`` is generating the port, it may also use the port inside this function, which prevents the ``BaseChipTop`` code from ever needing to access the port ``val``, thus having the ``IOBinder`` house all port specific code. -This scheme prevents the need to have two separate binder functions for each ``System`` trait. -When creating custom ``IOBinders`` it is important to use ``suggestName`` to name ports; otherwise Chisel will raise an exception trying to name the IOs. -The example ``IOBinders`` demonstrate this. +The ``HarnessBinder`` functions determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. The ``HarnessBinder`` interface is designed to be reused across various simulation modes, enabling decoupling of the target design from simulation and testing concerns. -As an example, the ``WithGPIOTiedOff`` IOBinder creates IO cells for the GPIO module(s) instantiated in the ``System``, then punches out new ``Analog`` ports for each one. -The test harness simply ties these off, but additional logic could be inserted to perform some kind of test in the ``TestHarness``. + * For SW RTL simulations, the default set of ``HarnessBinders`` instantiate software-simulated models of various devices, for example external memory or UART, and connect those models to the IOs of the ``ChipTop``. + * For FireSim simulations, FireSim-specific ``HarnessBinders`` instantiate ``Bridges``, which faciliate cycle-accurate simulation across the simulated chip's IOs. See the FireSim documentation for more details. + * In the future, a Chipyard FPGA prototyping flow may use ``HarnessBinders`` to connect ``ChipTop`` IOs to other devices or IOs in the FPGA harness. -.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala +For FireSim simulations, the ``HarnessBinder`` attach ``Bridge`` modules (See the FireSim documentation for more details). + +Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarnessBinder, ComposeHarnessBinder``), and matches ``Systems`` with a given trait. However, ``HarnessBinders`` are also passed a reference to the ``TestHarness`` (``th: HasHarnessSignalReferences``) and the list of ports generated by the corresponding ``IOBinder`` (``ports: Seq[Data]``). + +For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to the ports generated by the ``WithUARTIOCells`` described earlier, if those ports are present. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala :language: scala - :start-after: DOC include start: WithGPIOTiedOff - :end-before: DOC include end: WithGPIOTiedOff + :start-after: DOC include start: WithUARTAdapter + :end-before: DOC include end: WithUARTAdapter +The ``IOBinder`` and ``HarnesBinder`` system is designed to enable decoupling of concerns between target design and simulation ssystem. -``IOBinders`` also do not need to create ports. Some ``IOBinders`` can simply insert circuitry inside the ``ChipTop`` layer. -For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``System`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected inside ``ChipTop``. +For a given set of chip IOs, there may be not only multiple simulation platforms ("harnesses", so-to-speak), but also multiple simulation strategies. For example, the choice of whether to connect the backing AXI4 memory port to a accurate DRAM model (``SimDRAM``) or a simple simulated memory model (``SimAXIMem``) is isolated in ``HarnessBinders``, and does not affect target RTL generation. -.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala - :language: scala - :start-after: DOC include start: WithSimAXIMem - :end-before: DOC include end: WithSimAXIMem - -These classes are all ``Config`` objects, which can be mixed into the configs to specify IO connection behaviors. - -There are two macros for generating these ``Config``s. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. +Similarly, for a given simulation platform and strategy, there may be multiple strategies for generating the chip IOs. This target-design configuration is isolated in the ``IOBinders``. diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 89017172..a26b5104 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -66,12 +66,14 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({ } }) +// DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { UARTAdapter.connect(ports.map(_.asInstanceOf[UARTPortIO]))(system.p) Nil } }) +// DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index acd57207..db5c7008 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -40,13 +40,6 @@ import scala.reflect.{ClassTag} // You can add your own binder by adding a new (key, fn) pair, typically by using // the OverrideIOBinder or ComposeIOBinder macros - - -// DOC include start: IOBinders -// This type describes a function callable on the TestHarness instance. Its return type is unused. - - - case object IOBinders extends Field[Map[String, (Any) => (Seq[Data], Seq[IOCell])]]( Map[String, (Any) => (Seq[Data], Seq[IOCell])]().withDefaultValue((Any) => (Nil, Nil)) ) @@ -59,7 +52,6 @@ object ApplyIOBinders { } } - // Note: The parameters instance is accessible only through LazyModule // or LazyModuleImpLike. The self-type requirement in traits like // CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder @@ -116,8 +108,6 @@ object BoreHelper { } } -// DOC include end: IOBinders - case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) @@ -140,7 +130,7 @@ class WithGPIOCells extends OverrideIOBinder({ } }) - +// DOC include start: WithUARTIOCells class WithUARTIOCells extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { val (ports, cells2d) = system.uart.zipWithIndex.map({ case (u, i) => @@ -151,6 +141,7 @@ class WithUARTIOCells extends OverrideIOBinder({ (ports, cells2d.flatten) } }) +// DOC include end: WithUARTIOCells class WithSPIIOCells extends OverrideIOBinder({ (system: HasPeripherySPIFlashModuleImp) => { From 927244bf2e724c01b42a59dc297942ba12bdaa39 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 5 Sep 2020 11:16:55 -0700 Subject: [PATCH 166/457] DTM only supports HTIF in DMI mode --- generators/chipyard/src/main/scala/Subsystem.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 7f089ce1..92753db5 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -31,7 +31,7 @@ trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { case _: CanHavePeripherySerial if p(SerialKey) => true - case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true + case _: HasPeripheryDebug if p(ExportDebug).dmi => true case _ => false }) { ResourceBinding { From 11dcd71a48161ea1e0fb78225c6fb778ad50936d Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 6 Sep 2020 23:06:00 -0700 Subject: [PATCH 167/457] Clean up 5-stage instruction fetch --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 4c3bab58..e635b4ae 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 4c3bab5885b7d9f3ce0d621c0c2918aa853e879c +Subproject commit e635b4ae41d3d5ac570b8766877003e1c60f48ff From 7ed02a7d385921a22e88fa1e77dc411d16a732c8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 7 Sep 2020 11:36:37 -0700 Subject: [PATCH 168/457] Fix Typos --- docs/Customization/IOBinders.rst | 12 ++++++------ generators/chipyard/src/main/scala/TestHarness.scala | 6 +++--- .../src/main/scala/config/TutorialConfigs.scala | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 55920cd3..adfac22b 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -10,7 +10,7 @@ The ``IOBinder`` functions are responsible for instantiating IO cells and IOPort ``IOBinders`` are typically defined using the ``OverrideIOBinder`` or ``ComposeIOBinder`` macros. An ``IOBInder`` consists of a function matching ``Systems`` with a given trait that generates IO ports and IOCells, and returns a list of generated ports and cells. -For example, the ``WithUARTIOCells`` IOBinder specifies will, for any ``System`` that might have UART ports (``HasPeripheryUARTModuleIMP``, generate ports within the ``ChipTop`` (``ports``) as well as IOCells with the appropriate type and direction (``cells2d``). This function returns a the list of generated ports, and the list of generate IOCells. The list of generated ports is passed to the ``HarnessBinders`` such that they can be connected to ``TestHarness`` devices. +For example, the ``WithUARTIOCells`` IOBinder will, for any ``System`` that might have UART ports (``HasPeripheryUARTModuleImp``, generate ports within the ``ChipTop`` (``ports``) as well as IOCells with the appropriate type and direction (``cells2d``). This function returns a the list of generated ports, and the list of generated IOCells. The list of generated ports is passed to the ``HarnessBinders`` such that they can be connected to ``TestHarness`` devices. .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala @@ -21,15 +21,15 @@ For example, the ``WithUARTIOCells`` IOBinder specifies will, for any ``System`` HarnessBinders ============== -The ``HarnessBinder`` functions determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. The ``HarnessBinder`` interface is designed to be reused across various simulation modes, enabling decoupling of the target design from simulation and testing concerns. +The ``HarnessBinder`` functions determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. The ``HarnessBinder`` interface is designed to be reused across various simulation/implementation modes, enabling decoupling of the target design from simulation and testing concerns. * For SW RTL simulations, the default set of ``HarnessBinders`` instantiate software-simulated models of various devices, for example external memory or UART, and connect those models to the IOs of the ``ChipTop``. * For FireSim simulations, FireSim-specific ``HarnessBinders`` instantiate ``Bridges``, which faciliate cycle-accurate simulation across the simulated chip's IOs. See the FireSim documentation for more details. * In the future, a Chipyard FPGA prototyping flow may use ``HarnessBinders`` to connect ``ChipTop`` IOs to other devices or IOs in the FPGA harness. -For FireSim simulations, the ``HarnessBinder`` attach ``Bridge`` modules (See the FireSim documentation for more details). +For FireSim simulations, the ``HarnessBinder`` attaches ``Bridge`` modules (See the FireSim documentation for more details). -Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarnessBinder, ComposeHarnessBinder``), and matches ``Systems`` with a given trait. However, ``HarnessBinders`` are also passed a reference to the ``TestHarness`` (``th: HasHarnessSignalReferences``) and the list of ports generated by the corresponding ``IOBinder`` (``ports: Seq[Data]``). +Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarnessBinder, ComposeHarnessBinder``), and match ``Systems`` with a given trait. However, ``HarnessBinders`` are also passed a reference to the ``TestHarness`` (``th: HasHarnessSignalReferences``) and the list of ports generated by the corresponding ``IOBinder`` (``ports: Seq[Data]``). For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to the ports generated by the ``WithUARTIOCells`` described earlier, if those ports are present. @@ -38,8 +38,8 @@ For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to :start-after: DOC include start: WithUARTAdapter :end-before: DOC include end: WithUARTAdapter -The ``IOBinder`` and ``HarnesBinder`` system is designed to enable decoupling of concerns between target design and simulation ssystem. +The ``IOBinder`` and ``HarnessBinder`` system is designed to enable decoupling of concerns between the target design and the simulation system. -For a given set of chip IOs, there may be not only multiple simulation platforms ("harnesses", so-to-speak), but also multiple simulation strategies. For example, the choice of whether to connect the backing AXI4 memory port to a accurate DRAM model (``SimDRAM``) or a simple simulated memory model (``SimAXIMem``) is isolated in ``HarnessBinders``, and does not affect target RTL generation. +For a given set of chip IOs, there may be not only multiple simulation platforms ("harnesses", so-to-speak), but also multiple simulation strategies. For example, the choice of whether to connect the backing AXI4 memory port to an accurate DRAM model (``SimDRAM``) or a simple simulated memory model (``SimAXIMem``) is isolated in ``HarnessBinders``, and does not affect target RTL generation. Similarly, for a given simulation platform and strategy, there may be multiple strategies for generating the chip IOs. This target-design configuration is isolated in the ``IOBinders``. diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 67cf03bf..2faff565 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -31,8 +31,8 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign val success = Output(Bool()) }) - val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") - val dut = Module(ldut.module) + val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") + val dut = Module(lazyDut.module) io.success := false.B val harnessClock = clock @@ -42,7 +42,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) - ldut match { case d: HasTestHarnessFunctions => + lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) } diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index e7adbdc1..3c64958f 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -48,7 +48,7 @@ class TutorialMMIOConfig extends Config( new chipyard.config.AbstractConfig ) -// // Tutorial Phase 3: Integrate a SHA3 RoCC accelerator +// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator class TutorialSha3Config extends Config( // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo // new sha3.WithSha3Accel ++ From a8083aa5709d9c17591de3d55bd146cba6ced532 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 7 Sep 2020 11:47:37 -0700 Subject: [PATCH 169/457] First pass at fpga-shells with IOBinders --- build.sbt | 6 +- common.mk | 2 +- fpga/Makefile | 12 +- fpga/src/main/scala/arty/Config.scala | 3 +- fpga/src/main/scala/arty/FPGAChip.scala | 193 ----------- fpga/src/main/scala/arty/IOBinders.scala | 357 +++++++++++++++++++++ fpga/src/main/scala/arty/Platform.scala | 180 ----------- fpga/src/main/scala/arty/TestHarness.scala | 34 ++ 8 files changed, 403 insertions(+), 384 deletions(-) delete mode 100644 fpga/src/main/scala/arty/FPGAChip.scala create mode 100644 fpga/src/main/scala/arty/IOBinders.scala delete mode 100644 fpga/src/main/scala/arty/Platform.scala create mode 100644 fpga/src/main/scala/arty/TestHarness.scala diff --git a/build.sbt b/build.sbt index 31bb3f88..ffe8bfe8 100644 --- a/build.sbt +++ b/build.sbt @@ -217,10 +217,10 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testGrouping in Test := isolateAllTests( (definedTests in Test).value ), testOptions in Test += Tests.Argument("-oF") ) -lazy val fpgaShells = (project in file("./fpga/fpga-shells")) +lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) -lazy val freedomPlatforms = (project in file("./fpga")) - .dependsOn(chipyard, fpgaShells) +lazy val fpga_platforms = (project in file("./fpga")) + .dependsOn(chipyard, fpga_shells) .settings(commonSettings) diff --git a/common.mk b/common.mk index 89ebbea3..ee290ddc 100644 --- a/common.mk +++ b/common.mk @@ -58,7 +58,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk # Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources diff --git a/fpga/Makefile b/fpga/Makefile index e0882e63..0110bb10 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -18,15 +18,15 @@ include $(base_dir)/variables.mk # default variables to build the arty example SUB_PROJECT := fpga -SBT_PROJECT := freedomPlatforms -MODEL := E300ArtyDevKitFPGAChip -VLOG_MODEL := E300ArtyDevKitFPGAChip -MODEL_PACKAGE := chipyard.fpga +SBT_PROJECT := fpga_platforms +MODEL := ArtyFPGATestHarness +VLOG_MODEL := ArtyFPGATestHarness +MODEL_PACKAGE := chipyard.fpga.arty CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := chipyard.fpga +CONFIG_PACKAGE := chipyard.fpga.arty GENERATOR_PACKAGE := chipyard TB := none # unused -TOP := E300ArtyDevKitPlatform +TOP := ChipTop # setup the board to use BOARD ?= arty diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala index 73fb8b31..bcea7c78 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/Config.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga +package chipyard.fpga.arty import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -47,6 +47,7 @@ class E300DevKitExtra extends Config((site, here, up) => { }) class E300ArtyDevKitConfig extends Config( + new WithE300Connections ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/FPGAChip.scala b/fpga/src/main/scala/arty/FPGAChip.scala deleted file mode 100644 index 26e75500..00000000 --- a/fpga/src/main/scala/arty/FPGAChip.scala +++ /dev/null @@ -1,193 +0,0 @@ -// See LICENSE for license details. -package chipyard.fpga - -import Chisel._ -import chisel3.core.{attach} -import chisel3.experimental.{withClockAndReset} - -import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.spi._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -//------------------------------------------------------------------------- -// E300ArtyDevKitFPGAChip -//------------------------------------------------------------------------- - -class E300ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell { - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(clock_8MHz, ~mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - - withClockAndReset(clock_32MHz, ck_rst) { - val dut = Module(new E300ArtyDevKitPlatform) - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(qspi_sck, dut.io.pins.qspi.sck) - IOBUF(qspi_cs, dut.io.pins.qspi.cs(0)) - - IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0)) - IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1)) - IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2)) - IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt - - IOBUF(jd_5, dut.io.pins.jtag.TMS) - PULLUP(jd_5) - - IOBUF(jd_4, dut.io.pins.jtag.TDI) - PULLUP(jd_4) - - IOBUF(jd_0, dut.io.pins.jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - SRST_n := IOBUF(jd_6) - PULLUP(jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz) - dut.io.jtag_reset := jtag_power_on_reset - - // debug reset - dut_ndreset := dut.io.ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval - iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(sw_3) - dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie) - - IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(ck_io(2), dut.io.pins.gpio.pins(18)) - IOBUF(ck_io(3), dut.io.pins.gpio.pins(19)) // PWM1(1) - IOBUF(ck_io(4), dut.io.pins.gpio.pins(20)) // PWM1(0) - IOBUF(ck_io(5), dut.io.pins.gpio.pins(21)) // PWM1(2) - IOBUF(ck_io(6), dut.io.pins.gpio.pins(22)) // PWM1(3) - IOBUF(ck_io(7), dut.io.pins.gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(ck_io(8), dut.io.pins.gpio.pins(0)) // PWM0(0) - IOBUF(ck_io(9), dut.io.pins.gpio.pins(1)) // PWM0(1) - IOBUF(ck_io(10), dut.io.pins.gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(ck_io(11), dut.io.pins.gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(ck_io(12), dut.io.pins.gpio.pins(4)) // SPI MISO - IOBUF(ck_io(13), dut.io.pins.gpio.pins(5)) // SPI SCK - - dut.io.pins.gpio.pins(6).i.ival := 0.U - dut.io.pins.gpio.pins(7).i.ival := 0.U - dut.io.pins.gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(ck_io(15), dut.io.pins.gpio.pins(9)) // A1 = CS(2) - IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1) - IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(led0_r, dut.io.pins.gpio.pins(1)) - IOBUF(led0_g, dut.io.pins.gpio.pins(2)) - IOBUF(led0_b, dut.io.pins.gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(led1_r, dut.io.pins.gpio.pins(19)) - IOBUF(led1_g, dut.io.pins.gpio.pins(21)) - IOBUF(led1_b, dut.io.pins.gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(led2_r, dut.io.pins.gpio.pins(11)) - IOBUF(led2_g, dut.io.pins.gpio.pins(12)) - IOBUF(led2_b, dut.io.pins.gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(btn_0, dut.io.pins.gpio.pins(15)) - IOBUF(btn_1, dut.io.pins.gpio.pins(30)) - IOBUF(btn_2, dut.io.pins.gpio.pins(31)) - - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe - attach(btn_3, iobuf_btn_3.io.IO) - dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX - IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(ck_ss, dut.io.pins.gpio.pins(26)) - IOBUF(ck_mosi, dut.io.pins.gpio.pins(27)) - IOBUF(ck_miso, dut.io.pins.gpio.pins(28)) - IOBUF(ck_sck, dut.io.pins.gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(led_0, ck_rst) - IOBUF(led_1, SRST_n) - IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival) - IOBUF(led_3, dut.io.pins.gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - dut.io.pins.aon.erst_n.i.ival := ~reset_periph - dut.io.pins.aon.lfextclk.i.ival := slow_clock - dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U - } -} diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala new file mode 100644 index 00000000..e8833827 --- /dev/null +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -0,0 +1,357 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{attach, IO} + +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.subsystem.{NExtTopInterrupts} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pinctrl._ + +import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + +import chipsalliance.rocketchip.config._ + +import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} +import chipyard.{HasHarnessSignalReferences} + +class WithE300Connections extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp + with HasPeripheryUARTModuleImp + with HasPeripherySPIModuleImp + with HasPeripheryDebugModuleImp + with HasPeripheryPWMModuleImp + with HasPeripherySPIFlashModuleImp + with HasPeripheryMockAONModuleImp + with HasPeripheryI2CModuleImp) => { + // match the E300 connections using a "Chipyard"-like structure + + implicit val p: Parameters = GetSystemParameters(system) + + object PinGen { + def apply(): BasePin = { + val pin = new BasePin() + pin + } + } + + val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") + val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") + val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") + val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") + val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") + val io_ndreset = IO(Output(Bool())).suggestName("ndreset") + + // TODO: Fix + // add iocells (or none) + // This needs to be de-asserted synchronously to the coreClk. + val async_corerst = system.aon.rsts.corerst + // Add in debug-controlled reset. + system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) + Debug.connectDebugClockAndReset(system.debug, system.clock) + + //----------------------------------------------------------------------- + // Check for unsupported rocket-chip connections + //----------------------------------------------------------------------- + + require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); + + //----------------------------------------------------------------------- + // Build GPIO Pin Mux + //----------------------------------------------------------------------- + // Pin Mux for UART, SPI, PWM + // First convert the System outputs into "IOF" using the respective *GPIOPort + // converters. + + val sys_uart = system.uart + val sys_pwm = system.pwm + val sys_spi = system.spi + val sys_i2c = system.i2c + + val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} + val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} + val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} + val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} + + (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} + (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } + (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} + (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} + + //----------------------------------------------------------------------- + // Default Pin connections before attaching pinmux + + for (iof_0 <- system.gpio(0).iof_0.get) { + iof_0.default() + } + + for (iof_1 <- system.gpio(0).iof_1.get) { + iof_1.default() + } + + //----------------------------------------------------------------------- + + val iof_0 = system.gpio(0).iof_0.get + val iof_1 = system.gpio(0).iof_1.get + + // SPI1 (0 is the dedicated) + BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) + BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) + BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) + BasePinToIOF(spi_pins(0).sck, iof_0(5)) + BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) + BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) + BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) + BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) + BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) + + // SPI2 + BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) + BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) + BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) + BasePinToIOF(spi_pins(1).sck, iof_0(29)) + BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) + BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) + + // I2C + if (p(PeripheryI2CKey).length == 1) { + BasePinToIOF(i2c_pins(0).sda, iof_0(12)) + BasePinToIOF(i2c_pins(0).scl, iof_0(13)) + } + + // UART0 + BasePinToIOF(uart_pins(0).rxd, iof_0(16)) + BasePinToIOF(uart_pins(0).txd, iof_0(17)) + + // UART1 + BasePinToIOF(uart_pins(1).rxd, iof_0(24)) + BasePinToIOF(uart_pins(1).txd, iof_0(25)) + + //PWM + BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) + BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) + BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) + BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) + + BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) + BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) + BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) + BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) + + BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) + BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) + BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) + BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) + + //----------------------------------------------------------------------- + // Drive actual Pads + //----------------------------------------------------------------------- + + // Result of Pin Mux + GPIOPinsFromPort(io_gpio, system.gpio(0)) + + // Dedicated SPI Pads + SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) + + // JTAG Debug Interface + val sjtag = system.debug.get.systemjtag.get + JTAGPinsFromPort(io_jtag, sjtag.jtag) + sjtag.reset := io_jtag_reset + sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + + io_ndreset := system.debug.get.ndreset + + // AON Pads -- direct connection is OK because + // EnhancedPin is hard-coded in MockAONPads + // and thus there is no .fromPort method. + io_aon <> system.aon.pins + + val harnessFn = (baseTh: HasHarnessSignalReferences) => { + baseTh match { case th: ArtyShell => + + //----------------------------------------------------------------------- + // Clock divider + //----------------------------------------------------------------------- + val slow_clock = Wire(Bool()) + + // Divide clock by 256, used to generate 32.768 kHz clock for AON block + withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { + val clockToggleReg = RegInit(false.B) + val (_, slowTick) = chisel3.util.Counter(true.B, 256) + when (slowTick) {clockToggleReg := ~clockToggleReg} + slow_clock := clockToggleReg + } + + //----------------------------------------------------------------------- + // DUT + //----------------------------------------------------------------------- + withClockAndReset(th.clock_32MHz, th.ck_rst) { + + //--------------------------------------------------------------------- + // SPI flash IOBUFs + //--------------------------------------------------------------------- + + IOBUF(th.qspi_sck, io_qspi.sck) + IOBUF(th.qspi_cs, io_qspi.cs(0)) + + IOBUF(th.qspi_dq(0), io_qspi.dq(0)) + IOBUF(th.qspi_dq(1), io_qspi.dq(1)) + IOBUF(th.qspi_dq(2), io_qspi.dq(2)) + IOBUF(th.qspi_dq(3), io_qspi.dq(3)) + + //--------------------------------------------------------------------- + // JTAG IOBUFs + //--------------------------------------------------------------------- + + io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + + IOBUF(th.jd_5, io_jtag.TMS) + PULLUP(th.jd_5) + + IOBUF(th.jd_4, io_jtag.TDI) + PULLUP(th.jd_4) + + IOBUF(th.jd_0, io_jtag.TDO) + + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) + + // jtag reset + val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) + io_jtag_reset := jtag_power_on_reset + + // debug reset + th.dut_ndreset := io_ndreset + + //--------------------------------------------------------------------- + // Assignment to package pins + //--------------------------------------------------------------------- + // Pins IO0-IO13 + // + // FTDI UART TX/RX are not connected to th.ck_io[0,1] + // the way they are on Arduino boards. We copy outgoing + // data to both places, switch 3 (sw[3]) determines whether + // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) + + val iobuf_ck0 = Module(new IOBUF()) + iobuf_ck0.io.I := io_gpio.pins(16).o.oval + iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe + attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX + + val iobuf_uart_txd = Module(new IOBUF()) + iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval + iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe + attach(iobuf_uart_txd.io.IO, th.uart_txd_in) + + // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] + val sw_3_in = IOBUF(th.sw_3) + io_gpio.pins(16).i.ival := Mux(sw_3_in, + iobuf_ck0.io.O & io_gpio.pins(16).o.ie, + iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) + + IOBUF(th.uart_rxd_out, io_gpio.pins(17)) + + // Shield header row 0: PD2-PD7 + IOBUF(th.ck_io(2), io_gpio.pins(18)) + IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) + IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) + IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) + IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) + IOBUF(th.ck_io(7), io_gpio.pins(23)) + + // Header row 1: PB0-PB5 + IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) + IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) + IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) + IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) + IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO + IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK + + io_gpio.pins(6).i.ival := 0.U + io_gpio.pins(7).i.ival := 0.U + io_gpio.pins(8).i.ival := 0.U + + // Header row 3: A0-A5 (we don't support using them as analog inputs) + // just treat them as regular digital GPIOs + IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) + IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) + IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) + IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA + IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL + + // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty + // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active + IOBUF(th.led0_r, io_gpio.pins(1)) + IOBUF(th.led0_g, io_gpio.pins(2)) + IOBUF(th.led0_b, io_gpio.pins(3)) + + // Note that this is the one which is actually connected on the HiFive/Crazy88 + // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active + IOBUF(th.led1_r, io_gpio.pins(19)) + IOBUF(th.led1_g, io_gpio.pins(21)) + IOBUF(th.led1_b, io_gpio.pins(22)) + + // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active + IOBUF(th.led2_r, io_gpio.pins(11)) + IOBUF(th.led2_g, io_gpio.pins(12)) + IOBUF(th.led2_b, io_gpio.pins(13)) + + // Only 19 out of 20 shield pins connected to GPIO pins + // Shield pin A5 (pin 14) left unconnected + // The buttons are connected to some extra GPIO pins not connected on the + // HiFive1 board + IOBUF(th.btn_0, io_gpio.pins(15)) + IOBUF(th.btn_1, io_gpio.pins(30)) + IOBUF(th.btn_2, io_gpio.pins(31)) + + val iobuf_btn_3 = Module(new IOBUF()) + iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval + iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe + attach(th.btn_3, iobuf_btn_3.io.IO) + io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie + + // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 + IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX + IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX + + // SPI2 pins mapped to 6 pin ICSP connector (standard on later + // arduinos) These are connected to some extra GPIO pins not connected + // on the HiFive1 board + IOBUF(th.ck_ss, io_gpio.pins(26)) + IOBUF(th.ck_mosi, io_gpio.pins(27)) + IOBUF(th.ck_miso, io_gpio.pins(28)) + IOBUF(th.ck_sck, io_gpio.pins(29)) + + // Use the LEDs for some more useful debugging things + IOBUF(th.led_0, th.ck_rst) + IOBUF(th.led_1, th.SRST_n) + IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) + IOBUF(th.led_3, io_gpio.pins(14)) + + //--------------------------------------------------------------------- + // Unconnected inputs + //--------------------------------------------------------------------- + + io_aon.erst_n.i.ival := ~th.reset_periph + io_aon.lfextclk.i.ival := slow_clock + io_aon.pmu.vddpaden.i.ival := 1.U + } + + Nil + } + } + + Seq((Nil, Nil, Some(harnessFn))) + } +}) + diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala deleted file mode 100644 index 514ff74c..00000000 --- a/fpga/src/main/scala/arty/Platform.scala +++ /dev/null @@ -1,180 +0,0 @@ -// See LICENSE for license details. -package chipyard.fpga - -import Chisel._ - -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util.ResetCatchAndSync -import freechips.rocketchip.system._ - -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.pinctrl._ - -import chipyard.{DigitalTop} - -//------------------------------------------------------------------------- -// PinGen -//------------------------------------------------------------------------- - -object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } -} - -//------------------------------------------------------------------------- -// E300ArtyDevKitPlatformIO -//------------------------------------------------------------------------- - -class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { - val pins = new Bundle { - val jtag = new JTAGPins(() => PinGen(), false) - val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0)) - val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0)) - val aon = new MockAONWrapperPins() - } - val jtag_reset = Bool(INPUT) - val ndreset = Bool(OUTPUT) -} - -//------------------------------------------------------------------------- -// E300ArtyDevKitPlatform -//------------------------------------------------------------------------- - -class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { - val sys = Module(LazyModule(new DigitalTop).module) - val io = new E300ArtyDevKitPlatformIO - - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = sys.aon.rsts.corerst - // Add in debug-controlled reset. - sys.reset := ResetCatchAndSync(clock, async_corerst, 20) - Debug.connectDebugClockAndReset(sys.debug, clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = sys.uart - val sys_pwm = sys.pwm - val sys_spi = sys.spi - val sys_i2c = sys.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- sys.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- sys.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = sys.gpio(0).iof_0.get - val iof_1 = sys.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io.pins.gpio, sys.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3) - - // JTAG Debug Interface - val sjtag = sys.debug.get.systemjtag.get - JTAGPinsFromPort(io.pins.jtag, sjtag.jtag) - sjtag.reset := io.jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io.ndreset := sys.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - io.pins.aon <> sys.aon.pins -} diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala new file mode 100644 index 00000000..919e5c99 --- /dev/null +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -0,0 +1,34 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{Analog} + +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.config.{Parameters} + +import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} + +import chipyard.{BuildTop, HasHarnessSignalReferences} + +class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { + + val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") + + // turn IO clock into Reset type + val hReset = Wire(Reset()) + hReset := ck_rst + + // default to 32MHz clock + withClockAndReset(clock_32MHz, hReset) { + val dut = Module(ldut.module) + } + + val harnessClock = clock_32MHz + val harnessReset = hReset + val success = false.B + val dutReset = hReset + + // must be after HasHarnessSignalReferences assignments + ldut.harnessFunctions.foreach(_(this)) +} + From b4e270219d06f5be568bbc62df362a9c29f98822 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 7 Sep 2020 14:02:31 -0700 Subject: [PATCH 170/457] Bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7cb10dcb..522125da 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7cb10dcb5eac4f2dc35ca8ee2bb0e1629fedd19b +Subproject commit 522125da5d546544e3ce4492b6f105eeb93fcdf6 From c49eef32241ff2a112628d5999ffec89c2f8179d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 7 Sep 2020 15:26:30 -0700 Subject: [PATCH 171/457] Small cleanup to CY DigitalTop | Move E300 configs to unique folder --- fpga/Makefile | 2 +- .../arty/{Config.scala => e300/Configs.scala} | 9 +++++++- .../src/main/scala/arty/e300/DigitalTop.scala | 23 +++++++++++++++++++ .../scala/arty/{ => e300}/IOBinders.scala | 2 +- .../chipyard/src/main/scala/DigitalTop.scala | 14 +++++------ 5 files changed, 39 insertions(+), 11 deletions(-) rename fpga/src/main/scala/arty/{Config.scala => e300/Configs.scala} (92%) create mode 100644 fpga/src/main/scala/arty/e300/DigitalTop.scala rename fpga/src/main/scala/arty/{ => e300}/IOBinders.scala (99%) diff --git a/fpga/Makefile b/fpga/Makefile index 0110bb10..c1e4fb2d 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -23,7 +23,7 @@ MODEL := ArtyFPGATestHarness VLOG_MODEL := ArtyFPGATestHarness MODEL_PACKAGE := chipyard.fpga.arty CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := chipyard.fpga.arty +CONFIG_PACKAGE := chipyard.fpga.arty.e300 GENERATOR_PACKAGE := chipyard TB := none # unused TOP := ChipTop diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/e300/Configs.scala similarity index 92% rename from fpga/src/main/scala/arty/Config.scala rename to fpga/src/main/scala/arty/e300/Configs.scala index bcea7c78..dd9213fc 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga.arty +package chipyard.fpga.arty.e300 import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,6 +16,8 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ +import chipyard.{BuildSystem} + class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) @@ -46,7 +48,12 @@ class E300DevKitExtra extends Config((site, here, up) => { debugIdleCycles = 5) }) +class WithE300System extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) +}) + class E300ArtyDevKitConfig extends Config( + new WithE300System ++ new WithE300Connections ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala new file mode 100644 index 00000000..1bda2680 --- /dev/null +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -0,0 +1,23 @@ +package chipyard.fpga.arty.e300 + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ + +import chipyard.{DigitalTop, DigitalTopModule} + +// ------------------------------------ +// E300 DigitalTop +// ------------------------------------ + +class E300DigitalTop(implicit p: Parameters) extends DigitalTop + with sifive.blocks.devices.mockaon.HasPeripheryMockAON +{ + override lazy val module = new E300DigitalTopModule(this) +} + +class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) + with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala similarity index 99% rename from fpga/src/main/scala/arty/IOBinders.scala rename to fpga/src/main/scala/arty/e300/IOBinders.scala index e8833827..d9a2e1cc 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty +package chipyard.fpga.arty.e300 import chisel3._ import chisel3.experimental.{attach, IO} diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 160e6acf..9e40cfab 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,10 +13,6 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem - with sifive.blocks.devices.mockaon.HasPeripheryMockAON - with sifive.blocks.devices.spi.HasPeripherySPI - with sifive.blocks.devices.pwm.HasPeripheryPWM - with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -24,6 +20,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI + with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM + with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -35,16 +34,15 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp - with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch From 2580073d75cd98838f4ccf9ae3757e158a2d25f2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 7 Sep 2020 15:30:21 -0700 Subject: [PATCH 172/457] Comment cleanup --- fpga/src/main/scala/arty/e300/IOBinders.scala | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index d9a2e1cc..8d866619 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -33,10 +33,15 @@ class WithE300Connections extends OverrideIOBinder({ with HasPeripherySPIFlashModuleImp with HasPeripheryMockAONModuleImp with HasPeripheryI2CModuleImp) => { - // match the E300 connections using a "Chipyard"-like structure implicit val p: Parameters = GetSystemParameters(system) + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + // E300DigitalTop <-> ChipTop connections + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + object PinGen { def apply(): BasePin = { val pin = new BasePin() @@ -51,8 +56,6 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - // TODO: Fix - // add iocells (or none) // This needs to be de-asserted synchronously to the coreClk. val async_corerst = system.aon.rsts.corerst // Add in debug-controlled reset. @@ -175,6 +178,11 @@ class WithE300Connections extends OverrideIOBinder({ // and thus there is no .fromPort method. io_aon <> system.aon.pins + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + // Harness Function (ArtyHarness <-> ChipTop) + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- val harnessFn = (baseTh: HasHarnessSignalReferences) => { baseTh match { case th: ArtyShell => From 11a9ad24286e0588e7e7a613d81ac3d8552fbe14 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 8 Sep 2020 15:52:09 -0700 Subject: [PATCH 173/457] Address code review comments --- build.sbt | 2 +- docs/Customization/IOBinders.rst | 6 +-- .../chipyard/src/main/scala/ChipTop.scala | 3 +- .../chipyard/src/main/scala/Clocks.scala | 1 - .../src/main/scala/HarnessBinders.scala | 36 ++++++++----- .../chipyard/src/main/scala/IOBinders.scala | 20 +++++-- .../src/main/scala/config/ArianeConfigs.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 54 +++++++++---------- .../main/scala/config/TracegenConfigs.scala | 44 ++++----------- 9 files changed, 81 insertions(+), 87 deletions(-) diff --git a/build.sbt b/build.sbt index 3ca021a7..5d642c1d 100644 --- a/build.sbt +++ b/build.sbt @@ -211,7 +211,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) - .dependsOn(chipyard, midasTargetUtils, midas, iocell, firesimLib % "test->test;compile->compile") + .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ), diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index adfac22b..ff180bcd 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -8,7 +8,7 @@ IOBinders The ``IOBinder`` functions are responsible for instantiating IO cells and IOPorts in the ``ChipTop`` layer. -``IOBinders`` are typically defined using the ``OverrideIOBinder`` or ``ComposeIOBinder`` macros. An ``IOBInder`` consists of a function matching ``Systems`` with a given trait that generates IO ports and IOCells, and returns a list of generated ports and cells. +``IOBinders`` are typically defined using the ``OverrideIOBinder`` or ``ComposeIOBinder`` macros. An ``IOBinder`` consists of a function matching ``Systems`` with a given trait that generates IO ports and IOCells, and returns a list of generated ports and cells. For example, the ``WithUARTIOCells`` IOBinder will, for any ``System`` that might have UART ports (``HasPeripheryUARTModuleImp``, generate ports within the ``ChipTop`` (``ports``) as well as IOCells with the appropriate type and direction (``cells2d``). This function returns a the list of generated ports, and the list of generated IOCells. The list of generated ports is passed to the ``HarnessBinders`` such that they can be connected to ``TestHarness`` devices. @@ -23,12 +23,10 @@ HarnessBinders The ``HarnessBinder`` functions determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. The ``HarnessBinder`` interface is designed to be reused across various simulation/implementation modes, enabling decoupling of the target design from simulation and testing concerns. - * For SW RTL simulations, the default set of ``HarnessBinders`` instantiate software-simulated models of various devices, for example external memory or UART, and connect those models to the IOs of the ``ChipTop``. + * For SW RTL or GL simulations, the default set of ``HarnessBinders`` instantiate software-simulated models of various devices, for example external memory or UART, and connect those models to the IOs of the ``ChipTop``. * For FireSim simulations, FireSim-specific ``HarnessBinders`` instantiate ``Bridges``, which faciliate cycle-accurate simulation across the simulated chip's IOs. See the FireSim documentation for more details. * In the future, a Chipyard FPGA prototyping flow may use ``HarnessBinders`` to connect ``ChipTop`` IOs to other devices or IOs in the FPGA harness. -For FireSim simulations, the ``HarnessBinder`` attaches ``Bridge`` modules (See the FireSim documentation for more details). - Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarnessBinder, ComposeHarnessBinder``), and match ``Systems`` with a given trait. However, ``HarnessBinders`` are also passed a reference to the ``TestHarness`` (``th: HasHarnessSignalReferences``) and the list of ports generated by the corresponding ``IOBinder`` (``ports: Seq[Data]``). For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to the ports generated by the ``WithUARTIOCells`` described earlier, if those ports are present. diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 6ae63d57..dfe08780 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -46,8 +46,7 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc val implicit_reset = implicitClockSinkNode.in.head._1.reset - // The implicit clock and reset for the system is also, by convention, used for all the IOBinders - // TODO: This may not be the right thing to do in all cases + // Note: IOBinders cannot rely on the implicit clock/reset, as this is a LazyRawModuleImp val (_ports, _iocells, _portMap) = ApplyIOBinders(lazySystem, p(IOBinders)) // We ignore _ports for now... iocells ++= _iocells diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index d6b19e8d..a1ff1b0f 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -120,7 +120,6 @@ object ClockingSchemeGenerators { } }} - chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { clock_io := th.harnessClock Nil diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index a26b5104..694d45da 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -69,7 +69,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({ // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - UARTAdapter.connect(ports.map(_.asInstanceOf[UARTPortIO]))(system.p) + UARTAdapter.connect(ports.map({case p: UARTPortIO => p}))(system.p) Nil } }) @@ -77,7 +77,7 @@ class WithUARTAdapter extends OverrideHarnessBinder({ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - SimSPIFlashModel.connect(ports.map(_.asInstanceOf[SPIChipIO]), th.harnessReset, rdOnly)(system.p) + SimSPIFlashModel.connect(ports.map({case p: SPIChipIO => p}), th.harnessReset, rdOnly)(system.p) Nil } }) @@ -132,8 +132,11 @@ class WithSimAXIMem extends OverrideHarnessBinder({ (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) val clock = WireInit(false.B.asClock) - ports.filter(_.isInstanceOf[Clock]).map { case p: Clock => clock := p } - val axi4_ports = ports.filter(_.isInstanceOf[AXI4Bundle]) + ports.map { + case p: Clock => clock := p + case _ => + } + val axi4_ports = ports.collect { case p: AXI4Bundle => p } (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) withClockAndReset(clock, th.harnessReset) { @@ -149,7 +152,10 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) val clock = WireInit(false.B.asClock) - ports.filter(_.isInstanceOf[Clock]).map { case p: Clock => clock := p } + ports.map { + case p: Clock => clock := p + case _ => + } val axi4_ports = ports.collect { case p: AXI4Bundle => p } (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => val memSize = p(ExtMem).get.master.size @@ -167,11 +173,15 @@ class WithSimAXIMMIO extends OverrideHarnessBinder({ (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) val clock = WireInit(false.B.asClock) - ports.filter(_.isInstanceOf[Clock]).map { case p: Clock => clock := p } - (ports zip system.mmioAXI4Node.edges.in).zipWithIndex.map { case ((port: AXI4Bundle, edge), i) => - val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)(p)) + ports.map { + case p: Clock => clock := p + case _ => + } + val axi4_ports = ports.collect { case p: AXI4Bundle => p } + (axi4_ports zip system.mmioAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => + val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) withClockAndReset(clock, th.harnessReset) { - Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") + Module(mmio_mem.module).suggestName("mmio_mem") } mmio_mem.io_axi4.head <> port } @@ -188,9 +198,11 @@ class WithTieOffInterrupts extends OverrideHarnessBinder({ class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { case p: AXI4Bundle => - p := DontCare - p.tieoff() + ports.map { + case p: AXI4Bundle => + p := DontCare + p.tieoff() + case c: Clock => } Nil } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index db5c7008..dfcbd8ba 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -47,8 +47,13 @@ case object IOBinders extends Field[Map[String, (Any) => (Seq[Data], Seq[IOCell] object ApplyIOBinders { def apply(sys: LazyModule, map: Map[String, (Any) => (Seq[Data], Seq[IOCell])]): (Iterable[Data], Iterable[IOCell], Map[String, Seq[Data]]) = { - val r = map.map({ case (s,f) => (f(sys), s) }) ++ map.map({ case (s,f) => (f(sys.module), s) }) - (r.flatMap(_._1._1), r.flatMap(_._1._2), r.map { t => t._2 -> t._1._1 }) + val lzy = map.map({ case (s,f) => s -> f(sys) }) + val imp = map.map({ case (s,f) => s -> f(sys.module) }) + + val ports: Iterable[Data] = lzy.values.map(_._1).flatten ++ imp.values.map(_._1).flatten + val cells: Iterable[IOCell] = lzy.values.map(_._2).flatten ++ imp.values.map(_._2).flatten + val portMap: Map[String, Seq[Data]] = map.keys.map(k => k -> (lzy(k)._1 ++ imp(k)._1)).toMap + (ports, cells, portMap) } } @@ -287,13 +292,18 @@ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ }) class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4Port) => { - val port = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => + (system: CanHaveSlaveAXI4Port) => { + val clock = if (!system.l2_frontend_bus_axi4.isEmpty) { + Some(BoreHelper("axi4_fbus_clock", system.asInstanceOf[BaseSubsystem].fbus.module.clock)) + } else { + None + } + val ports = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => val p = IO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_fbus_${i}") m <> p p }) - (port, Nil) + (ports ++ clock, Nil) } }) diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 47e7c15b..9f701331 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -13,7 +13,7 @@ class ArianeConfig extends Config( new chipyard.config.AbstractConfig) class dmiArianeConfig extends Config( - new chipyard.harness.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index a8686961..16d298fb 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -12,21 +12,21 @@ class RocketConfig extends Config( class HwachaRocketConfig extends Config( new chipyard.config.WithHwachaTest ++ - new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: GemminiRocketConfig class GemminiRocketConfig extends Config( - new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator + new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: GemminiRocketConfig // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.harness.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead - new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new chipyard.harness.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: DmiRocket @@ -40,53 +40,53 @@ class GCDTLRocketConfig extends Config( // DOC include start: GCDAXI4BlackBoxRocketConfig class GCDAXI4BlackBoxRocketConfig extends Config( - new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink + new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig class LargeSPIFlashROMRocketConfig extends Config( - new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) + new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) new chipyard.config.WithSPIFlash ++ // add the SPI flash controller new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class SmallSPIFlashRocketConfig extends Config( - new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) + new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class SimAXIRocketConfig extends Config( - new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM + new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class SimBlockDeviceRocketConfig extends Config( - new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice - new testchipip.WithBlockDevice ++ // add block-device module to peripherybus + new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice + new testchipip.WithBlockDevice ++ // add block-device module to peripherybus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class BlockDeviceModelRocketConfig extends Config( - new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel - new testchipip.WithBlockDevice ++ // add block-device module to periphery bus + new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel + new testchipip.WithBlockDevice ++ // add block-device module to periphery bus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: GPIORocketConfig class GPIORocketConfig extends Config( - new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus + new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: GPIORocketConfig class QuadRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) new chipyard.config.AbstractConfig) class RV32RocketConfig extends Config( - new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit + new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -104,14 +104,14 @@ class Sha3RocketConfig extends Config( // DOC include start: InitZeroRocketConfig class InitZeroRocketConfig extends Config( - new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero + new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: InitZeroRocketConfig class LoopbackNICRocketConfig extends Config( - new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback - new icenet.WithIceNIC ++ // add an IceNIC + new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback + new icenet.WithIceNIC ++ // add an IceNIC new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -126,8 +126,8 @@ class ScratchpadOnlyRocketConfig extends Config( // DOC include end: l1scratchpadrocket class L1ScratchpadRocketConfig extends Config( - new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad - new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad + new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad + new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -141,35 +141,35 @@ class MbusScratchpadRocketConfig extends Config( // DOC include start: RingSystemBusRocket class RingSystemBusRocketConfig extends Config( - new testchipip.WithRingSystemBus ++ // Ring-topology system bus + new testchipip.WithRingSystemBus ++ // Ring-topology system bus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: RingSystemBusRocket class StreamingPassthroughRocketConfig extends Config( - new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough + new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include start: StreamingFIRRocketConfig class StreamingFIRRocketConfig extends Config ( - new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR + new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: StreamingFIRRocketConfig class SmallNVDLARocketConfig extends Config( - new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA + new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class LargeNVDLARocketConfig extends Config( - new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams + new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class MMIORocketConfig extends Config( - new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port + new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -177,7 +177,7 @@ class MMIORocketConfig extends Config( // NOTE: This config doesn't work yet because SimWidgets in the TestHarness // always get the TestHarness clock. The Tiles and Uncore receive the correct clocks class DividedClockRocketConfig extends Config( - new chipyard.config.WithTileDividedClock ++ // Put the Tile on its own clock domain + new chipyard.config.WithTileDividedClock ++ // Put the Tile on its own clock domain new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 28bc5dcd..78cb6851 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -3,61 +3,37 @@ package chipyard import freechips.rocketchip.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} -class TraceGenConfig extends Config( +class AbstractTraceGenConfig extends Config( new chipyard.harness.WithBlackBoxSimMem ++ new chipyard.harness.WithTraceGenSuccess ++ new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ - new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.groundtest.GroundTestBaseConfig) + +class TraceGenConfig extends Config( + new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new AbstractTraceGenConfig) + class NonBlockingTraceGenConfig extends Config( - new chipyard.harness.WithBlackBoxSimMem ++ - new chipyard.harness.WithTraceGenSuccess ++ - new chipyard.iobinders.WithAXI4MemPunchthrough ++ - new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ - new chipyard.config.WithTracegenSystem ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.groundtest.GroundTestBaseConfig) + new AbstractTraceGenConfig) class BoomTraceGenConfig extends Config( - new chipyard.harness.WithBlackBoxSimMem ++ - new chipyard.harness.WithTraceGenSuccess ++ - new chipyard.iobinders.WithAXI4MemPunchthrough ++ - new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ - new chipyard.config.WithTracegenSystem ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.groundtest.GroundTestBaseConfig) + new AbstractTraceGenConfig) class NonBlockingTraceGenL2Config extends Config( - new chipyard.harness.WithBlackBoxSimMem ++ - new chipyard.harness.WithTraceGenSuccess ++ - new chipyard.iobinders.WithAXI4MemPunchthrough ++ - new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ - new chipyard.config.WithTracegenSystem ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.groundtest.GroundTestBaseConfig) + new AbstractTraceGenConfig) class NonBlockingTraceGenL2RingConfig extends Config( - new chipyard.harness.WithBlackBoxSimMem ++ - new chipyard.harness.WithTraceGenSuccess ++ - new chipyard.iobinders.WithAXI4MemPunchthrough ++ - new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ - new chipyard.config.WithTracegenSystem ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.groundtest.GroundTestBaseConfig) + new AbstractTraceGenConfig) From 56eead4053df7f7a2c284e9aa7602ca544e18011 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 8 Sep 2020 17:04:56 -0700 Subject: [PATCH 174/457] NOT WORKING: VCU118 Commit --- build.sbt | 2 +- fpga/Makefile | 10 +-- fpga/src/main/scala/vcu118/Configs.scala | 51 ++++++++++++++ fpga/src/main/scala/vcu118/IOBinders.scala | 69 +++++++++++++++++++ fpga/src/main/scala/vcu118/Shell.scala | 0 fpga/src/main/scala/vcu118/TestHarness.scala | 36 ++++++++++ .../chipyard/src/main/scala/ChipTop.scala | 1 + 7 files changed, 163 insertions(+), 6 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/Configs.scala create mode 100644 fpga/src/main/scala/vcu118/IOBinders.scala create mode 100644 fpga/src/main/scala/vcu118/Shell.scala create mode 100644 fpga/src/main/scala/vcu118/TestHarness.scala diff --git a/build.sbt b/build.sbt index ffe8bfe8..3420955b 100644 --- a/build.sbt +++ b/build.sbt @@ -218,7 +218,7 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testOptions in Test += Tests.Argument("-oF") ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) - .dependsOn(rocketchip, sifive_blocks) + .dependsOn(rocketchip, sifive_blocks, chipyard) .settings(commonSettings) lazy val fpga_platforms = (project in file("./fpga")) diff --git a/fpga/Makefile b/fpga/Makefile index c1e4fb2d..643e0c67 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -19,11 +19,11 @@ include $(base_dir)/variables.mk # default variables to build the arty example SUB_PROJECT := fpga SBT_PROJECT := fpga_platforms -MODEL := ArtyFPGATestHarness -VLOG_MODEL := ArtyFPGATestHarness -MODEL_PACKAGE := chipyard.fpga.arty -CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := chipyard.fpga.arty.e300 +MODEL := VCU118FPGATestHarness +VLOG_MODEL := VCU118FPGATestHarness +MODEL_PACKAGE := chipyard.fpga.vcu118 +CONFIG := FakeBringupConfig +CONFIG_PACKAGE := chipyard.fpga.vcu118 GENERATOR_PACKAGE := chipyard TB := none # unused TOP := ChipTop diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala new file mode 100644 index 00000000..a98aa3cf --- /dev/null +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -0,0 +1,51 @@ +// See LICENSE for license details. +package chipyard.fpga.vcu118 + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +import freechips.rocketchip.system._ +import freechips.rocketchip.tile._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ + +import sifive.fpgashells.shell.{DesignKey} + +import chipyard.{BuildTop} + +class WithChipyardBuildTop extends Config((site, here, up) => { + //case DesignKey => { (p:Parameters) => p(BuildTop)(p) } + case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) } +}) + +class WithBringupUARTs extends Config((site, here, up) => { + case PeripheryUARTKey => List( + UARTParams(address = BigInt(0x64000000L)), + UARTParams(address = BigInt(0x64003000L))) +}) + +class FakeBringupConfig extends Config( + new WithUARTConnection1 ++ + new WithBringupUARTs ++ + new WithChipyardBuildTop ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.With1TinyCore ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala new file mode 100644 index 00000000..dfec55cc --- /dev/null +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -0,0 +1,69 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{attach, IO} + +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.subsystem.{NExtTopInterrupts} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pinctrl._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + +import chipsalliance.rocketchip.config._ +import sifive.fpgashells.shell._ + +import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} +import chipyard.{HasHarnessSignalReferences} +import freechips.rocketchip.diplomacy._ + +class WithUARTConnection1 extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + + implicit val p: Parameters = GetSystemParameters(system) + + val io_uart_pins = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } + (io_uart_pins zip system.uart) map { case (p, r) => p <> r } + + val harnessFn = (th: HasHarnessSignalReferences) => { + println(th) + println("Got here - -- - - - ") + Nil + } + //val harnessFn = (baseTh: HasHarnessSignalReferences) => { + // println("DEBUG: ---------------------- 0") + // baseTh match { case th: VCU118Shell => + // println("DEBUG: ---------------------- 1") + + // val io_uart_pins_bb = p(PeripheryUARTKey) map { c => BundleBridgeSource(() => (new UARTPortIO(c))) } + + // InModuleBody { + // (io_uart_pins_bb zip io_uart_pins) map { case (p, r) => p.bundle <> r } + // } + + // require(p(PeripheryUARTKey).size >= 1) + + // println("DEBUG: ---------------------- 2") + + // th.designParameters(UARTOverlayKey).foreach { uok => + // println("DEBUG: ---------------------- 3") + // uok.place(UARTDesignInput(io_uart_pins_bb(0))).overlayOutput + // } + + // Nil + // } + //} + + Seq((Nil, Nil, Some(harnessFn))) + } +}) + diff --git a/fpga/src/main/scala/vcu118/Shell.scala b/fpga/src/main/scala/vcu118/Shell.scala new file mode 100644 index 00000000..e69de29b diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala new file mode 100644 index 00000000..6da984bf --- /dev/null +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -0,0 +1,36 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{Analog, IO} + +import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp} +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.diplomacy.{InModuleBody} + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} + +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell with HasHarnessSignalReferences { + val pllResetAsReset = InModuleBody{ Wire(Reset()) } + + InModuleBody { + pllResetAsReset := pllReset + } + + lazy val harnessClock = this.module.sysclk + lazy val harnessReset = pllResetAsReset.getWrappedValue + val success = false.B + lazy val dutReset = pllResetAsReset.getWrappedValue + + // must be after HasHarnessSignalReferences assignments + println(s"DEBUG: ----- sz:${topDesign.harnessFunctions.size}") + topDesign match { case d: HasTestHarnessFunctions => + println(s"DEBUG: ----- sz:${d.harnessFunctions.size}") + d.harnessFunctions.foreach(_(this)) + } +} + diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index cf71987b..2df79ec2 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -55,6 +55,7 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten + println(s"ChipTop: sz:${harnessFunctions.size}") } // Connect the implicit clock/reset, if present From 8f9574fd7980f38320bfac8095ce9d3d31d94a70 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 8 Sep 2020 21:52:50 -0700 Subject: [PATCH 175/457] Clean up passing ports from IOBinders to HarnessBinders --- .../src/main/scala/HarnessBinders.scala | 175 +++++++----------- .../chipyard/src/main/scala/IOBinders.scala | 103 +++++------ 2 files changed, 114 insertions(+), 164 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 694d45da..f427d44e 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -1,6 +1,7 @@ package chipyard.harness import chisel3._ +import chisel3.experimental.{Analog} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -19,6 +20,7 @@ import barstools.iocell.chisel._ import testchipip._ import chipyard.HasHarnessSignalReferences +import chipyard.iobinders.ClockedIO import tracegen.{TraceGenSystemModuleImp} import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} @@ -33,26 +35,29 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer object ApplyHarnessBinders { def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { val pm = portMap.withDefaultValue(Nil) - map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) + } } } -class OverrideHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val pts = ports.map(_.asInstanceOf[S]) t match { - case system: T => fn(system, th, ports) + case system: T => fn(system, th, pts) case _ => Nil } }) ) }) -class ComposeHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val pts = ports.map(_.asInstanceOf[S]) t match { - case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, ports) ++ fn(system, th, ports) + case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts) case _ => Nil } }) @@ -60,109 +65,83 @@ class ComposeHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data]) }) class WithGPIOTiedOff extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { case p: GPIOPortIO => p <> AnalogConst(0) } + (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => { + ports.foreach { _ <> AnalogConst(0) } Nil } }) // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - UARTAdapter.connect(ports.map({case p: UARTPortIO => p}))(system.p) + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + UARTAdapter.connect(ports)(system.p) Nil } }) // DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ - (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - SimSPIFlashModel.connect(ports.map({case p: SPIChipIO => p}), th.harnessReset, rdOnly)(system.p) + (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { + SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p) Nil } }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val clock = WireInit(false.B.asClock) - ports.map { - case p: BlockDeviceIO => SimBlockDevice.connect(clock, th.harnessReset.asBool, Some(p))(system.p) - case c: Clock => clock := c - } + (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + ports.map { p => SimBlockDevice.connect(p.clock, th.harnessReset.asBool, Some(p.bits))(system.p) } Nil } }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val clock = WireInit(false.B.asClock) - ports.map { - case p: BlockDeviceIO => withClockAndReset(clock, th.harnessReset) { BlockDeviceModel.connect(Some(p))(system.p) } - case c: Clock => clock := c - } + (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + ports.map { p => withClockAndReset(p.clock, th.harnessReset) { BlockDeviceModel.connect(Some(p.bits))(system.p) } } Nil } }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val clock = WireInit(false.B.asClock) - ports.map { - case p: NICIOvonly => withClockAndReset(clock, th.harnessReset) { - NicLoopback.connect(Some(p), system.p(NICKey)) + (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + ports.map { p => + withClockAndReset(p.clock, th.harnessReset) { + NicLoopback.connect(Some(p.bits), system.p(NICKey)) } - case c: Clock => clock := c } Nil } }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val clock = WireInit(false.B.asClock) - ports.map { - case p: NICIOvonly => SimNetwork.connect(Some(p), clock, th.harnessReset.asBool) - case c: Clock => clock := c - } + (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + ports.map { p => SimNetwork.connect(Some(p.bits), p.clock, th.harnessReset.asBool) } Nil } }) class WithSimAXIMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) - val clock = WireInit(false.B.asClock) - ports.map { - case p: Clock => clock := p - case _ => - } - val axi4_ports = ports.collect { case p: AXI4Bundle => p } - (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => + (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) - withClockAndReset(clock, th.harnessReset) { + withClockAndReset(port.clock, th.harnessReset) { Module(mem.module).suggestName("mem") } - mem.io_axi4.head <> port + mem.io_axi4.head <> port.bits } Nil } }) class WithBlackBoxSimMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) - val clock = WireInit(false.B.asClock) - ports.map { - case p: Clock => clock := p - case _ => - } - val axi4_ports = ports.collect { case p: AXI4Bundle => p } - (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => + (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)).suggestName("simdram") - mem.io.axi <> port - mem.io.clock := clock + mem.io.axi <> port.bits + mem.io.clock := port.clock mem.io.reset := th.harnessReset } Nil @@ -170,57 +149,44 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ }) class WithSimAXIMMIO extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) - val clock = WireInit(false.B.asClock) - ports.map { - case p: Clock => clock := p - case _ => - } - val axi4_ports = ports.collect { case p: AXI4Bundle => p } - (axi4_ports zip system.mmioAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) => + (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) - withClockAndReset(clock, th.harnessReset) { + withClockAndReset(port.clock, th.harnessReset) { Module(mmio_mem.module).suggestName("mmio_mem") } - mmio_mem.io_axi4.head <> port + mmio_mem.io_axi4.head <> port.bits } Nil } }) class WithTieOffInterrupts extends OverrideHarnessBinder({ - (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { case p: UInt => p := 0.U } + (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => { + ports.foreach { _ := 0.U } Nil } }) class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ - (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { - case p: AXI4Bundle => - p := DontCare - p.tieoff() - case c: Clock => - } + (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + ports.foreach({ p => p := DontCare; p.bits.tieoff() }) Nil } }) class WithSimDebug extends OverrideHarnessBinder({ (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - if (!ports.isEmpty) { - val dtm_success = Wire(Bool()) - when (dtm_success) { th.success := true.B } - ports.map { - case d: ClockedDMIIO => - val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success) - case j: JTAGIO => - val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) - case _ => - require(false, "We only support DMI or JTAG simulated debug connections") - } + ports.map { + case d: ClockedDMIIO => + val dtm_success = WireInit(false.B) + when (dtm_success) { th.success := true.B } + val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success) + case j: JTAGIO => + val dtm_success = WireInit(false.B) + when (dtm_success) { th.success := true.B } + val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) } Nil } @@ -229,63 +195,56 @@ class WithSimDebug extends OverrideHarnessBinder({ class WithTiedOffDebug extends OverrideHarnessBinder({ (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { + case j: JTAGIO => + j.TCK := true.B.asClock + j.TMS := true.B + j.TDI := true.B + j.TRSTn.foreach { r => r := true.B } case d: ClockedDMIIO => d.dmi.req.valid := false.B d.dmi.req.bits := DontCare d.dmi.resp.ready := true.B d.dmiClock := false.B.asClock d.dmiReset := true.B - case j: JTAGIO => - j.TCK := true.B.asClock - j.TMS := true.B - j.TDI := true.B - j.TRSTn.foreach { r => r := true.B } case a: ClockedAPBBundle => a.tieoff() a.clock := false.B.asClock a.reset := true.B.asAsyncReset a.psel := false.B a.penable := false.B - case _ => require(false) } Nil } }) + class WithTiedOffSerial extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { - case p: SerialIO => SerialAdapter.tieoff(Some(p)) - case _ => - } + (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + ports.map { p => SerialAdapter.tieoff(Some(p.bits)) } Nil } }) class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val serial_clock = WireInit(false.B.asClock) - ports.map { - case p: SerialIO => - val ser_success = SerialAdapter.connectSimSerial(p, serial_clock, th.harnessReset) - when (ser_success) { th.success := true.B } - case c: Clock => - serial_clock := c + (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + ports.map { p => + val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset) + when (ser_success) { th.success := true.B } } Nil } }) class WithTraceGenSuccess extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { case p: Bool => when (p) { th.success := true.B } } + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { + ports.map { p => when (p) { th.success := true.B } } Nil } }) class WithSimDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } }) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index dfcbd8ba..969ad571 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -74,7 +74,7 @@ object GetSystemParameters { // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { @@ -87,7 +87,7 @@ class OverrideIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag: // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { @@ -116,6 +116,11 @@ object BoreHelper { case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) +class ClockedIO[T <: Data](gen: T) extends Bundle { + val clock = Output(Clock()) + val bits = gen + override def cloneType: this.type = (new ClockedIO(DataMirror.internal.chiselTypeClone[T](gen))).asInstanceOf[this.type] +} class WithGPIOCells extends OverrideIOBinder({ (system: HasPeripheryGPIOModuleImp) => { @@ -131,14 +136,15 @@ class WithGPIOCells extends OverrideIOBinder({ (g, iocell) }).unzip }).unzip - (ports2d.flatten, cells2d.flatten) + val ports: Seq[Analog] = ports2d.flatten + (ports, cells2d.flatten) } }) // DOC include start: WithUARTIOCells class WithUARTIOCells extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { - val (ports, cells2d) = system.uart.zipWithIndex.map({ case (u, i) => + val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) => val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}"), system.p(IOCellKey)) port.suggestName(s"uart_${i}") (port, ios) @@ -150,7 +156,7 @@ class WithUARTIOCells extends OverrideIOBinder({ class WithSPIIOCells extends OverrideIOBinder({ (system: HasPeripherySPIFlashModuleImp) => { - val (ports, cells2d) = system.qspi.zipWithIndex.map({ case (s, i) => + val (ports: Seq[SPIChipIO], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) => val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"spi_${i}") val iocellBase = s"iocell_spi_${i}" @@ -178,7 +184,7 @@ class WithSPIIOCells extends OverrideIOBinder({ class WithExtInterruptIOCells extends OverrideIOBinder({ (system: HasExtInterruptsModuleImp) => { if (system.outer.nExtInterrupts > 0) { - val (port, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey)) + val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey)) port.suggestName("ext_interrupts") (Seq(port), cells) } else { @@ -246,94 +252,79 @@ class WithDebugIOCells extends OverrideIOBinder({ class WithSerialIOCells extends OverrideIOBinder({ (system: CanHavePeripherySerial) => system.serial.map({ s => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s, Some("iocell_serial"), sys.p(IOCellKey)) - val serial_clock = Wire(Output(Clock())).suggestName("chiptop_serial_clock") - serial_clock := false.B.asClock // necessary for BoringUtils to work properly - dontTouch(serial_clock) - BoringUtils.bore(sys.fbus.module.clock, Seq(serial_clock)) - val (serial_clock_io, serial_clock_cell) = IOCell.generateIOFromSignal(serial_clock, Some("serial_clock"), sys.p(IOCellKey)) - serial_clock_io.suggestName("serial_clock") + val clocked_serial = Wire(new ClockedIO(DataMirror.internal.chiselTypeClone[SerialIO](s))).suggestName("serial_wire") + clocked_serial.clock := BoreHelper("serial_clock", sys.fbus.module.clock) + clocked_serial.bits <> s + val (port, cells) = IOCell.generateIOFromSignal(clocked_serial, Some("serial"), sys.p(IOCellKey)) port.suggestName("serial") - (Seq(port, serial_clock_io), cells ++ serial_clock_cell) + (Seq(port), cells) }).getOrElse((Nil, Nil)) }) class WithAXI4MemPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort) => { - val clock = if (!system.mem_axi4.isEmpty) { - Some(BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock)) - } else { - None - } - val ports = system.mem_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mem_${i}") - p <> m + val ports: Seq[ClockedIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") + p.bits <> m + p.clock := BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) p }) - (ports ++ clock, Nil) + (ports, Nil) } }) class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { - val clock = if (!system.mmio_axi4.isEmpty) { - Some(BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock)) - } else { - None - } - val ports = system.mmio_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mmio_${i}") - p <> m + val ports: Seq[ClockedIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") + p.bits <> m + p.clock := BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) p }) - (ports ++ clock, Nil) + (ports, Nil) } }) class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({ (system: CanHaveSlaveAXI4Port) => { - val clock = if (!system.l2_frontend_bus_axi4.isEmpty) { - Some(BoreHelper("axi4_fbus_clock", system.asInstanceOf[BaseSubsystem].fbus.module.clock)) - } else { - None - } - val ports = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_fbus_${i}") - m <> p + val ports: Seq[ClockedIO[AXI4Bundle]] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}") + m <> p.bits + p.clock := BoreHelper("axi4_fbus_clock", system.asInstanceOf[BaseSubsystem].fbus.module.clock) p }) - (ports ++ clock, Nil) + (ports, Nil) } }) class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryBlockDeviceModuleImp) => { - val ports = system.bdev.map({ bdev => - val p = IO(new BlockDeviceIO()(system.p)).suggestName("blockdev") - val clock = BoreHelper("blkdev_clk", system.outer.controller.get.module.clock) - p <> bdev - Seq(p, clock) - }).getOrElse(Nil) + val ports: Seq[ClockedIO[BlockDeviceIO]] = system.bdev.map({ bdev => + val p = IO(new ClockedIO(new BlockDeviceIO()(system.p))).suggestName("blockdev") + p.clock := BoreHelper("blkdev_clk", system.outer.controller.get.module.clock) + p.bits <> bdev + p + }).toSeq (ports, Nil) } }) class WithNICIOPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryIceNICModuleImp) => { - val port = system.net.map({ n => - val p = IO(new NICIOvonly).suggestName("nic") - val clock = BoreHelper("nic_clk", system.outer.icenicOpt.get.module.clock) - p <> n - Seq(p, clock) - }).getOrElse(Nil) - (port.toSeq, Nil) + val ports: Seq[ClockedIO[NICIOvonly]] = system.net.map({ n => + val p = IO(new ClockedIO(new NICIOvonly)).suggestName("nic") + p.clock := BoreHelper("nic_clk", system.outer.icenicOpt.get.module.clock) + p.bits <> n + p + }).toSeq + (ports, Nil) } }) class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({ (system: TraceGenSystemModuleImp) => { - val success = IO(Output(Bool())).suggestName("success") + val success: Bool = IO(Output(Bool())).suggestName("success") success := system.success (Seq(success), Nil) } @@ -341,7 +332,7 @@ class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({ class WithTraceIOPunchthrough extends OverrideIOBinder({ (system: CanHaveTraceIOModuleImp) => { - val ports = system.traceIO.map { t => + val ports: Option[TraceOutputTop] = system.traceIO.map { t => val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace") trace <> t trace From facef464e69e786323e22bedc3ed8a60ea1429c6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 9 Sep 2020 00:15:02 -0700 Subject: [PATCH 176/457] Update BridgeBinders | fix runtime HarnessBinder port type checks --- .../src/main/scala/HarnessBinders.scala | 13 ++-- .../src/main/scala/BridgeBinders.scala | 66 ++++++++----------- 2 files changed, 35 insertions(+), 44 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index f427d44e..90365b39 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -35,15 +35,15 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer object ApplyHarnessBinders { def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { val pm = portMap.withDefaultValue(Nil) - map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) - } + map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } } } -class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.map(_.asInstanceOf[S]) + val pts = ports.collect({case p: S => p}) + require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") t match { case system: T => fn(system, th, pts) case _ => Nil @@ -52,10 +52,11 @@ class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, ) }) -class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.map(_.asInstanceOf[S]) + val pts = ports.collect({case p: S => p}) + require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") t match { case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts) case _ => Nil diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 0eb61a05..5dcddcfa 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -26,7 +26,7 @@ import ariane.ArianeTile import boom.common.{BoomTile} import barstools.iocell.chisel._ -import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} +import chipyard.iobinders.{ClockedIO, IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} import chipyard.{HasHarnessSignalReferences} import chipyard.harness._ @@ -56,57 +56,44 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val clock = ports.collectFirst({case c: Clock => c}) - val p: Parameters = chipyard.iobinders.GetSystemParameters(system) - ports.filter(_.isInstanceOf[SerialIO]).map { - case s: SerialIO => withClockAndReset(clock.get, th.harnessReset) { - SerialBridge(clock.get, s, MainMemoryConsts.globalName)(p) + (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + ports.map { p => + withClockAndReset(p.clock, th.harnessReset) { + SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system)) } - case _ => } Nil } }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val clock = ports.collectFirst({case c: Clock => c}) - ports.map { - case p: NICIOvonly => withClockAndReset(clock.get, th.harnessReset) { NICBridge(clock.get, p)(system.p) } - case _ => - } + (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + ports.map { p => withClockAndReset(p.clock, th.harnessReset) { NICBridge(p.clock, p.bits)(system.p) } } Nil } }) class WithUARTBridge extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => - ports.map { case p: UARTPortIO => UARTBridge(th.harnessClock, p)(system.p) }; Nil + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => + ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val clock = ports.collectFirst({case c: Clock => c}) - ports.map { - case p: BlockDeviceIO => BlockDevBridge(clock.get, p, th.harnessReset.toBool)(system.p) - case _ => - } + (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + ports.map { p => BlockDevBridge(p.clock, p.bits, th.harnessReset.toBool)(system.p) } Nil } }) class WithFASEDBridge extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { implicit val p: Parameters = GetSystemParameters(system) - val clock = ports.collectFirst({case c: Clock => c}) - val axi4_ports = ports.collect { case p: AXI4Bundle => p } - (axi4_ports zip system.memAXI4Node.edges.in).map { case (axi4: AXI4Bundle, edge) => - val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, - axi4.ar.bits.addr.getWidth, - axi4.ar.bits.id.getWidth) + (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) => + val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, + axi4.bits.ar.bits.addr.getWidth, + axi4.bits.ar.bits.id.getWidth) system match { - case s: BaseSubsystem => FASEDBridge(clock.get, axi4, th.harnessReset.asBool, + case s: BaseSubsystem => FASEDBridge(axi4.clock, axi4.bits, th.harnessReset.asBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)), @@ -119,22 +106,25 @@ class WithFASEDBridge extends OverrideHarnessBinder({ }) class WithTracerVBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => - withClockAndReset(tileTrace.clock, tileTrace.reset) { TracerVBridge(tileTrace)(system.p) } - )} + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + ports.map { p => + p.traces.map( + tileTrace => withClockAndReset(tileTrace.clock, tileTrace.reset) { TracerVBridge(tileTrace)(system.p) } + ) + } + Nil } }) class WithDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => - ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => + ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil }) class WithTraceGenBridge extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => - ports.map { case p: Bool => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => + ports.map { p => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ From 15d53e2cda499f46c9f3ddc727ae35a95461ecce Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 9 Sep 2020 15:12:37 -0700 Subject: [PATCH 177/457] Bump to the latest Rocket --- .../src/main/scala/config/SodorConfigs.scala | 101 +++++++++++++++++- generators/riscv-sodor | 2 +- 2 files changed, 99 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 1e1b7e51..335e7c4e 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -4,7 +4,7 @@ import chisel3._ import freechips.rocketchip.config.{Config} -class SodorConfig extends Config( +class Sodor1StageConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithTiedOffDebug ++ @@ -19,6 +19,101 @@ class SodorConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new sodor.common.WithNSodorCores(1) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) \ No newline at end of file + new freechips.rocketchip.system.BaseConfig) + +class Sodor2StageConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class Sodor3StageConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class Sodor3StageSinglePortConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class Sodor5StageConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class SodorUCodeConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index e635b4ae..70033f04 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit e635b4ae41d3d5ac570b8766877003e1c60f48ff +Subproject commit 70033f041a5e46fdc2c7c473fb8fa509bddc2e2d From a5385c0a54d9291ba0ec444c58042fdcc387ee98 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 10 Sep 2020 23:20:37 -0700 Subject: [PATCH 178/457] Update testchipip/icenet to use rocket-chip Located API --- .../chipyard/src/main/scala/DigitalTop.scala | 2 - .../src/main/scala/HarnessBinders.scala | 28 ++++++----- .../chipyard/src/main/scala/IOBinders.scala | 48 +++++++++---------- .../src/main/scala/BridgeBinders.scala | 14 +++--- .../src/main/scala/TargetConfigs.scala | 2 +- generators/icenet | 2 +- generators/testchipip | 2 +- 7 files changed, 49 insertions(+), 49 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index ddcf66f3..a065b6be 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -32,11 +32,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp - with testchipip.CanHavePeripheryBlockDeviceModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 90365b39..06a3af5d 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -20,10 +20,10 @@ import barstools.iocell.chisel._ import testchipip._ import chipyard.HasHarnessSignalReferences -import chipyard.iobinders.ClockedIO +import chipyard.iobinders.GetSystemParameters import tracegen.{TraceGenSystemModuleImp} -import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import scala.reflect.{ClassTag} @@ -89,24 +89,27 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { - ports.map { p => SimBlockDevice.connect(p.clock, th.harnessReset.asBool, Some(p.bits))(system.p) } + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } Nil } }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { - ports.map { p => withClockAndReset(p.clock, th.harnessReset) { BlockDeviceModel.connect(Some(p.bits))(system.p) } } + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } Nil } }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { - ports.map { p => - withClockAndReset(p.clock, th.harnessReset) { - NicLoopback.connect(Some(p.bits), system.p(NICKey)) + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { n => + withClockAndReset(n.clock, th.harnessReset) { + NicLoopback.connect(Some(n.bits), p(NICKey)) } } Nil @@ -114,8 +117,9 @@ class WithLoopbackNIC extends OverrideHarnessBinder({ }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { - ports.map { p => SimNetwork.connect(Some(p.bits), p.clock, th.harnessReset.asBool) } + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } Nil } }) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 969ad571..78233118 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util.experimental.{BoringUtils} import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.config._ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} @@ -22,7 +22,7 @@ import tracegen.{TraceGenSystemModuleImp} import barstools.iocell.chisel._ import testchipip._ -import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.GlobalResetSchemeKey @@ -43,15 +43,15 @@ import scala.reflect.{ClassTag} case object IOBinders extends Field[Map[String, (Any) => (Seq[Data], Seq[IOCell])]]( Map[String, (Any) => (Seq[Data], Seq[IOCell])]().withDefaultValue((Any) => (Nil, Nil)) ) - object ApplyIOBinders { def apply(sys: LazyModule, map: Map[String, (Any) => (Seq[Data], Seq[IOCell])]): (Iterable[Data], Iterable[IOCell], Map[String, Seq[Data]]) = { val lzy = map.map({ case (s,f) => s -> f(sys) }) val imp = map.map({ case (s,f) => s -> f(sys.module) }) + val unzipped = (lzy.values ++ imp.values).unzip - val ports: Iterable[Data] = lzy.values.map(_._1).flatten ++ imp.values.map(_._1).flatten - val cells: Iterable[IOCell] = lzy.values.map(_._2).flatten ++ imp.values.map(_._2).flatten + val ports: Iterable[Data] = unzipped._1.flatten + val cells: Iterable[IOCell] = unzipped._2.flatten val portMap: Map[String, Seq[Data]] = map.keys.map(k => k -> (lzy(k)._1 ++ imp(k)._1)).toMap (ports, cells, portMap) } @@ -72,13 +72,17 @@ object GetSystemParameters { } } +class IOBinder(f: (View, View, View) => PartialFunction[Any, Any]) extends Config(f) + // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { - case system: T => fn(system) + case system: T => + val (ports, cells) = fn(system) + (ports, cells) case _ => (Nil, Nil) } }) @@ -87,14 +91,16 @@ class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implic // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { case system: T => val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) val h = fn(system) - (r._1 ++ h._1, r._2 ++ h._2) + val ports = r._1 ++ h._1 + val cells = r._2 ++ h._2 + (ports, cells) case _ => (Nil, Nil) } }) @@ -116,11 +122,6 @@ object BoreHelper { case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) -class ClockedIO[T <: Data](gen: T) extends Bundle { - val clock = Output(Clock()) - val bits = gen - override def cloneType: this.type = (new ClockedIO(DataMirror.internal.chiselTypeClone[T](gen))).asInstanceOf[this.type] -} class WithGPIOCells extends OverrideIOBinder({ (system: HasPeripheryGPIOModuleImp) => { @@ -252,10 +253,7 @@ class WithDebugIOCells extends OverrideIOBinder({ class WithSerialIOCells extends OverrideIOBinder({ (system: CanHavePeripherySerial) => system.serial.map({ s => val sys = system.asInstanceOf[BaseSubsystem] - val clocked_serial = Wire(new ClockedIO(DataMirror.internal.chiselTypeClone[SerialIO](s))).suggestName("serial_wire") - clocked_serial.clock := BoreHelper("serial_clock", sys.fbus.module.clock) - clocked_serial.bits <> s - val (port, cells) = IOCell.generateIOFromSignal(clocked_serial, Some("serial"), sys.p(IOCellKey)) + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial"), sys.p(IOCellKey)) port.suggestName("serial") (Seq(port), cells) }).getOrElse((Nil, Nil)) @@ -299,11 +297,10 @@ class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({ }) class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => { + (system: CanHavePeripheryBlockDevice) => { val ports: Seq[ClockedIO[BlockDeviceIO]] = system.bdev.map({ bdev => - val p = IO(new ClockedIO(new BlockDeviceIO()(system.p))).suggestName("blockdev") - p.clock := BoreHelper("blkdev_clk", system.outer.controller.get.module.clock) - p.bits <> bdev + val p = IO(new ClockedIO(new BlockDeviceIO()(GetSystemParameters(system)))).suggestName("blockdev") + p <> bdev p }).toSeq (ports, Nil) @@ -311,11 +308,10 @@ class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({ }) class WithNICIOPunchthrough extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => { - val ports: Seq[ClockedIO[NICIOvonly]] = system.net.map({ n => + (system: CanHavePeripheryIceNIC) => { + val ports: Seq[ClockedIO[NICIOvonly]] = system.icenicOpt.map({ n => val p = IO(new ClockedIO(new NICIOvonly)).suggestName("nic") - p.clock := BoreHelper("nic_clk", system.outer.icenicOpt.get.module.clock) - p.bits <> n + p <> n p }).toSeq (ports, Nil) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 5dcddcfa..f42a1adf 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart._ import testchipip._ -import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} @@ -26,7 +26,7 @@ import ariane.ArianeTile import boom.common.{BoomTile} import barstools.iocell.chisel._ -import chipyard.iobinders.{ClockedIO, IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} +import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} import chipyard.{HasHarnessSignalReferences} import chipyard.harness._ @@ -67,8 +67,9 @@ class WithSerialBridge extends OverrideHarnessBinder({ }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { - ports.map { p => withClockAndReset(p.clock, th.harnessReset) { NICBridge(p.clock, p.bits)(system.p) } } + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + val p: Parameters = GetSystemParameters(system) + ports.map { n => withClockAndReset(n.clock, th.harnessReset) { NICBridge(n.clock, n.bits)(p) } } Nil } }) @@ -79,8 +80,9 @@ class WithUARTBridge extends OverrideHarnessBinder({ }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { - ports.map { p => BlockDevBridge(p.clock, p.bits, th.harnessReset.toBool)(system.p) } + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) } Nil } }) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0d8cd367..2dede960 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.LazyModule -import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} +import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} diff --git a/generators/icenet b/generators/icenet index bb23c81f..277a9080 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit bb23c81fcfbdfde6767c5b7daa95f8f9436fb7db +Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 diff --git a/generators/testchipip b/generators/testchipip index 6f4e7ae2..70df93e5 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6f4e7ae2c94e867f08cd0d408a106fba2f389de2 +Subproject commit 70df93e5867e6676e62bb23b11b9086471fdecf7 From e98a0f172f92cbf37d6aed258267a502b90fc1fa Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Sep 2020 16:55:25 -0700 Subject: [PATCH 179/457] Connected UART nicely --- fpga/Makefile | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 6 +- fpga/src/main/scala/vcu118/IOBinders.scala | 69 -------------------- fpga/src/main/scala/vcu118/Shell.scala | 0 fpga/src/main/scala/vcu118/TestHarness.scala | 25 +++---- 5 files changed, 11 insertions(+), 91 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/IOBinders.scala delete mode 100644 fpga/src/main/scala/vcu118/Shell.scala diff --git a/fpga/Makefile b/fpga/Makefile index 643e0c67..f3f6308b 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -26,7 +26,7 @@ CONFIG := FakeBringupConfig CONFIG_PACKAGE := chipyard.fpga.vcu118 GENERATOR_PACKAGE := chipyard TB := none # unused -TOP := ChipTop +TOP := VCU118Platform # setup the board to use BOARD ?= arty diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index a98aa3cf..ba88377f 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -21,8 +21,7 @@ import sifive.fpgashells.shell.{DesignKey} import chipyard.{BuildTop} class WithChipyardBuildTop extends Config((site, here, up) => { - //case DesignKey => { (p:Parameters) => p(BuildTop)(p) } - case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) } + case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } }) class WithBringupUARTs extends Config((site, here, up) => { @@ -32,7 +31,6 @@ class WithBringupUARTs extends Config((site, here, up) => { }) class FakeBringupConfig extends Config( - new WithUARTConnection1 ++ new WithBringupUARTs ++ new WithChipyardBuildTop ++ new chipyard.config.WithBootROM ++ @@ -47,5 +45,5 @@ class FakeBringupConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala deleted file mode 100644 index dfec55cc..00000000 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ /dev/null @@ -1,69 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ -import sifive.fpgashells.shell._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} -import freechips.rocketchip.diplomacy._ - -class WithUARTConnection1 extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - val io_uart_pins = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } - (io_uart_pins zip system.uart) map { case (p, r) => p <> r } - - val harnessFn = (th: HasHarnessSignalReferences) => { - println(th) - println("Got here - -- - - - ") - Nil - } - //val harnessFn = (baseTh: HasHarnessSignalReferences) => { - // println("DEBUG: ---------------------- 0") - // baseTh match { case th: VCU118Shell => - // println("DEBUG: ---------------------- 1") - - // val io_uart_pins_bb = p(PeripheryUARTKey) map { c => BundleBridgeSource(() => (new UARTPortIO(c))) } - - // InModuleBody { - // (io_uart_pins_bb zip io_uart_pins) map { case (p, r) => p.bundle <> r } - // } - - // require(p(PeripheryUARTKey).size >= 1) - - // println("DEBUG: ---------------------- 2") - - // th.designParameters(UARTOverlayKey).foreach { uok => - // println("DEBUG: ---------------------- 3") - // uok.place(UARTDesignInput(io_uart_pins_bb(0))).overlayOutput - // } - - // Nil - // } - //} - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - diff --git a/fpga/src/main/scala/vcu118/Shell.scala b/fpga/src/main/scala/vcu118/Shell.scala deleted file mode 100644 index e69de29b..00000000 diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 6da984bf..0bce7c97 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -5,32 +5,23 @@ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp} import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy.{InModuleBody} +import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell._ import sifive.fpgashells.clocks._ -import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} +import sifive.blocks.devices.uart._ -class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell with HasHarnessSignalReferences { - val pllResetAsReset = InModuleBody{ Wire(Reset()) } +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { - InModuleBody { - pllResetAsReset := pllReset - } + require(p(PeripheryUARTKey).size >= 1) - lazy val harnessClock = this.module.sysclk - lazy val harnessReset = pllResetAsReset.getWrappedValue - val success = false.B - lazy val dutReset = pllResetAsReset.getWrappedValue - - // must be after HasHarnessSignalReferences assignments - println(s"DEBUG: ----- sz:${topDesign.harnessFunctions.size}") - topDesign match { case d: HasTestHarnessFunctions => - println(s"DEBUG: ----- sz:${d.harnessFunctions.size}") - d.harnessFunctions.foreach(_(this)) + designParameters(UARTOverlayKey).foreach { uok => + topDesign match { case td: HasPlatformIO => + io_uart_bb)) + } } } From 382e5f1ae8061b0934e5d53d7aa89d473c852a50 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Sep 2020 17:02:22 -0700 Subject: [PATCH 180/457] Add forgotten file --- fpga/src/main/scala/vcu118/Platform.scala | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 fpga/src/main/scala/vcu118/Platform.scala diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala new file mode 100644 index 00000000..3a4cac8a --- /dev/null +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -0,0 +1,40 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{Analog, IO} + +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} +import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} +import freechips.rocketchip.config.{Parameters} + +import chipyard.{BuildSystem} + +import sifive.blocks.devices.uart._ + +trait HasPlatformIO { + val io_uart_bb: BundleBridgeSource[UARTPortIO] +} + +class VCU118Platform(override implicit val p: Parameters) extends LazyModule + with HasPlatformIO { + + val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") + + // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design + // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey)(0)))) + + override lazy val module = new VCU118PlatformModule(this) +} + +class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) { + + _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => + // create UART pins in Platform + //val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } + + //(io_uart_pins_temp zip sys.uart) map { case (p, r) => p <> r } + _outer.io_uart_bb.bundle <> sys.uart(0) + } + +} From 69bf39bf13053f566a32a5c6d2e05403b95bfd60 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 12 Sep 2020 18:18:13 -0700 Subject: [PATCH 181/457] Added more overlays | Closer to bringup platform --- fpga/src/main/scala/vcu118/Configs.scala | 11 +- .../main/scala/vcu118/CustomOverlays.scala | 65 ++++ fpga/src/main/scala/vcu118/FMCUtil.scala | 334 ++++++++++++++++++ fpga/src/main/scala/vcu118/Platform.scala | 45 ++- fpga/src/main/scala/vcu118/TestHarness.scala | 54 ++- 5 files changed, 488 insertions(+), 21 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/CustomOverlays.scala create mode 100644 fpga/src/main/scala/vcu118/FMCUtil.scala diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ba88377f..42663f0b 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,6 +17,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.fpgashells.shell.{DesignKey} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} @@ -24,14 +25,20 @@ class WithChipyardBuildTop extends Config((site, here, up) => { case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } }) -class WithBringupUARTs extends Config((site, here, up) => { +class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) + case PeripherySPIKey => List( + SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64004000L))) + case PeripheryI2CKey => List( + I2CParams(address = BigInt(0x64005000L))) + case VCU118ShellPMOD => "SDIO" }) class FakeBringupConfig extends Config( - new WithBringupUARTs ++ + new WithBringupPeripherals ++ new WithChipyardBuildTop ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala new file mode 100644 index 00000000..3d51c3e7 --- /dev/null +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -0,0 +1,65 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ + +import freechips.rocketchip.diplomacy._ + +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell.xilinx._ + +import chipyard.fpga.vcu118.{FMCPMap} + +/* Connect the I2C to certain FMC pins */ +class BringupI2CVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) + extends I2CXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(shellInput.index == 0) // only support 1 I2C <-> FMC connection + val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2"))) + val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)), + (i2cLocations(shellInput.index)(1), IOPin(io.sda))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + } } +} + +class BringupI2CVCU118ShellPlacer(val shell: VCU118Shell, val shellInput: I2CShellInput)(implicit val valName: ValName) + extends I2CShellPlacer[VCU118Shell] +{ + def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +/* Connect the UART to certain FMC pins */ +class BringupUARTVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) + extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) +{ + shell { InModuleBody { + val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused + (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused + (FMCPMap("C15"), IOPin(io.rxd)), + (FMCPMap("C14"), IOPin(io.txd))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + + // add pullup on ctsn (ctsn is an input that is not used or driven) + packagePinsWithPackageIOs take 1 foreach { case (pin, io) => { + shell.xdc.addPullup(io) + } } + } } +} + +class BringupUARTVCU118ShellPlacer(shell: VCU118Shell, val shellInput: UARTShellInput)(implicit val valName: ValName) + extends UARTShellPlacer[VCU118Shell] { + def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +/* Connect SPI to ADI device */ diff --git a/fpga/src/main/scala/vcu118/FMCUtil.scala b/fpga/src/main/scala/vcu118/FMCUtil.scala new file mode 100644 index 00000000..00982585 --- /dev/null +++ b/fpga/src/main/scala/vcu118/FMCUtil.scala @@ -0,0 +1,334 @@ +package chipyard.fpga.vcu118 + +import scala.collection.immutable.HashMap + +// TODO: was typed by hand, so this needs a once-over before it can be considered trustworthy + +object FMCMap { + // Take an FMC pin name and return the VCU118 package pin + // See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf + // Pages 97-98 + // Omitted pins are not connected to a GPIO + def apply(fmcPin: String): String = HashMap( + "C10" -> "BD13", + "C11" -> "BE13", + "C14" -> "BB13", + "C15" -> "BB12", + "C18" -> "AW8", + "C19" -> "AW7", + "C22" -> "AP12", + "C23" -> "AR12", + "C26" -> "AL14", + "C27" -> "AM14", + "D1" -> "AK35", + "D8" -> "BF10", + "D9" -> "BF9", + "D11" -> "BE14", + "D12" -> "BF14", + "D14" -> "BA14", + "D15" -> "BB14", + "D17" -> "AY8", + "D18" -> "AY7", + "D20" -> "AR14", + "D21" -> "AT14", + "D23" -> "AN16", + "D24" -> "AP16", + "D26" -> "AK15", + "D27" -> "AL15", + "F1" -> "BA7", + "G2" -> "AV14", + "G3" -> "AV13", + "G6" -> "AY9", + "G7" -> "BA9", + "G9" -> "BD12", + "G10" -> "BE12", + "G12" -> "BE15", + "G13" -> "BF15", + "G15" -> "BC14", + "G16" -> "BC13", + "G18" -> "AV9", + "G19" -> "AV8", + "G21" -> "AW11", + "G22" -> "AY10", + "G24" -> "AW13", + "G25" -> "AY13", + "G27" -> "AT12", + "G28" -> "AU12", + "G30" -> "AN15", + "G31" -> "AP15", + "G33" -> "AM13", + "G34" -> "AM12", + "G36" -> "AK14", + "G37" -> "AK13", + "H2" -> "BB7", + "H4" -> "BC9", + "H5" -> "BC8", + "H7" -> "BC11", + "H8" -> "BD11", + "H10" -> "BF12", + "H11" -> "BF11", + "H13" -> "BC15", + "H14" -> "BD15", + "H16" -> "BA16", + "H17" -> "BA15", + "H19" -> "BB16", + "H20" -> "BC16", + "H22" -> "AW12", + "H23" -> "AY12", + "H25" -> "AU11", + "H26" -> "AV11", + "H28" -> "AP13", + "H29" -> "AR13", + "H31" -> "AV10", + "H32" -> "AW10", + "H34" -> "AK12", + "H35" -> "AL12", + "H37" -> "AJ13", + "H38" -> "AJ12" + )(fmcPin) +} + +object FMCPMap { + // Take an FMC+ pin name and return the VCU118 package pin + // See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf + // Pages 100-106 + // Omitted pins are not connected to a GPIO + def apply(fmcpPin: String): String = HashMap( + "A2" -> "AN45", + "A3" -> "AN46", + "A6" -> "AL45", + "A7" -> "AL45", + "A10" -> "AJ45", + "A11" -> "AJ46", + "A14" -> "W45", + "A15" -> "W46", + "A18" -> "U45", + "A19" -> "U46", + "A22" -> "AP42", + "A23" -> "AP43", + "A26" -> "AM42", + "A27" -> "AM43", + "A30" -> "AL40", + "A31" -> "AL41", + "A34" -> "T42", + "A35" -> "T43", + "A38" -> "P42", + "A39" -> "P43", + "B4" -> "AF43", + "B5" -> "AF44", + "B8" -> "AG45", + "B9" -> "AG46", + "B12" -> "N45", + "B13" -> "N46", + "B16" -> "R45", + "B17" -> "R46", + "B24" -> "AJ40", + "B25" -> "AJ41", + "B28" -> "AK42", + "B29" -> "AK43", + "B32" -> "K42", + "B33" -> "K43", + "B36" -> "M42", + "B37" -> "M43", + "C2" -> "AT42", + "C3" -> "AT43", + "C6" -> "AR45", + "C7" -> "AR46", + "C10" -> "AT35", + "C11" -> "AT36", + "C14" -> "AP35", + "C15" -> "AR35", + "C18" -> "AG31", + "C19" -> "AH31", + "C22" -> "R31", + "C23" -> "P31", + "C26" -> "V33", + "C27" -> "V34", + "D1" -> "AK35", + "D8" -> "AL30", + "D9" -> "AL31", + "D11" -> "AP38", + "D12" -> "AR38", + "D14" -> "AJ33", + "D15" -> "AK33", + "D17" -> "AJ35", + "D18" -> "AJ36", + "D20" -> "R34", + "D21" -> "P34", + "D23" -> "Y32", + "D24" -> "W32", + "D26" -> "V32", + "D27" -> "U33", + "E2" -> "V15", + "E3" -> "U15", + "E6" -> "R14", + "E7" -> "P14", + "E9" -> "W14", + "E10" -> "V14", + "E12" -> "V13", + "E13" -> "U12", + "E15" -> "T14", + "E16" -> "R13", + "E18" -> "M15", + "E19" -> "L15", + "F1" -> "AM34", + "F4" -> "N14", + "F5" -> "N13", + "F7" -> "AA13", + "F8" -> "Y13", + "F10" -> "U11", + "F11" -> "T11", + "F13" -> "T16", + "F14" -> "T15", + "F16" -> "M13", + "F17" -> "M12", + "F19" -> "L14", + "F20" -> "L13", + "G2" -> "P35", + "G3" -> "P36", + "G6" -> "AL35", + "G7" -> "AL36", + "G9" -> "AT39", + "G10" -> "AT40", + "G12" -> "AK29", + "G13" -> "AK30", + "G15" -> "AH33", + "G16" -> "AH34", + "G18" -> "AG34", + "G19" -> "AH35", + "G21" -> "N32", + "G22" -> "M32", + "G24" -> "N34", + "G25" -> "N35", + "G27" -> "Y34", + "G28" -> "W34", + "G30" -> "U35", + "G31" -> "T36", + "G33" -> "P37", + "G34" -> "N37", + "G36" -> "L34", + "G37" -> "K34", + "H2" -> "AM33", + "H4" -> "AL32", + "H5" -> "AM32", + "H7" -> "AJ32", + "H8" -> "AK32", + "H10" -> "AR37", + "H11" -> "AT37", + "H13" -> "AP36", + "H14" -> "AP37", + "H16" -> "AJ30", + "H17" -> "AJ31", + "H19" -> "AG32", + "H20" -> "AG33", + "H22" -> "N33", + "H23" -> "M33", + "H25" -> "M35", + "H26" -> "L35", + "H28" -> "T34", + "H29" -> "T35", + "H31" -> "M36", + "H32" -> "L36", + "H34" -> "N38", + "H35" -> "M38", + "H37" -> "L33", + "H38" -> "K33", + "J6" -> "W12", + "J7" -> "V12", + "J9" -> "AA14", + "J10" -> "Y14", + "J12" -> "R12", + "J13" -> "P12", + "J15" -> "M11", + "J16" -> "L11", + "J18" -> "P15", + "J19" -> "N15", + "J21" -> "K12", + "J22" -> "J12", + "K7" -> "AA12", + "K8" -> "Y12", + "K10" -> "U13", + "K11" -> "T13", + "K13" -> "V16", + "K14" -> "U16", + "K16" -> "R11", + "K17" -> "P11", + "K19" -> "K14", + "K20" -> "K13", + "K22" -> "K11", + "K23" -> "J11", + "L4" -> "R40", + "L5" -> "R41", + "L8" -> "AB38", + "L9" -> "AB39", + "L12" -> "AF38", + "L13" -> "AF39", + "L16" -> "AN34", + "L17" -> "AN35", + "L20" -> "AN33", + "L21" -> "AP33", + "L24" -> "AK34", + "L25" -> "AL34", + "L28" -> "AM36", + "L29" -> "AN36", + "M2" -> "AU45", + "M3" -> "AU46", + "M6" -> "AW45", + "M7" -> "AW46", + "M10" -> "BA45", + "M11" -> "BA46", + "M14" -> "BC45", + "M15" -> "BC46", + "M18" -> "W40", + "M19" -> "W41", + "M22" -> "U40", + "M23" -> "U41", + "M26" -> "H42", + "M27" -> "H43", + "M30" -> "F42", + "M31" -> "F43", + "M34" -> "D42", + "M35" -> "D43", + "M38" -> "B42", + "M39" -> "B43", + "Y2" -> "AV42", + "Y3" -> "AV43", + "Y6" -> "BB42", + "Y7" -> "BB43", + "Y10" -> "AE45", + "Y11" -> "AE46", + "Y14" -> "AC45", + "Y15" -> "AC46", + "Y18" -> "AA45", + "Y19" -> "AA46", + "Y22" -> "Y43", + "Y23" -> "Y44", + "Y26" -> "AE40", + "Y27" -> "AE41", + "Y30" -> "AA40", + "Y31" -> "AA41", + "Y34" -> "J45", + "Y35" -> "J46", + "Y38" -> "E45", + "Y39" -> "E46", + "Z1" -> "AM29", + "Z4" -> "AY42", + "Z5" -> "AY43", + "Z8" -> "BD42", + "Z9" -> "BD43", + "Z12" -> "AD43", + "Z13" -> "AD44", + "Z16" -> "AB43", + "Z17" -> "AB44", + "Z20" -> "AN40", + "Z21" -> "AN41", + "Z24" -> "AG40", + "Z25" -> "AG41", + "Z28" -> "AC40", + "Z29" -> "AC41", + "Z32" -> "L45", + "Z33" -> "L46", + "Z36" -> "G45", + "Z37" -> "G46" + )(fmcpPin) +} diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index 3a4cac8a..47e64de0 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -10,31 +10,46 @@ import freechips.rocketchip.config.{Parameters} import chipyard.{BuildSystem} import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ -trait HasPlatformIO { - val io_uart_bb: BundleBridgeSource[UARTPortIO] +trait HasVCU118PlatformIO { + val io_uart: Seq[UARTPortIO] + val io_spi: Seq[SPIPortIO] + val io_i2c: Seq[I2CPort] } -class VCU118Platform(override implicit val p: Parameters) extends LazyModule - with HasPlatformIO { +class VCU118Platform(override implicit val p: Parameters) extends LazyModule { val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey)(0)))) - override lazy val module = new VCU118PlatformModule(this) } -class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) { +class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) + with HasVCU118PlatformIO { - _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => - // create UART pins in Platform - //val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } - - //(io_uart_pins_temp zip sys.uart) map { case (p, r) => p <> r } - _outer.io_uart_bb.bundle <> sys.uart(0) + val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => + val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") } + (io_uart_pins_temp zip sys.uart).map { case (io, sysio) => + io <> sysio + } + io_uart_pins_temp } + val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp => + val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") } + (io_spi_pins_temp zip sys.spi).map { case (io, sysio) => + io <> sysio + } + io_spi_pins_temp + } + + val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp => + val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") } + (io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) => + io <> sysio + } + io_i2c_pins_temp + } } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 0bce7c97..31f3c0ff 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -13,14 +13,60 @@ import sifive.fpgashells.shell._ import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { - require(p(PeripheryUARTKey).size >= 1) - designParameters(UARTOverlayKey).foreach { uok => - topDesign match { case td: HasPlatformIO => - io_uart_bb)) + /*** UART ***/ + require(p(PeripheryUARTKey).size == 2) + + // 1st UART goes to the VCU118 dedicated UART + + // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design + // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).head))) + designParameters(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_uart_bb.bundle <> dutMod.io_uart.head + } + } + + // 2nd UART goes to the FMC UART + + val uart_fmc = Overlay(UARTOverlayKey, new chipyard.fpga.vcu118.bringup.BringupUARTVCU118ShellPlacer(this, UARTShellInput())) + + val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).last))) + designParameters(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_uart_bb_2.bundle <> dutMod.io_uart.last + } + } + + /*** SPI ***/ + require(p(PeripherySPIKey).size >= 1) + + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head))) + designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_spi_bb.bundle <> dutMod.io_spi.head + } + } + + /*** I2C ***/ + require(p(PeripheryI2CKey).size >= 1) + + val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput())) + + val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) + designParameters(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_i2c_bb.bundle <> dutMod.io_i2c.head } } } From d2b42cee2ce7e5d22d3480ad7e6b9470a2507652 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 12 Sep 2020 23:31:54 -0700 Subject: [PATCH 182/457] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 70df93e5..a86c827c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 70df93e5867e6676e62bb23b11b9086471fdecf7 +Subproject commit a86c827ca6e4e9d8320117ef1223da0ff752d064 From be0c04123245a722bc9bd18484fd2cb5d40c1c07 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 13 Sep 2020 06:36:37 +0000 Subject: [PATCH 183/457] Bump Firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 522125da..c1cd3e5e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 522125da5d546544e3ce4492b6f105eeb93fcdf6 +Subproject commit c1cd3e5e7013b30f30508c7f47ff13180949eafe From 6c5bce5430002e60a676a9089f7d5822523e13ff Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 13 Sep 2020 11:59:16 -0700 Subject: [PATCH 184/457] Support Tilelink over serial --- .circleci/config.yml | 19 ++++++++++ .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 3 ++ .../chipyard/src/main/scala/DigitalTop.scala | 3 +- .../src/main/scala/HarnessBinders.scala | 36 ++++++++++++++++--- .../chipyard/src/main/scala/IOBinders.scala | 17 ++++++--- .../chipyard/src/main/scala/Subsystem.scala | 4 +-- .../main/scala/config/AbstractConfig.scala | 7 ++-- .../src/main/scala/config/ArianeConfigs.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 10 ++++-- .../src/main/scala/BridgeBinders.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 4 +-- generators/testchipip | 2 +- sims/firesim | 2 +- 14 files changed, 90 insertions(+), 22 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index eac8504a..1b239354 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -204,6 +204,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-dmirocket" + prepare-chipyard-tlserial: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-tlserial" prepare-chipyard-sha3: executor: main-env steps: @@ -302,6 +307,11 @@ jobs: steps: - run-tests: project-key: "chipyard-dmirocket" + chipyard-tlserial-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-tlserial" chipyard-sha3-run-tests: executor: main-env steps: @@ -456,6 +466,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-tlserial: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-sha3: requires: - install-riscv-toolchain @@ -551,6 +566,10 @@ workflows: requires: - prepare-chipyard-dmirocket + - chipyard-tlserial-run-tests: + requires: + - prepare-chipyard-tlserial + - chipyard-sha3-run-tests: requires: - prepare-chipyard-sha3 diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 703737cd..2a744e89 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -49,6 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" +mapping["chipyard-tlserial"]=" CONFIG=TLSerialRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 3e7b0285..cee04dd3 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -35,6 +35,9 @@ case $1 in chipyard-dmirocket) run_bmark ${mapping[$1]} ;; + chipyard-tlserial) + run_bmark ${mapping[$1]} + ;; chipyard-boom) run_bmark ${mapping[$1]} ;; diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index a065b6be..f967b8fc 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -16,7 +16,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port + with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the tilelink-over-serial backing memory + with testchipip.CanHavePeripheryTSISerial // Enables optionally adding the TSI serial-adapter and port with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 06a3af5d..c1b57f72 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -223,15 +223,15 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithTiedOffSerial extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { +class WithTiedOffTSISerial extends OverrideHarnessBinder({ + (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => SerialAdapter.tieoff(Some(p.bits)) } Nil } }) -class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { +class WithSimTSISerial extends OverrideHarnessBinder({ + (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset) when (ser_success) { th.success := true.B } @@ -240,6 +240,34 @@ class WithSimSerial extends OverrideHarnessBinder({ } }) +class WithSimTLSerial(withHarnessSerialAdapter: Boolean = false) extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + ports.map({ port => + withClockAndReset(port.clock, th.harnessReset) { + val lRam = LazyModule(new SerialRAM( + p(SerialTLKey).get.width, + p(SerialTLKey).get.memParams.master.size, + p(SerialTLKey).get.memParams.master.base, + managerEdge = system.serdesser.get.managerNode.edges.in(0), + clientEdge = system.serdesser.get.clientNode.edges.out(0) + )) + val ram = Module(lRam.module) + ram.io.ser <> port.bits + + require(lRam.serdesser.module.mergedParams == system.serdesser.get.module.mergedParams, + "Mismatch between chip-side diplomatic params and testram diplomatic params") + if (withHarnessSerialAdapter) { + val success = SerialAdapter.connectSimSerial(Some(ram.io.tsi_ser), port.clock, th.harnessReset.asBool) + when (success) { th.success := true.B } + } else { + SerialAdapter.tieoff(Some(ram.io.tsi_ser)) + } + } + }) + } +}) + class WithTraceGenSuccess extends OverrideHarnessBinder({ (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 78233118..03138cc1 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -250,11 +250,20 @@ class WithDebugIOCells extends OverrideIOBinder({ } }) -class WithSerialIOCells extends OverrideIOBinder({ - (system: CanHavePeripherySerial) => system.serial.map({ s => +class WithSerialTSIIOCells extends OverrideIOBinder({ + (system: CanHavePeripheryTSISerial) => system.serial_tsi.map({ s => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial"), sys.p(IOCellKey)) - port.suggestName("serial") + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tsi"), sys.p(IOCellKey)) + port.suggestName("serial_tsi") + (Seq(port), cells) + }).getOrElse((Nil, Nil)) +}) + +class WithSerialTLIOCells extends OverrideIOBinder({ + (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s => + val sys = system.asInstanceOf[BaseSubsystem] + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tl"), sys.p(IOCellKey)) + port.suggestName("serial_tl") (Seq(port), cells) }).getOrElse((Nil, Nil)) }) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 7f089ce1..35c41e0c 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile} -import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey} +import testchipip.{DromajoHelper, CanHavePeripheryTSISerial, SerialTSIKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripherySerial if p(SerialKey) => true + case _: CanHavePeripheryTSISerial if p(SerialTSIKey).nonEmpty => true case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true case _ => false }) { diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 950cb4b4..aed55d02 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -15,7 +15,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled - new chipyard.harness.WithSimSerial ++ // add SimSerial adapter for HTIF, if serial port is present + new chipyard.harness.WithSimTSISerial ++ // add SimSerial adapter for HTIF, if serial port is present new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled @@ -29,7 +29,8 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ new chipyard.iobinders.WithNICIOPunchthrough ++ - new chipyard.iobinders.WithSerialIOCells ++ + new chipyard.iobinders.WithSerialTSIIOCells ++ + new chipyard.iobinders.WithSerialTLIOCells ++ new chipyard.iobinders.WithDebugIOCells ++ new chipyard.iobinders.WithUARTIOCells ++ new chipyard.iobinders.WithGPIOCells ++ @@ -39,7 +40,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithExtInterruptIOCells ++ - new testchipip.WithTSI ++ // use testchipip serial offchip link + new testchipip.WithSerialTSI ++ // use testchipip serial offchip link new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 9f701331..b7c347dc 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -13,7 +13,7 @@ class ArianeConfig extends Config( new chipyard.config.AbstractConfig) class dmiArianeConfig extends Config( - new chipyard.harness.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithTiedOffTSISerial ++ // Tie off the serial port, override default instantiation of SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 16d298fb..9f2a97de 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config( // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.harness.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.harness.WithTiedOffTSISerial ++ // don't use serial to drive the chip, since we use DMI instead new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -182,4 +182,10 @@ class DividedClockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) - +class TLSerialRocketConfig extends Config( + new chipyard.harness.WithSimTLSerial(withHarnessSerialAdapter = true) ++ // add external TL backing memory, and external serial adapter + new testchipip.WithDefaultSerialTL ++ // support tilelink-over-serial + new testchipip.WithNoSerialTSI ++ // remove internal serial adapter + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory + new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f42a1adf..ebd629c7 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -56,7 +56,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => withClockAndReset(p.clock, th.harnessReset) { SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system)) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 2dede960..7df0bf61 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config( // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible // for signalling simulation termination under simulation success. This fragment can // be removed if you supply an auxiliary bridge that signals simulation termination - new testchipip.WithTSI ++ + new testchipip.WithSerialTSI ++ // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ // Required*: Scale default baud rate with periphery bus frequency @@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config( new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ - new testchipip.WithTSI ++ + new testchipip.WithSerialTSI ++ new testchipip.WithBlockDevice ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ diff --git a/generators/testchipip b/generators/testchipip index a86c827c..6f815737 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit a86c827ca6e4e9d8320117ef1223da0ff752d064 +Subproject commit 6f8157375451fbb32e9dae291f2c65878a2b1dcd diff --git a/sims/firesim b/sims/firesim index c1cd3e5e..2b52057e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c1cd3e5e7013b30f30508c7f47ff13180949eafe +Subproject commit 2b52057e158fd91d44c6259aa08869622a88040a From 72c0f4b3d3f2236c2477b0ab405f5fd26c58b520 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Sep 2020 16:37:20 -0700 Subject: [PATCH 185/457] Add GPIO Overlay --- fpga/src/main/scala/vcu118/BringupGPIOs.scala | 28 ++++++ fpga/src/main/scala/vcu118/Configs.scala | 19 +++- .../main/scala/vcu118/CustomOverlays.scala | 86 +++++++++++++++++++ fpga/src/main/scala/vcu118/Platform.scala | 10 +++ fpga/src/main/scala/vcu118/TestHarness.scala | 57 ++++++++++-- 5 files changed, 193 insertions(+), 7 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/BringupGPIOs.scala diff --git a/fpga/src/main/scala/vcu118/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/BringupGPIOs.scala new file mode 100644 index 00000000..1e11dfa2 --- /dev/null +++ b/fpga/src/main/scala/vcu118/BringupGPIOs.scala @@ -0,0 +1,28 @@ +package chipyard.fpga.vcu118.bringup + +import scala.collection.mutable.{LinkedHashMap} + +object BringupGPIOs { + // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD) + val pinMapping = LinkedHashMap( + // these connect to LEDs and switches on the VCU118 (and use 1.2V) + "led0" -> ("AT32", "LVCMOS12"), // 0 + "led1" -> ("AV34", "LVCMOS12"), // 1 + "led2" -> ("AY30", "LVCMOS12"), // 2 + "led3" -> ("BB32", "LVCMOS12"), // 3 + "led4" -> ("BF32", "LVCMOS12"), // 4 + "led5" -> ("AU37", "LVCMOS12"), // 5 + "led6" -> ("AV36", "LVCMOS12"), // 6 + "led7" -> ("BA37", "LVCMOS12"), // 7 + "sw0" -> ("B17", "LVCMOS12"), // 8 + "sw1" -> ("G16", "LVCMOS12"), // 9 + "sw2" -> ("J16", "LVCMOS12"), // 10 + "sw3" -> ("D21", "LVCMOS12") // 11 + ) + + // return list of names (ordered) + def names: Seq[String] = pinMapping.keys.toSeq + + // return number of GPIOs + def width: Int = pinMapping.size +} diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 42663f0b..7cc106d5 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. package chipyard.fpga.vcu118 +import math.min + import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ @@ -9,7 +11,6 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.spi._ @@ -20,6 +21,7 @@ import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} +import chipyard.fpga.vcu118.bringup.{BringupGPIOs} class WithChipyardBuildTop extends Config((site, here, up) => { case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } @@ -32,9 +34,22 @@ class WithBringupPeripherals extends Config((site, here, up) => { case PeripherySPIKey => List( SPIParams(rAddress = BigInt(0x64001000L)), SPIParams(rAddress = BigInt(0x64004000L))) + case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( I2CParams(address = BigInt(0x64005000L))) - case VCU118ShellPMOD => "SDIO" + case PeripheryGPIOKey => { + if (BringupGPIOs.width > 0) { + require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) + val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000)) + val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32) + List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => { + GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport)) + }) + } + else { + List.empty[GPIOParams] + } + } }) class FakeBringupConfig extends Config( diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index 3d51c3e7..ccb61f0e 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -1,13 +1,17 @@ package chipyard.fpga.vcu118.bringup import chisel3._ +import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ +import chipsalliance.rocketchip.config.{Parameters, Field} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ +import sifive.blocks.devices.gpio._ + import chipyard.fpga.vcu118.{FMCPMap} /* Connect the I2C to certain FMC pins */ @@ -63,3 +67,85 @@ class BringupUARTVCU118ShellPlacer(shell: VCU118Shell, val shellInput: UARTShell } /* Connect SPI to ADI device */ +class BringupSPIVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) + extends SDIOXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + val packagePinsWithPackageIOs = Seq((FMCPMap("H37"), IOPin(io.spi_clk)), + (FMCPMap("H19"), IOPin(io.spi_cs)), + (FMCPMap("H17"), IOPin(io.spi_dat(0))), + (FMCPMap("H28"), IOPin(io.spi_dat(1))), + (FMCPMap("H29"), IOPin(io.spi_dat(2))), + (FMCPMap("H16"), IOPin(io.spi_dat(3)))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + } } + packagePinsWithPackageIOs drop 1 foreach { case (pin, io) => { + shell.xdc.addPullup(io) + shell.xdc.addIOB(io) + } } + } } +} + +class BringupSPIVCU118ShellPlacer(shell: VCU118Shell, val shellInput: SPIShellInput)(implicit val valName: ValName) + extends SPIShellPlacer[VCU118Shell] { + def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +// TODO: Move this to a different location +// SPI device description for ADI part +class ADISPIDevice(spi: Device, maxMHz: Double = 1) extends SimpleDevice("clkgen", Seq("analog,adi9516-4")) { + override def parent = Some(spi) + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + val extra = Map("spi-max-frequency" -> Seq(ResourceInt(maxMHz * 1000000))) + Description(name, mapping ++ extra) + } +} + +/* Connect GPIOs to FMC */ +abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) + extends GPIOPlacedOverlay(name, di, si) +{ + def shell: XilinxShell + + shell { InModuleBody { + (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) => + val iobuf = Module(new IOBUF) + iobuf.suggestName(s"gpio_iobuf") + attach(ioPin, iobuf.io.IO) + sinkPin.i.ival := iobuf.io.O + iobuf.io.T := !sinkPin.o.oe + iobuf.io.I := sinkPin.o.oval + } + } } +} + +class BringupGPIOVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) + extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(gpioNames.length == io.gpio.length) + + val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => + val (pin, iostd) = BringupGPIOs.pinMapping(name) + (pin, iostd, IOPin(io)) + } + + packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, iostd) + // TODO: no drive strength found + //if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } + } } + } } +} + +class BringupGPIOVCU118ShellPlacer(shell: VCU118Shell, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) + extends GPIOShellPlacer[VCU118Shell] { + def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) +} + + diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index 47e64de0..8f9a1ae8 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -12,11 +12,13 @@ import chipyard.{BuildSystem} import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ trait HasVCU118PlatformIO { val io_uart: Seq[UARTPortIO] val io_spi: Seq[SPIPortIO] val io_i2c: Seq[I2CPort] + val io_gpio: Seq[GPIOPortIO] } class VCU118Platform(override implicit val p: Parameters) extends LazyModule { @@ -52,4 +54,12 @@ class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleIm } io_i2c_pins_temp } + + val io_gpio = _outer.lazySystem.module match { case sys: HasPeripheryGPIOModuleImp => + val io_gpio_pins_temp = p(PeripheryGPIOKey).zipWithIndex.map { case (p, i) => IO(new GPIOPortIO(p)).suggestName(s"gpio_$i") } + (io_gpio_pins_temp zip sys.gpio).map { case (io, sysio) => + io <> sysio + } + io_gpio_pins_temp + } } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 31f3c0ff..9a58960f 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -3,9 +3,8 @@ package chipyard.fpga.vcu118 import chisel3._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp} +import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ @@ -15,6 +14,9 @@ import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ + +import chipyard.fpga.vcu118.bringup._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { @@ -47,18 +49,44 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } /*** SPI ***/ - require(p(PeripherySPIKey).size >= 1) + require(p(PeripherySPIKey).size == 2) + + // 1st SPI goes to the VCU118 SDIO port val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head))) - designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) + val sdio_placed = designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_spi_bb.bundle <> dutMod.io_spi.head } } + // TODO: No access to the TLSPI node... + //val mmcDev = new MMCDevice(sdio_placed.device, 1) + //ResourceBinding { + // Resource(mmcDev, "reg").bind(ResourceAddress(0)) + //} + + // 2nd SPI goes to the ADI port + + val adi = Overlay(SPIOverlayKey, new chipyard.fpga.vcu118.bringup.BringupSPIVCU118ShellPlacer(this, SPIShellInput())) + + val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).last))) + val adi_placed = designParameters(SPIOverlayKey).last.place(SPIDesignInput(p(PeripherySPIKey).last, io_spi_bb_2)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_spi_bb_2.bundle <> dutMod.io_spi.last + } + } + + // TODO: No access to the TLSPI node... + //val adiDev = new chipyard.fpga.vcu118.bringup.ADISPIDevice(adi_placed.device, 1) + //ResourceBinding { + // Resource(adiDev, "reg").bind(ResourceAddress(0)) + //} + /*** I2C ***/ - require(p(PeripheryI2CKey).size >= 1) + require(p(PeripheryI2CKey).size == 1) val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput())) @@ -69,5 +97,24 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S io_i2c_bb.bundle <> dutMod.io_i2c.head } } + + /*** GPIO ***/ + val gpio = Seq.tabulate(p(PeripheryGPIOKey).size)(i => { + val maxGPIOSupport = 32 + val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) + Overlay(GPIOOverlayKey, new chipyard.fpga.vcu118.bringup.BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) + }) + + val io_gpio_bb = p(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (designParameters(GPIOOverlayKey) zip p(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + placer.place(GPIODesignInput(params, io_gpio_bb(i))) + } + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + (io_gpio_bb zip dutMod.io_gpio).map { case (bb_io, dut_io) => + bb_io.bundle <> dut_io + } + } + } } From 5506f776796dc54ca301c910dacfc3bbeb21adb4 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 14 Sep 2020 09:14:57 -0700 Subject: [PATCH 186/457] Add CircleCI check and update Sodor config --- .circleci/config.yml | 20 +++ .circleci/run-tests.sh | 3 + .../src/main/scala/config/SodorConfigs.scala | 120 ++++-------------- scripts/tutorial-patches/build.sbt.patch | 2 +- 4 files changed, 48 insertions(+), 97 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index eac8504a..7b09791c 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,6 +262,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-ariane" + prepare-chipyard-sodor: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor" prepare-icenet: executor: main-env steps: @@ -390,6 +395,12 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" + chipyard-sodor-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor" + timeout: "20m" chipyard-nvdla-run-tests: executor: main-env steps: @@ -511,6 +522,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-sodor: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-icenet: requires: - install-riscv-toolchain @@ -616,6 +632,10 @@ workflows: requires: - prepare-chipyard-ariane + - chipyard-sodor-run-tests: + requires: + - prepare-chipyard-sodor + - chipyard-nvdla-run-tests: requires: - prepare-chipyard-nvdla diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 3e7b0285..c0b932b6 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -91,6 +91,9 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + chipyard-sodor) + run_asm ${mapping[$1]} + ;; chipyard-nvdla) make -C $LOCAL_CHIPYARD_DIR/tests make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 335e7c4e..df386dd9 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -5,115 +5,43 @@ import chisel3._ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor2StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor3StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor3StageSinglePortConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor5StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class SodorUCodeConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 6c1e3007..aa7f0bd4 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -9,7 +9,7 @@ index 5d642c1..56f6fda 100644 - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla) + gemmini, icenet, tracegen, ariane, nvdla, sodor) .settings(commonSettings) @@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) From 10625a3a6cc72a304a8608134b9d4876b9386e6a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 14 Sep 2020 13:27:31 -0700 Subject: [PATCH 187/457] Undo regression in iocells flexibility --- .../src/main/scala/BridgeBinders.scala | 18 ++++++++++++++---- tools/barstools | 2 +- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f42a1adf..8a4d0a69 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -39,10 +39,20 @@ trait Unsupported { require(false, "We do not support this IOCell type") } -class FireSimAnalogIOCell extends RawModule with AnalogIOCell with Unsupported -class FireSimDigitalGPIOCell extends RawModule with DigitalGPIOCell with Unsupported -class FireSimDigitalInIOCell extends RawModule with DigitalInIOCell { io.i := io.pad } -class FireSimDigitalOutIOCell extends RawModule with DigitalOutIOCell { io.pad := io.o } +class FireSimAnalogIOCell extends RawModule with AnalogIOCell with Unsupported { + val io = IO(new AnalogIOCellBundle) +} +class FireSimDigitalGPIOCell extends RawModule with DigitalGPIOCell with Unsupported { + val io = IO(new DigitalGPIOCellBundle) +} +class FireSimDigitalInIOCell extends RawModule with DigitalInIOCell { + val io = IO(new DigitalInIOCellBundle) + io.i := io.pad +} +class FireSimDigitalOutIOCell extends RawModule with DigitalOutIOCell { + val io = IO(new DigitalOutIOCellBundle) + io.pad := io.o +} case class FireSimIOCellParams() extends IOCellTypeParams { def analog() = Module(new FireSimAnalogIOCell) diff --git a/tools/barstools b/tools/barstools index ba681676..31590a79 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit ba681676f338af158023c99b4c802009aa0b601b +Subproject commit 31590a7948db47fd16beed266c4833579acc305b From 0d8e87126cb4070044a3a86da7fe7bdac125a4fc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 14 Sep 2020 19:41:02 -0700 Subject: [PATCH 188/457] Deprecate support for on-chip SerialAdapter --- .../chipyard/src/main/scala/DigitalTop.scala | 1 - .../src/main/scala/HarnessBinders.scala | 50 +++++-------------- .../chipyard/src/main/scala/IOBinders.scala | 9 ---- .../chipyard/src/main/scala/Subsystem.scala | 4 +- .../main/scala/config/AbstractConfig.scala | 6 +-- .../src/main/scala/config/ArianeConfigs.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 10 ++-- .../src/main/scala/BridgeBinders.scala | 5 +- .../src/main/scala/TargetConfigs.scala | 4 +- generators/testchipip | 2 +- tools/barstools | 2 +- 11 files changed, 29 insertions(+), 66 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index f967b8fc..a14a3fbe 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -17,7 +17,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the tilelink-over-serial backing memory - with testchipip.CanHavePeripheryTSISerial // Enables optionally adding the TSI serial-adapter and port with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index c1b57f72..e5cfacfb 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -223,47 +223,23 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithTiedOffTSISerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { - ports.map { p => SerialAdapter.tieoff(Some(p.bits)) } - Nil - } -}) - -class WithSimTSISerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { - ports.map { p => - val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset) - when (ser_success) { th.success := true.B } - } - Nil - } -}) - -class WithSimTLSerial(withHarnessSerialAdapter: Boolean = false) extends OverrideHarnessBinder({ +class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - withClockAndReset(port.clock, th.harnessReset) { - val lRam = LazyModule(new SerialRAM( - p(SerialTLKey).get.width, - p(SerialTLKey).get.memParams.master.size, - p(SerialTLKey).get.memParams.master.base, - managerEdge = system.serdesser.get.managerNode.edges.in(0), - clientEdge = system.serdesser.get.clientNode.edges.out(0) - )) - val ram = Module(lRam.module) - ram.io.ser <> port.bits + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) + SerialAdapter.tieoff(ram.module.io.tsi_ser) + }) + } +}) - require(lRam.serdesser.module.mergedParams == system.serdesser.get.module.mergedParams, - "Mismatch between chip-side diplomatic params and testram diplomatic params") - if (withHarnessSerialAdapter) { - val success = SerialAdapter.connectSimSerial(Some(ram.io.tsi_ser), port.clock, th.harnessReset.asBool) - when (success) { th.success := true.B } - } else { - SerialAdapter.tieoff(Some(ram.io.tsi_ser)) - } - } +class WithSimSerial extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + ports.map({ port => + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) + val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool) + when (success) { th.success := true.B } }) } }) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 03138cc1..73a8acfd 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -250,15 +250,6 @@ class WithDebugIOCells extends OverrideIOBinder({ } }) -class WithSerialTSIIOCells extends OverrideIOBinder({ - (system: CanHavePeripheryTSISerial) => system.serial_tsi.map({ s => - val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tsi"), sys.p(IOCellKey)) - port.suggestName("serial_tsi") - (Seq(port), cells) - }).getOrElse((Nil, Nil)) -}) - class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s => val sys = system.asInstanceOf[BaseSubsystem] diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index c3ca93b7..172be692 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile} -import testchipip.{DromajoHelper, CanHavePeripheryTSISerial, SerialTSIKey} +import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripheryTSISerial if p(SerialTSIKey).nonEmpty => true + case _: CanHavePeripheryTKSerial if p(SerialTLKey).nonEmpty => true case _: HasPeripheryDebug if p(ExportDebug).dmi => true case _ => false }) { diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index aed55d02..5b356c74 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -14,8 +14,8 @@ class AbstractConfig extends Config( // The HarnessBinders control generation of hardware in the TestHarness new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled + new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled - new chipyard.harness.WithSimTSISerial ++ // add SimSerial adapter for HTIF, if serial port is present new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled @@ -29,7 +29,6 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ new chipyard.iobinders.WithNICIOPunchthrough ++ - new chipyard.iobinders.WithSerialTSIIOCells ++ new chipyard.iobinders.WithSerialTLIOCells ++ new chipyard.iobinders.WithDebugIOCells ++ new chipyard.iobinders.WithUARTIOCells ++ @@ -39,8 +38,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithExtInterruptIOCells ++ - - new testchipip.WithSerialTSI ++ // use testchipip serial offchip link + new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index b7c347dc..6e75ac54 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -13,7 +13,7 @@ class ArianeConfig extends Config( new chipyard.config.AbstractConfig) class dmiArianeConfig extends Config( - new chipyard.harness.WithTiedOffTSISerial ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 9f2a97de..42b5f3b0 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config( // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.harness.WithTiedOffTSISerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -182,10 +182,8 @@ class DividedClockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class TLSerialRocketConfig extends Config( - new chipyard.harness.WithSimTLSerial(withHarnessSerialAdapter = true) ++ // add external TL backing memory, and external serial adapter - new testchipip.WithDefaultSerialTL ++ // support tilelink-over-serial - new testchipip.WithNoSerialTSI ++ // remove internal serial adapter +class LBWIFMemoryRocketConfig extends Config( + new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 98f672a9..4943e130 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -66,10 +66,11 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset) withClockAndReset(p.clock, th.harnessReset) { - SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system)) + SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system)) } } Nil diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 7df0bf61..678afccf 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config( // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible // for signalling simulation termination under simulation success. This fragment can // be removed if you supply an auxiliary bridge that signals simulation termination - new testchipip.WithSerialTSI ++ + new testchipip.WithDefaultSerialTL ++ // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ // Required*: Scale default baud rate with periphery bus frequency @@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config( new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ - new testchipip.WithSerialTSI ++ + new testchipip.WithDefaultSerialTL ++ new testchipip.WithBlockDevice ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ diff --git a/generators/testchipip b/generators/testchipip index 6f815737..e845cb3f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6f8157375451fbb32e9dae291f2c65878a2b1dcd +Subproject commit e845cb3f50bb141fec7e8291a40d0b46d5ef5c12 diff --git a/tools/barstools b/tools/barstools index 31590a79..847f72ec 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 31590a7948db47fd16beed266c4833579acc305b +Subproject commit 847f72eca0fa3207ab7140c07e980ac9f8cf1251 From 642441e0a27171665ff3a2484b599d94e244f497 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 14 Sep 2020 23:54:52 -0700 Subject: [PATCH 189/457] Replaced memory and fixed 3-stage single port arbiter --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 70033f04..43985218 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 70033f041a5e46fdc2c7c473fb8fa509bddc2e2d +Subproject commit 43985218b8c91c9206018177d81e37e27267dbf6 From f1b40d51afdba1e1d7c9bd95742aec2e85adef3d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 15 Sep 2020 12:58:58 -0700 Subject: [PATCH 190/457] Connected clocks | Exposed Master TL port --- fpga/src/main/scala/vcu118/Configs.scala | 29 ++++-- .../main/scala/vcu118/CustomOverlays.scala | 25 ++--- fpga/src/main/scala/vcu118/Platform.scala | 16 +++- fpga/src/main/scala/vcu118/TestHarness.scala | 94 ++++++++++++++----- .../chipyard/src/main/scala/DigitalTop.scala | 40 ++++++++ .../chipyard/src/main/scala/System.scala | 1 - 6 files changed, 159 insertions(+), 46 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 7cc106d5..ab087afa 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ @@ -52,20 +52,35 @@ class WithBringupPeripherals extends Config((site, here, up) => { } }) +class SmallModifications extends Config((site, here, up) => { + case SystemBusKey => up(SystemBusKey).copy( + errorDevice = Some(DevNullParams( + Seq(AddressSet(0x3000, 0xfff)), + maxAtomic=site(XLen)/8, + maxTransfer=128, + region = RegionType.TRACKED))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = + Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt), + errorDevice = None) + case DTSTimebase => BigInt(1000000) + case JtagDTMKey => new JtagDTMConfig( + idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai). + idcodePartNum = 0x000, // Decided to simplify. + idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses. + debugIdleCycles = 5) // Reasonable guess for synchronization +}) + + class FakeBringupConfig extends Config( new WithBringupPeripherals ++ new WithChipyardBuildTop ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index ccb61f0e..2c438a34 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -12,10 +12,11 @@ import sifive.fpgashells.shell.xilinx._ import sifive.blocks.devices.gpio._ + import chipyard.fpga.vcu118.{FMCPMap} /* Connect the I2C to certain FMC pins */ -class BringupI2CVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) +class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) extends I2CXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { @@ -32,14 +33,14 @@ class BringupI2CVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val de } } } -class BringupI2CVCU118ShellPlacer(val shell: VCU118Shell, val shellInput: I2CShellInput)(implicit val valName: ValName) - extends I2CShellPlacer[VCU118Shell] +class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName) + extends I2CShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } /* Connect the UART to certain FMC pins */ -class BringupUARTVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) +class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) { shell { InModuleBody { @@ -61,13 +62,13 @@ class BringupUARTVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val d } } } -class BringupUARTVCU118ShellPlacer(shell: VCU118Shell, val shellInput: UARTShellInput)(implicit val valName: ValName) - extends UARTShellPlacer[VCU118Shell] { +class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName) + extends UARTShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } /* Connect SPI to ADI device */ -class BringupSPIVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) +class BringupSPIVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) extends SDIOXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { @@ -89,8 +90,8 @@ class BringupSPIVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val de } } } -class BringupSPIVCU118ShellPlacer(shell: VCU118Shell, val shellInput: SPIShellInput)(implicit val valName: ValName) - extends SPIShellPlacer[VCU118Shell] { +class BringupSPIVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: SPIShellInput)(implicit val valName: ValName) + extends SPIShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } @@ -123,7 +124,7 @@ abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GP } } } -class BringupGPIOVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) +class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { @@ -143,8 +144,8 @@ class BringupGPIOVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val d } } } -class BringupGPIOVCU118ShellPlacer(shell: VCU118Shell, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) - extends GPIOShellPlacer[VCU118Shell] { +class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) + extends GPIOShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index 8f9a1ae8..bdacdf42 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -1,11 +1,12 @@ package chipyard.fpga.vcu118 import chisel3._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} -import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyScope, InModuleBody, BundleBridgeSource, ValName} import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} import chipyard.{BuildSystem} @@ -19,9 +20,10 @@ trait HasVCU118PlatformIO { val io_spi: Seq[SPIPortIO] val io_i2c: Seq[I2CPort] val io_gpio: Seq[GPIOPortIO] + val io_tl_mem: HeterogeneousBag[TLBundle] } -class VCU118Platform(override implicit val p: Parameters) extends LazyModule { +class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope { val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") @@ -62,4 +64,10 @@ class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleIm } io_gpio_pins_temp } + + val io_tl_mem = _outer.lazySystem match { case sys: chipyard.CanHaveMasterTLMemPort => + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](sys.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> sys.mem_tl + io_tl_mem_pins_temp + } } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 9a58960f..d4e299a5 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -4,7 +4,8 @@ import chisel3._ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ @@ -16,20 +17,55 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.fpga.vcu118.bringup._ +import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} -class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { +case object DUTFrequencyKey extends Field[Double](100.0) +class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell { + + def dp = designParameters + + /*** Connect/Generate clocks ***/ + + // connect to the PLL that will generate multiple clocks + val harnessSysPLL = dp(PLLFactoryKey)() + sys_clock.get() match { + case Some(x : SysClockVCU118PlacedOverlay) => { + harnessSysPLL := x.node + } + } + + // create and connect to the dutClock + val dutClock = ClockSinkNode(freqMHz = dp(DUTFrequencyKey)) + val dutWrangler = LazyModule(new ResetWrangler) + val dutGroup = ClockGroup() + dutClock := dutWrangler.node := dutGroup := harnessSysPLL + + InModuleBody { + topDesign.module match { case td: LazyModuleImp => { + td.clock := dutClock.in.head._1.clock + td.reset := dutClock.in.head._1.reset + } + } + } + + // connect ref clock to dummy sink node + ref_clock.get() match { + case Some(x : RefClockVCU118PlacedOverlay) => { + val sink = ClockSinkNode(Seq(ClockSinkParameters())) + sink := x.node + } + } /*** UART ***/ - require(p(PeripheryUARTKey).size == 2) + require(dp(PeripheryUARTKey).size == 2) // 1st UART goes to the VCU118 dedicated UART // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).head))) - designParameters(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_uart_bb.bundle <> dutMod.io_uart.head @@ -38,10 +74,10 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S // 2nd UART goes to the FMC UART - val uart_fmc = Overlay(UARTOverlayKey, new chipyard.fpga.vcu118.bringup.BringupUARTVCU118ShellPlacer(this, UARTShellInput())) + val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).last))) - designParameters(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) + dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_uart_bb_2.bundle <> dutMod.io_uart.last @@ -49,12 +85,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } /*** SPI ***/ - require(p(PeripherySPIKey).size == 2) + require(dp(PeripherySPIKey).size == 2) // 1st SPI goes to the VCU118 SDIO port - val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head))) - val sdio_placed = designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) + val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_spi_bb.bundle <> dutMod.io_spi.head @@ -69,10 +105,10 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S // 2nd SPI goes to the ADI port - val adi = Overlay(SPIOverlayKey, new chipyard.fpga.vcu118.bringup.BringupSPIVCU118ShellPlacer(this, SPIShellInput())) + val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).last))) - val adi_placed = designParameters(SPIOverlayKey).last.place(SPIDesignInput(p(PeripherySPIKey).last, io_spi_bb_2)) + val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) + val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_spi_bb_2.bundle <> dutMod.io_spi.last @@ -86,12 +122,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S //} /*** I2C ***/ - require(p(PeripheryI2CKey).size == 1) + require(dp(PeripheryI2CKey).size == 1) - val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput())) + val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - designParameters(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) + dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_i2c_bb.bundle <> dutMod.io_i2c.head @@ -99,14 +135,14 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } /*** GPIO ***/ - val gpio = Seq.tabulate(p(PeripheryGPIOKey).size)(i => { + val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { val maxGPIOSupport = 32 val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new chipyard.fpga.vcu118.bringup.BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) + Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) }) - val io_gpio_bb = p(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (designParameters(GPIOOverlayKey) zip p(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => placer.place(GPIODesignInput(params, io_gpio_bb(i))) } InModuleBody { @@ -116,5 +152,19 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } } } + + /*** Experimental DDR ***/ + + //val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + + //topDesign match { case lazyDut: VCU118Platform => + // lazyDut.lazySystem match { case lazyDutWBus: BaseSubsystem => + // lazyDutWBus { + // InModuleBody { + // ddrPlaced.overlayOutput.ddr := lazyDutWBus.mbus.toDRAMController(Some("xilinxvcu118mig"))() + // } + // } + // } + //} } diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 9e40cfab..dedcfbf8 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -29,6 +29,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA + with CanHaveMasterTLMemPort { override lazy val module = new DigitalTopModule(this) } @@ -47,3 +48,42 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +/** Adds a TileLink port to the system intended to master an MMIO device bus */ +trait CanHaveMasterTLMemPort { this: BaseSubsystem => + private val memPortParamsOpt = p(ExtMem) + private val portName = "tl_mem" + private val device = new MemoryDevice + private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsGet = TransferSizes(1, mbus.blockBytes), + supportsPutFull = TransferSizes(1, mbus.blockBytes), + supportsPutPartial = TransferSizes(1, mbus.blockBytes))), + beatBytes = memPortParams.beatBytes) + } + }).toList.flatten) + + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) + } + + val mem_tl = InModuleBody { memTLNode.makeIOs() } +} diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index bd20ddc7..f8906e04 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -23,7 +23,6 @@ import freechips.rocketchip.util.{DontTouch} */ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts - with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port { From aa8b7c15ecfed723d8f01748ebb3af6e64516cde Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 14 Sep 2020 23:04:58 -0700 Subject: [PATCH 191/457] Reduce CI redundancy by grouping builds --- .circleci/config.yml | 386 ++++++++++++-------------------------- .circleci/defaults.sh | 9 + .circleci/do-rtl-build.sh | 19 +- 3 files changed, 142 insertions(+), 272 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index eac8504a..6ed04488 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -99,11 +99,10 @@ commands: tools-version: type: string default: "riscv-tools" + group-key: + type: string project-key: type: string - extra-cache-restore: - type: string - default: "" run-script: type: string default: "run-tests.sh" @@ -115,13 +114,7 @@ commands: tools-version: "<< parameters.tools-version >>" - restore_cache: keys: - - << parameters.project-key >>-{{ .Branch }}-{{ .Revision }} - - when: - condition: << parameters.extra-cache-restore >> - steps: - - restore_cache: - keys: - - << parameters.extra-cache-restore >>-{{ .Branch }}-{{ .Revision }} + - << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} - run: name: Run << parameters.project-key >> subproject tests command: .circleci/<< parameters.run-script >> << parameters.project-key >> @@ -194,177 +187,147 @@ jobs: key: extra-tests-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project/tests" - prepare-chipyard-rocket: + + prepare-chipyard-cores: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-rocket" - prepare-chipyard-dmirocket: + project-key: "group-cores" + prepare-chipyard-peripherals: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-dmirocket" - prepare-chipyard-sha3: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-sha3" - prepare-chipyard-streaming-fir: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-streaming-fir" - prepare-chipyard-streaming-passthrough: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-streaming-passthrough" - prepare-chipyard-hetero: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-hetero" - timeout: "240m" - prepare-chipyard-boom: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-boom" - prepare-chipyard-blkdev: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-blkdev" - prepare-chipyard-hwacha: + project-key: "group-peripherals" + prepare-chipyard-accels: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "chipyard-hwacha" - prepare-chipyard-gemmini: + project-key: "group-accels" + prepare-chipyard-tracegen: executor: main-env steps: - prepare-rtl: - tools-version: "esp-tools" - project-key: "chipyard-gemmini" - prepare-tracegen: + project-key: "group-tracegen" + prepare-chipyard-other: executor: main-env steps: - prepare-rtl: - project-key: "tracegen" - prepare-tracegen-boom: - executor: main-env - steps: - - prepare-rtl: - project-key: "tracegen-boom" - prepare-chipyard-ariane: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-ariane" - prepare-icenet: - executor: main-env - steps: - - prepare-rtl: - project-key: "icenet" - prepare-testchipip: - executor: main-env - steps: - - prepare-rtl: - project-key: "testchipip" - prepare-chipyard-nvdla: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-nvdla" - prepare-chipyard-spiflashwrite: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-spiflashwrite" - prepare-chipyard-spiflashread: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-spiflashread" - prepare-chipyard-mmios: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-mmios" + project-key: "group-other" + chipyard-rocket-run-tests: executor: main-env steps: - run-tests: + group-key: "group-cores" project-key: "chipyard-rocket" - chipyard-dmirocket-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-dmirocket" - chipyard-sha3-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-sha3" - chipyard-streaming-fir-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-streaming-fir" - chipyard-streaming-passthrough-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-streaming-passthrough" chipyard-hetero-run-tests: executor: main-env steps: - run-tests: + group-key: "group-cores" project-key: "chipyard-hetero" timeout: "15m" chipyard-boom-run-tests: executor: main-env steps: - run-tests: + group-key: "group-cores" project-key: "chipyard-boom" + chipyard-ariane-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-cores" + project-key: "chipyard-ariane" + timeout: "30m" + chipyard-dmirocket-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-peripherals" + project-key: "chipyard-dmirocket" + chipyard-spiflashwrite-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-peripherals" + project-key: "chipyard-spiflashwrite" + chipyard-spiflashread-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-peripherals" + project-key: "chipyard-spiflashread" + chipyard-sha3-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-accels" + project-key: "chipyard-sha3" + chipyard-streaming-fir-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-accels" + project-key: "chipyard-streaming-fir" + chipyard-streaming-passthrough-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-accels" + project-key: "chipyard-streaming-passthrough" chipyard-hwacha-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" + group-key: "group-accels" project-key: "chipyard-hwacha" chipyard-gemmini-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" + group-key: "group-accels" project-key: "chipyard-gemmini" - chipyard-spiflashwrite-run-tests: + chipyard-nvdla-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-spiflashwrite" - chipyard-spiflashread-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-spiflashread" + group-key: "group-accels" + project-key: "chipyard-nvdla" tracegen-run-tests: executor: main-env steps: - run-tests: + group-key: "group-tracegen" project-key: "tracegen" tracegen-boom-run-tests: executor: main-env steps: - run-tests: + group-key: "group-tracegen" project-key: "tracegen-boom" + icenet-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-other" + project-key: "icenet" + timeout: "30m" + testchipip-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-other" + project-key: "testchipip" + timeout: "30m" firesim-run-tests: executor: main-env steps: - run-tests: - extra-cache-restore: "extra-tests" + group-key: "extra-tests" project-key: "firesim" run-script: "run-firesim-scala-tests.sh" timeout: "20m" @@ -372,7 +335,7 @@ jobs: executor: main-env steps: - run-tests: - extra-cache-restore: "extra-tests" + group-key: "extra-tests" project-key: "fireboom" run-script: "run-firesim-scala-tests.sh" timeout: "45m" @@ -380,33 +343,10 @@ jobs: executor: main-env steps: - run-tests: - extra-cache-restore: "extra-tests" + group-key: "extra-tests" project-key: "firesim-multiclock" run-script: "run-firesim-scala-tests.sh" timeout: "20m" - chipyard-ariane-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-ariane" - timeout: "30m" - chipyard-nvdla-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-nvdla" - icenet-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "icenet" - timeout: "30m" - testchipip-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "testchipip" - timeout: "30m" # Order and dependencies of jobs to run workflows: @@ -446,154 +386,83 @@ workflows: - install-riscv-toolchain # Prepare the verilator builds - - prepare-chipyard-rocket: + - prepare-chipyard-cores: requires: - install-riscv-toolchain - install-verilator - - - prepare-chipyard-dmirocket: + - prepare-chipyard-peripherals: requires: - install-riscv-toolchain - install-verilator - - - prepare-chipyard-sha3: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-streaming-fir: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-streaming-passthrough: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-hetero: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-boom: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-blkdev: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-hwacha: + - prepare-chipyard-accels: requires: - install-esp-toolchain - install-verilator - - - prepare-chipyard-gemmini: - requires: - - install-esp-toolchain - - install-verilator - - - prepare-tracegen: + - prepare-chipyard-tracegen: requires: - install-riscv-toolchain - install-verilator - - - prepare-tracegen-boom: + - prepare-chipyard-other: requires: - install-riscv-toolchain - install-verilator - - prepare-chipyard-ariane: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-icenet: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-testchipip: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-nvdla: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-spiflashwrite: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-spiflashread: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-mmios: - requires: - - install-riscv-toolchain - - # Run the respective tests - # Run the example tests - chipyard-rocket-run-tests: requires: - - prepare-chipyard-rocket + - prepare-chipyard-cores + - chipyard-hetero-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-boom-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-ariane-run-tests: + requires: + - prepare-chipyard-cores - chipyard-dmirocket-run-tests: requires: - - prepare-chipyard-dmirocket + - prepare-chipyard-peripherals + - chipyard-spiflashwrite-run-tests: + requires: + - prepare-chipyard-peripherals + - chipyard-spiflashread-run-tests: + requires: + - prepare-chipyard-peripherals - chipyard-sha3-run-tests: requires: - - prepare-chipyard-sha3 - + - prepare-chipyard-accels - chipyard-streaming-fir-run-tests: requires: - - prepare-chipyard-streaming-fir - + - prepare-chipyard-accels - chipyard-streaming-passthrough-run-tests: requires: - - prepare-chipyard-streaming-passthrough - - - chipyard-hetero-run-tests: - requires: - - prepare-chipyard-hetero - - - chipyard-boom-run-tests: - requires: - - prepare-chipyard-boom - + - prepare-chipyard-accels - chipyard-hwacha-run-tests: requires: - - prepare-chipyard-hwacha - + - prepare-chipyard-accels - chipyard-gemmini-run-tests: requires: - - prepare-chipyard-gemmini + - prepare-chipyard-accels + - chipyard-nvdla-run-tests: + requires: + - prepare-chipyard-accels - tracegen-run-tests: requires: - - prepare-tracegen - + - prepare-chipyard-tracegen - tracegen-boom-run-tests: requires: - - prepare-tracegen-boom + - prepare-chipyard-tracegen - - chipyard-spiflashwrite-run-tests: + - icenet-run-tests: requires: - - prepare-chipyard-spiflashwrite - - - chipyard-spiflashread-run-tests: + - prepare-chipyard-other + - testchipip-run-tests: requires: - - prepare-chipyard-spiflashread + - prepare-chipyard-other # Run the firesim tests - firesim-run-tests: @@ -612,17 +481,4 @@ workflows: - install-verilator - build-extra-tests - - chipyard-ariane-run-tests: - requires: - - prepare-chipyard-ariane - - chipyard-nvdla-run-tests: - requires: - - prepare-chipyard-nvdla - - icenet-run-tests: - requires: - - prepare-icenet - - - testchipip-run-tests: - requires: - - prepare-testchipip diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 703737cd..6f74c26d 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -45,6 +45,14 @@ LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim +# key value store to get the build groups +declare -A grouping +grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios" +grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" +grouping["group-tracegen"]="tracegen tracegen-boom" +grouping["group-other"]="icenet testchipip" + # key value store to get the build strings declare -A mapping mapping["chipyard-rocket"]="" @@ -64,6 +72,7 @@ mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" + mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 3973026f..9093b29e 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -31,7 +31,7 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -if [ $1 = "chipyard-gemmini" ]; then +if [ $1 = "group-accels" ]; then export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH @@ -40,9 +40,7 @@ if [ $1 = "chipyard-gemmini" ]; then git submodule update --init --recursive gemmini-rocc-tests cd gemmini-rocc-tests ./build.sh -fi -if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib run "mkdir -p $REMOTE_ESP_DIR" @@ -58,12 +56,19 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -C $REMOTE_SIM_DIR clean; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" -run "rm -rf $REMOTE_CHIPYARD_DIR/project" + make -C $REMOTE_SIM_DIR clean;" -# copy back the final build +read -a keys <<< ${grouping[$1]} +for key in "${keys[@]}" +do + run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" +done run "rm -rf $REMOTE_CHIPYARD_DIR/project" From 36ccb12560ef24eb492b93baf5c2da996badf1b8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 16 Sep 2020 10:29:03 -0700 Subject: [PATCH 192/457] Bump testchipip --- generators/chipyard/src/main/scala/Subsystem.scala | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 172be692..5dd6ac18 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -30,7 +30,7 @@ import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripheryTKSerial if p(SerialTLKey).nonEmpty => true + case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true case _: HasPeripheryDebug if p(ExportDebug).dmi => true case _ => false }) { diff --git a/generators/testchipip b/generators/testchipip index e845cb3f..57cac41f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e845cb3f50bb141fec7e8291a40d0b46d5ef5c12 +Subproject commit 57cac41f71653ca2a04d936f36ee8c78ec9919fd From 269af01a70d6fe6411dcc6ba5ef7f5aed5fa4e1d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 16 Sep 2020 12:06:36 -0700 Subject: [PATCH 193/457] Bump testchipip --- .circleci/defaults.sh | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 2a744e89..6053b367 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -49,7 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" -mapping["chipyard-tlserial"]=" CONFIG=TLSerialRocketConfig" +mapping["chipyard-tlserial"]=" CONFIG=LBWIFMemoryRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" diff --git a/generators/testchipip b/generators/testchipip index 57cac41f..f2efec8e 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 57cac41f71653ca2a04d936f36ee8c78ec9919fd +Subproject commit f2efec8ee7bd6988b94a6fa3615ae7f864714004 From 687430898116d98ff625fa9258ae89473dd26135 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 16 Sep 2020 15:27:43 -0700 Subject: [PATCH 194/457] Address review comments --- .circleci/config.yml | 18 +++++++++--------- .circleci/do-rtl-build.sh | 4 ---- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 6ed04488..48ed4883 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -73,7 +73,7 @@ commands: tools-version: type: string default: "riscv-tools" - project-key: + group-key: type: string timeout: type: string @@ -85,11 +85,11 @@ commands: - setup-tools: tools-version: "<< parameters.tools-version >>" - run: - name: Building << parameters.project-key >> subproject using Verilator - command: .circleci/<< parameters.build-script >> << parameters.project-key >> + name: Building << parameters.group-key >> subproject using Verilator + command: .circleci/<< parameters.build-script >> << parameters.group-key >> no_output_timeout: << parameters.timeout >> - save_cache: - key: << parameters.project-key >>-{{ .Branch }}-{{ .Revision }} + key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" @@ -192,28 +192,28 @@ jobs: executor: main-env steps: - prepare-rtl: - project-key: "group-cores" + group-key: "group-cores" prepare-chipyard-peripherals: executor: main-env steps: - prepare-rtl: - project-key: "group-peripherals" + group-key: "group-peripherals" prepare-chipyard-accels: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "group-accels" + group-key: "group-accels" prepare-chipyard-tracegen: executor: main-env steps: - prepare-rtl: - project-key: "group-tracegen" + group-key: "group-tracegen" prepare-chipyard-other: executor: main-env steps: - prepare-rtl: - project-key: "group-other" + group-key: "group-other" chipyard-rocket-run-tests: executor: main-env diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 9093b29e..784dbc04 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -52,10 +52,6 @@ fi # enter the verilator directory and build the specific config on remote server run "export RISCV=\"$TOOLS_DIR\"; \ - export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ - export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ make -C $REMOTE_SIM_DIR clean;" read -a keys <<< ${grouping[$1]} From 895bacea9884248493c0e44d3a4d1ad6b91e786d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 24 Aug 2020 11:01:29 -0700 Subject: [PATCH 195/457] WIP - Simple divider-only PLL generation flow --- .../src/main/resources/vsrc/ClockDividerN.sv | 40 +++++++++++ .../chipyard/src/main/scala/Clocks.scala | 36 ++++++++++ .../src/main/scala/ConfigFragments.scala | 27 +++++++- .../src/main/scala/GenericAttachParams.scala | 38 +++++++++++ .../main/scala/clocking/ClockDividerN.scala | 23 +++++++ .../scala/clocking/ClockGroupDealiaser.scala | 51 ++++++++++++++ .../scala/clocking/ClockNodeInjectors.scala | 29 ++++++++ .../main/scala/clocking/IdealizedPLL.scala | 68 +++++++++++++++++++ .../src/main/scala/config/RocketConfigs.scala | 9 ++- 9 files changed, 319 insertions(+), 2 deletions(-) create mode 100644 generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv create mode 100644 generators/chipyard/src/main/scala/GenericAttachParams.scala create mode 100644 generators/chipyard/src/main/scala/clocking/ClockDividerN.scala create mode 100644 generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala create mode 100644 generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala create mode 100644 generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala diff --git a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv new file mode 100644 index 00000000..33f7a05b --- /dev/null +++ b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv @@ -0,0 +1,40 @@ +// See LICENSE for license details. + +/** + * An unsynthesizable divide-by-N clock divider. + * Duty cycle is 100 * (ceil(DIV / 2)) / 2. + */ + +module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in); + + localparam DIV_COUNTER_WIDTH = $clog2(DIV); + localparam LOW_CYCLES = DIV / 2; + + generate + if (DIV == 1) begin + // This needs to be procedural because of the assignment on declaration + always @(clk_in) begin + clk_out = clk_in; + end + end else begin + reg [DIV_COUNTER_WIDTH - 1: 0] count = '0; + // The blocking assignment to clock out is used to conform what was done + // in RC's clock dividers. + // It should have the effect of preventing registers in the divided clock + // domain latching register updates launched by the fast clock-domain edge + // that occurs at the same simulated time (as the divided clock edge). + always @(posedge clk_in) begin + if (count == (DIV - 1)) begin + clk_out = 1'b0; + count <= '0; + end + else begin + if (count == (LOW_CYCLES - 1)) begin + clk_out = 1'b1; + end + count <= count + 1'b1; + end + end + end + endgenerate +endmodule // ClockDividerN diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index a1ff1b0f..01d6c828 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -12,6 +12,8 @@ import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} import barstools.iocell.chisel._ +import chipyard.clocking.{IdealizedPLL, ClockGroupDealiaser} + /** * Chipyard provides three baseline, top-level reset schemes, set using the * [[GlobalResetSchemeKey]] in a Parameters instance. These are: @@ -173,6 +175,40 @@ object ClockingSchemeGenerators { Nil }) } + } + val idealizedPLL: ChipTop => Unit = { chiptop => + implicit val p = chiptop.p + + // Requires existence of undriven asyncClockGroups in subsystem + val systemAsyncClockGroup = chiptop.lSystem match { + case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => + l.asyncClockGroupsNode + } + + val aggregator = ClockGroupAggregator() + chiptop.implicitClockSinkNode := ClockGroup() := aggregator + systemAsyncClockGroup := aggregator + + val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + aggregator := ClockGroupDealiaser() := IdealizedPLL() := referenceClockSource + + InModuleBody { + + val clock_wire = Wire(Input(Clock())) + val reset_wire = GenerateReset(chiptop, clock_wire) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) + chiptop.iocells ++= clockIOCell + clock_io.suggestName("clock") + + referenceClockSource.out.unzip._1.map { o => + o.clock := clock_wire + o.reset := reset_wire + } + + chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + clock_io := th.harnessClock + Nil }) + } } } diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index cfa465e7..9fb3adb2 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -28,7 +28,11 @@ import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingSchemeKey, TestSuitesKey, TestSuiteHelper} - +// Imports for multiclock sketch +import boom.common.{BoomTile, BoomTileParams} +import ariane.{ArianeTile, ArianeTileParams} +import chipyard.{GenericallyAttachableTile, GenericCrossingParams} +import chipyard.clocking.{ClockNodeInjectionUtils } // ----------------------- // Common Config Fragments // ----------------------- @@ -170,3 +174,24 @@ class WithDMIDTM extends Config((site, here, up) => { class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None }) + + +// Multiclock sketch +class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => + val genericAttachParams = up(TilesLocated(InSubsystem), site) map { + case b: BoomTileAttachParams => GenericallyAttachableTile[BoomTile]( + b.tileParams, GenericCrossingParams(b.crossingParams), b.lookup) + case r: RocketTileAttachParams => GenericallyAttachableTile[RocketTile]( + r.tileParams, GenericCrossingParams(r.crossingParams), r.lookup) + case a: ArianeTileAttachParams => GenericallyAttachableTile[ArianeTile]( + a.tileParams, GenericCrossingParams(a.crossingParams), a.lookup) + case g: GenericallyAttachableTile[_] => g + } + genericAttachParams.map(p => p.copy(crossingParams = p.crossingParams.copy( + injectClockNodeFunc = ClockNodeInjectionUtils.forceTakeFrequency(fMHz)))) +}) + +class WithIdealizedPLL extends Config((site, here, up) => { + case ChipyardClockKey => ClockDrivers.idealizedPLL +}) diff --git a/generators/chipyard/src/main/scala/GenericAttachParams.scala b/generators/chipyard/src/main/scala/GenericAttachParams.scala new file mode 100644 index 00000000..f90598af --- /dev/null +++ b/generators/chipyard/src/main/scala/GenericAttachParams.scala @@ -0,0 +1,38 @@ + +package chipyard + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tile.{LookupByHartIdImpl, TileParams, InstantiableTileParams, BaseTile} + +import chipyard.clocking.ClockNodeInjectionUtils._ + +case class GenericCrossingParams( + crossingType: ClockCrossingType = SynchronousCrossing(), + master: TilePortParamsLike = TileMasterPortParams(), + slave: TilePortParamsLike = TileSlavePortParams(), + mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS, + injectClockNodeFunc: InjectClockNodeFunc = injectIdentityClockNode, + forceSeparateClockReset: Boolean = false) extends TileCrossingParamsLike { + + def injectClockNode(a: Attachable)(implicit p: Parameters) = injectClockNodeFunc(a, p) +} + +object GenericCrossingParams { + def apply(params: TileCrossingParamsLike): GenericCrossingParams = GenericCrossingParams( + params.crossingType, + params.master, + params.slave, + params.mmioBaseAddressPrefixWhere, + (a: Attachable, p: Parameters) => params.injectClockNode(a)(p), + params.forceSeparateClockReset) +} + +case class GenericallyAttachableTile[TT <: BaseTile]( + tileParams: InstantiableTileParams[TT], + crossingParams: GenericCrossingParams, + lookup: LookupByHartIdImpl) extends CanAttachTile { + type TileType = TT +} + diff --git a/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala b/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala new file mode 100644 index 00000000..c9513b88 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala @@ -0,0 +1,23 @@ +// See LICENSE.SiFive for license details. + +package chipyard.clocking + +import chisel3._ +import chisel3.util._ + +class ClockDividerN(div: Int) extends BlackBox(Map("DIV" -> div)) with HasBlackBoxResource { + require(div > 0); + val io = IO(new Bundle { + val clk_out = Output(Clock()) + val clk_in = Input(Clock()) + }) + addResource("/vsrc/ClockDividerN.sv") +} + +object ClockDivideByN { + def apply(clockIn: Clock, div: Int): Clock = { + val clockDivider = Module(new ClockDividerN(div)) + clockDivider.io.clk_in := clockIn + clockDivider.io.clk_out + } +} diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala new file mode 100644 index 00000000..3ffea3c0 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala @@ -0,0 +1,51 @@ +package chipyard.clocking + +import chisel3._ + +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.prci._ + +/** + * Somewhat hacky. Since not all clocks in a clock group specify a taken frequency + * current, this LazyModule attempts to dealias them, by finding a specified + * clock whose name has the longest matching prefix. + * + * Perhaps another, simpler solution would be to pass a default. + * + */ + +case class ClockGroupDealiaserNode()(implicit valName: ValName) + extends NexusNode(ClockGroupImp)( + dFn = { _ => ClockGroupSourceParameters() }, + uFn = { u => + require(u.size == 1) + val takenClocks = u.head.members.filter(_.take.nonEmpty) + require(takenClocks.nonEmpty, + "At least one sink clock in clock group must specify its take parameter") + u.head.copy(members = takenClocks) + }) + +class ClockGroupDealiaser(name: String)(implicit p: Parameters) extends LazyModule { + val node = ClockGroupDealiaserNode() + + lazy val module = new LazyRawModuleImp(this) { + require(node.out.size == 1, "Must use a ClockGroupAggregator") + val (outClocks, e @ ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head + val (inClocks, ClockGroupEdgeParameters(_, inSinkParams, _, _)) = node.in.head + val inMap = inClocks.member.data.zip(inSinkParams.members).map({ case (b, p) => p.name -> b}).toMap + + for (((outBName, outB), outName) <- outClocks.member.elements.zip(outSinkParams.members.map(_.name))) { + val inClock = inMap.getOrElse(outName, throw new Exception(""" + | No clock in input group with name: Option matching ${outName}. At least one clock + | with the same must specify a frequency in its take parameter.""".stripMargin)) + // This will be removed. + dontTouch(outB) + outB := inClock + } + } +} + +object ClockGroupDealiaser { + def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupDealiaser(valName.name)).node +} diff --git a/generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala b/generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala new file mode 100644 index 00000000..981ed327 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala @@ -0,0 +1,29 @@ + +package chipyard.clocking + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.prci.{ClockNode, ClockTempNode, ClockAdapterNode, ClockParameters} +/** + * An adapter node hack c that just throws out the existing sink node + * clock parameters in favor of the provided ones. + */ +class ForceTakeClock(clockParams: Option[ClockParameters])(implicit p: Parameters, v: ValName) extends LazyModule { + val node = ClockAdapterNode(sinkFn = { s => s.copy(take = clockParams) }) + lazy val module = new LazyRawModuleImp(this) { + (node.out zip node.in) map { case ((o, _), (i, _)) => o := i } + } +} + +object ForceTakeClock { + def apply(clockParams: Option[ClockParameters])(implicit p: Parameters, v: ValName): ClockAdapterNode = + LazyModule(new ForceTakeClock(clockParams)).node +} + +object ClockNodeInjectionUtils { + type InjectClockNodeFunc = (Attachable, Parameters) => ClockNode + val injectIdentityClockNode: InjectClockNodeFunc = (a: Attachable, p: Parameters) => ClockTempNode() + def forceTakeFrequency(freqMHz: Double): InjectClockNodeFunc = + (a: Attachable, p: Parameters) => ForceTakeClock(Some(ClockParameters(freqMHz)))(p, ValName("ForcedTakeClock")) +} diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala new file mode 100644 index 00000000..3de99e8e --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala @@ -0,0 +1,68 @@ +package chipyard.clocking + +import chisel3._ + +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.prci._ + +import scala.collection.mutable + +object FrequencyUtils { + def computeReferenceFrequencyMHz( + requestedOutputs: Seq[ClockParameters], + maximumAllowableDivisor: Int = 0xFFFF): ClockParameters = { + require(requestedOutputs.nonEmpty) + require(!requestedOutputs.contains(0.0)) + val freqs = requestedOutputs.map(f => BigInt(Math.round(f.freqMHz * 1000 * 1000))) + val refFreq = freqs.reduce((a, b) => a * b / a.gcd(b)).toDouble / (1000 * 1000) + assert((refFreq / freqs.min.toDouble) < maximumAllowableDivisor.toDouble) + ClockParameters(refFreq) + } +} + +case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) + extends MixedNexusNode(ClockImp, ClockGroupImp)( + dFn = { _ => ClockGroupSourceParameters() }, + uFn = { u => + require(u.size == 1) + require(!u.head.members.contains(None), + "All output clocks in group must set their take parameters. Use a ClockGroupDealiaser") + ClockSinkParameters( + name = Some(s"${pllName}_reference_input"), + take = Some(FrequencyUtils.computeReferenceFrequencyMHz(u.head.members.flatMap(_.take)))) } + ) + +class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { + val node = IdealizedPLLNode(pllName) + + lazy val module = new LazyRawModuleImp(this) { + require(node.out.size == 1, "Must use a ClockGroupAggregator") + val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head + val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head + + val referenceFreq = refSinkParam.take.get.freqMHz + val requestedFreqs = outSinkParams.members.map(m => m.name -> m.take) + + val dividedClocks = mutable.HashMap[Int, Clock]() + def instantiateDivider(div: Int): Clock = { + val divider = Module(new ClockDividerN(div)) + divider.suggestName(s"ClockDivideBy${div}") + divider.io.clk_in := refClock.clock + dividedClocks(div) = divider.io.clk_out + divider.io.clk_out + } + + for (((sinkBName, sinkB), sinkP) <- outClocks.member.elements.zip(outSinkParams.members)) { + val requested = sinkP.take.get.freqMHz + val div = Math.round(referenceFreq / requested).toInt + val actual = referenceFreq / div.toDouble + println(s"Clock ${sinkBName}, requested freq: ${requested} MHz. Actual freq: ${actual} MHz via division of ${div}") + sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div)) + } + } +} + +object IdealizedPLL { + def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new IdealizedPLL(valName.name)).node +} diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 16d298fb..a4e1af72 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -182,4 +182,11 @@ class DividedClockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) - +// Multiclock Sketch +class ForcedClockRocketConfig extends Config( + new chipyard.config.WithForcedTileFrequency(200) ++ + new chipyard.config.WithIdealizedPLL ++ // Put the Tile on its own clock domain + //new chipyard.config.WithTileDividedClock ++ // Put the Tile on its own clock domain + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) From 8e4dedcecfe7c0f7a4e1a5a0e3cfdc867479cfcd Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 16 Sep 2020 16:30:00 -0700 Subject: [PATCH 196/457] Remove require guard on divided configs --- generators/chipyard/src/main/scala/Clocks.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 01d6c828..afe04eaf 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -134,8 +134,6 @@ object ClockingSchemeGenerators { val harnessDividedClock: ChipTop => Unit = { chiptop => implicit val p = chiptop.p - require(false, "Divided clock is broken until we fix passing onchip clocks to TestHarness objects") - val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) chiptop.implicitClockSinkNode := implicitClockSourceNode From b8d3e4a66d6e8a984bc49cc0ca1d11f0d49a87ed Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 16 Sep 2020 16:30:25 -0700 Subject: [PATCH 197/457] Update Idealized PLL config --- generators/chipyard/src/main/scala/Clocks.scala | 4 ++-- generators/chipyard/src/main/scala/ConfigFragments.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index afe04eaf..7c9ade21 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -179,7 +179,7 @@ object ClockingSchemeGenerators { implicit val p = chiptop.p // Requires existence of undriven asyncClockGroups in subsystem - val systemAsyncClockGroup = chiptop.lSystem match { + val systemAsyncClockGroup = chiptop.lazySystem match { case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => l.asyncClockGroupsNode } @@ -204,7 +204,7 @@ object ClockingSchemeGenerators { o.reset := reset_wire } - chiptop.harnessFunctions += ((th: HasHarnessUtils) => { + chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { clock_io := th.harnessClock Nil }) } diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 9fb3adb2..03ccdbca 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -193,5 +193,5 @@ class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => { }) class WithIdealizedPLL extends Config((site, here, up) => { - case ChipyardClockKey => ClockDrivers.idealizedPLL + case ClockingSchemeKey => ClockingSchemeGenerators.idealizedPLL }) From cfa7e30d95f82acc69811753183ca6b681f8954a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 17 Sep 2020 11:32:51 -0700 Subject: [PATCH 198/457] [clocks] Fix comment in ClockDividerN --- generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv index 33f7a05b..868b0eee 100644 --- a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv +++ b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv @@ -2,7 +2,7 @@ /** * An unsynthesizable divide-by-N clock divider. - * Duty cycle is 100 * (ceil(DIV / 2)) / 2. + * Duty cycle is 100 * (ceil(DIV / 2)) / DIV. */ module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in); From 6a26a350eee9d67032e6710d20ad59822bd51390 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 17 Sep 2020 11:33:26 -0700 Subject: [PATCH 199/457] [clocks] Update dealiaser based on feedback --- .../src/main/scala/clocking/ClockGroupDealiaser.scala | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala index 3ffea3c0..54b384e9 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.prci._ /** * Somewhat hacky. Since not all clocks in a clock group specify a taken frequency * current, this LazyModule attempts to dealias them, by finding a specified - * clock whose name has the longest matching prefix. + * clock with a matching name. * * Perhaps another, simpler solution would be to pass a default. * @@ -30,17 +30,16 @@ class ClockGroupDealiaser(name: String)(implicit p: Parameters) extends LazyModu val node = ClockGroupDealiaserNode() lazy val module = new LazyRawModuleImp(this) { - require(node.out.size == 1, "Must use a ClockGroupAggregator") + require(node.out.size == 1 && node.in.size == 1, + "ClockGroupDealiaser requires a single ClockGroup, please use a ClockGroupAggregator") val (outClocks, e @ ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head val (inClocks, ClockGroupEdgeParameters(_, inSinkParams, _, _)) = node.in.head val inMap = inClocks.member.data.zip(inSinkParams.members).map({ case (b, p) => p.name -> b}).toMap for (((outBName, outB), outName) <- outClocks.member.elements.zip(outSinkParams.members.map(_.name))) { val inClock = inMap.getOrElse(outName, throw new Exception(""" - | No clock in input group with name: Option matching ${outName}. At least one clock + | No clock in input group with name option matching ${outName}. At least one clock | with the same must specify a frequency in its take parameter.""".stripMargin)) - // This will be removed. - dontTouch(outB) outB := inClock } } From 0f33ea3999f0c7cf5610e4099178c683ada680f8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 17 Sep 2020 11:37:56 -0700 Subject: [PATCH 200/457] [clocks] Stringly specified clock frequencies; DRY out schemes --- .../chipyard/src/main/scala/ChipTop.scala | 2 +- .../chipyard/src/main/scala/Clocks.scala | 122 ++++-------------- .../src/main/scala/ConfigFragments.scala | 39 +++--- .../clocking/ClockGroupNamePrefixer.scala | 65 ++++++++++ .../main/scala/clocking/IdealizedPLL.scala | 20 ++- .../src/main/scala/config/RocketConfigs.scala | 13 +- 6 files changed, 125 insertions(+), 136 deletions(-) create mode 100644 generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index dfe08780..1cef2180 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -31,7 +31,7 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") // The implicitClockSinkNode provides the implicit clock and reset for the System - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) // Generate Clocks and Reset p(ClockingSchemeKey)(this) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 7c9ade21..609bf8a0 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -6,13 +6,13 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} -import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody, LazyModule} import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} import barstools.iocell.chisel._ -import chipyard.clocking.{IdealizedPLL, ClockGroupDealiaser} +import chipyard.clocking.{IdealizedPLL, ClockGroupDealiaser, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} /** * Chipyard provides three baseline, top-level reset schemes, set using the @@ -80,101 +80,26 @@ object GenerateReset { } -case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.harnessClock) +case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.idealizedPLL) +/** + * This is a dictionary of clock name to clock frequency in MHz. Names + * correspond to the IO coming off digital top. If the map is undefined for the given name, + * it will return a default value -- DFU. + */ +case object ClockFrequencyAssignment extends Field[Seq[(String) => Option[Double]]](Seq.empty) +case object DefaultClockFrequencyKey extends Field[Double](100.0) +class ClockNameMatchesAssignment(name: String, fMHz: Double) extends Config((site, here, up) => { + case ClockFrequencyAssignment => up(ClockFrequencyAssignment, site) ++ + Seq((cName: String) => if (cName == name) Some(fMHz) else None) +}) +class ClockNameContainsAssignment(name: String, fMHz: Double) extends Config((site, here, up) => { + case ClockFrequencyAssignment => up(ClockFrequencyAssignment, site) ++ + Seq((cName: String) => if (cName.contains(name)) Some(fMHz) else None) +}) object ClockingSchemeGenerators { - // A simple clock provider, for testing - val harnessClock: ChipTop => Unit = { chiptop => - implicit val p = chiptop.p - - val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) - chiptop.implicitClockSinkNode := implicitClockSourceNode - - // Drive the diplomaticclock graph of the DigitalTop (if present) - val simpleClockGroupSourceNode = chiptop.lazySystem match { - case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { - val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - l.asyncClockGroupsNode := n - Some(n) - } - case _ => None - } - - InModuleBody { - //this needs directionality so generateIOFromSignal works - val clock_wire = Wire(Input(Clock())) - val reset_wire = GenerateReset(chiptop, clock_wire) - val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) - chiptop.iocells ++= clockIOCell - clock_io.suggestName("clock") - - implicitClockSourceNode.out.unzip._1.map { o => - o.clock := clock_wire - o.reset := reset_wire - } - - simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => - out.member.data.foreach { o => - o.clock := clock_wire - o.reset := reset_wire - } - }} - - chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { - clock_io := th.harnessClock - Nil - }) - } - - } - - - val harnessDividedClock: ChipTop => Unit = { chiptop => - implicit val p = chiptop.p - - val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) - chiptop.implicitClockSinkNode := implicitClockSourceNode - - val simpleClockGroupSourceNode = chiptop.lazySystem match { - case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { - val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - l.asyncClockGroupsNode := n - Some(n) - } - case _ => throw new Exception("Harness multiclock assumes BaseSubsystem") - } - - InModuleBody { - // this needs directionality so generateIOFromSignal works - val clock_wire = Wire(Input(Clock())) - val reset_wire = GenerateReset(chiptop, clock_wire) - val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) - chiptop.iocells ++= clockIOCell - clock_io.suggestName("clock") - val div_clock = Pow2ClockDivider(clock_wire, 2) - - implicitClockSourceNode.out.unzip._1.map { o => - o.clock := div_clock - o.reset := reset_wire - } - - simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => - out.member.elements.map { case (name, data) => - // This is mega hacks, how are you actually supposed to do this? - data.clock := (if (name.contains("core")) clock_wire else div_clock) - data.reset := reset_wire - } - }} - - chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { - clock_io := th.harnessClock - Nil - }) - } - } - val idealizedPLL: ChipTop => Unit = { chiptop => implicit val p = chiptop.p @@ -184,15 +109,18 @@ object ClockingSchemeGenerators { l.asyncClockGroupsNode } - val aggregator = ClockGroupAggregator() + val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node chiptop.implicitClockSinkNode := ClockGroup() := aggregator - systemAsyncClockGroup := aggregator + systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) - aggregator := ClockGroupDealiaser() := IdealizedPLL() := referenceClockSource + (aggregator + := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignment), p(DefaultClockFrequencyKey)) + := IdealizedPLL() + := referenceClockSource) + InModuleBody { - val clock_wire = Wire(Input(Clock())) val reset_wire = GenerateReset(chiptop, clock_wire) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock")) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 03ccdbca..94b6477b 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -26,7 +26,7 @@ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingSchemeKey, TestSuitesKey, TestSuiteHelper} +import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingSchemeKey, TestSuitesKey, TestSuiteHelper, ClockNameContainsAssignment} // Imports for multiclock sketch import boom.common.{BoomTile, BoomTileParams} @@ -163,10 +163,6 @@ class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { case SubsystemDriveAsyncClockGroupsKey => None }) -class WithTileDividedClock extends Config((site, here, up) => { - case ClockingSchemeKey => ClockingSchemeGenerators.harnessDividedClock -}) - class WithDMIDTM extends Config((site, here, up) => { case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) }) @@ -175,23 +171,20 @@ class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None }) - // Multiclock sketch -class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => - val genericAttachParams = up(TilesLocated(InSubsystem), site) map { - case b: BoomTileAttachParams => GenericallyAttachableTile[BoomTile]( - b.tileParams, GenericCrossingParams(b.crossingParams), b.lookup) - case r: RocketTileAttachParams => GenericallyAttachableTile[RocketTile]( - r.tileParams, GenericCrossingParams(r.crossingParams), r.lookup) - case a: ArianeTileAttachParams => GenericallyAttachableTile[ArianeTile]( - a.tileParams, GenericCrossingParams(a.crossingParams), a.lookup) - case g: GenericallyAttachableTile[_] => g - } - genericAttachParams.map(p => p.copy(crossingParams = p.crossingParams.copy( - injectClockNodeFunc = ClockNodeInjectionUtils.forceTakeFrequency(fMHz)))) -}) +//class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => { +// case TilesLocated(InSubsystem) => +// val genericAttachParams = up(TilesLocated(InSubsystem), site) map { +// case b: BoomTileAttachParams => GenericallyAttachableTile[BoomTile]( +// b.tileParams, GenericCrossingParams(b.crossingParams), b.lookup) +// case r: RocketTileAttachParams => GenericallyAttachableTile[RocketTile]( +// r.tileParams, GenericCrossingParams(r.crossingParams), r.lookup) +// case a: ArianeTileAttachParams => GenericallyAttachableTile[ArianeTile]( +// a.tileParams, GenericCrossingParams(a.crossingParams), a.lookup) +// case g: GenericallyAttachableTile[_] => g +// } +// genericAttachParams.map(p => p.copy(crossingParams = p.crossingParams.copy( +// injectClockNodeFunc = ClockNodeInjectionUtils.forceTakeFrequency(fMHz)))) +//}) -class WithIdealizedPLL extends Config((site, here, up) => { - case ClockingSchemeKey => ClockingSchemeGenerators.idealizedPLL -}) +class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala new file mode 100644 index 00000000..bf756003 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala @@ -0,0 +1,65 @@ +package chipyard.clocking + +import chisel3._ + +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.prci._ + +/** + * This sort of node can be used when it is a connectivity passthrough, but modifies + * the flow of parameters (which may result in changing the names of the underlying signals). + */ +class ClockGroupParameterModifier( + sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m }, + sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { s => s })( + implicit p: Parameters, v: ValName) extends LazyModule { + val node = ClockGroupAdapterNode(sourceFn, sinkFn) + lazy val module = new LazyRawModuleImp(this) { + (node.out zip node.in).map { case ((o, _), (i, _)) => + (o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD } + } + } +} + +/** + * Pushes the ClockGroup's name into each member's name field as a prefix. This is + * intended to be used before a ClockGroupAggregator so that sources from + * different aggregated ClockGroups can be disambiguated by their names. + */ +object ClockGroupNamePrefixer { + def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = + LazyModule(new ClockGroupParameterModifier(sinkFn = { s => s.copy(members = s.members.zipWithIndex.map { case (m, idx) => + m.copy(name = m.name match { + // This matches what the chisel would do if the names were not modified + case Some(clockName) => Some(s"${s.name}_${clockName}") + case None => Some(s"${s.name}_${idx}") + }) + })})).node +} + +/** + * [Word from on high is that Strings are in...] + * Overrides the take field of all clocks in a group, by attempting to apply a + * series of assignment functions: + * (name: String) => freq-in-MHz: Option[Double] + * to each sink. Later functions that return non-empty values take priority. + * The default if all functions return None. + */ +object ClockGroupFrequencySpecifier { + def apply( + assigners: Seq[(String) => Option[Double]], + defaultFreq: Double)( + implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = { + + def lookupFrequencyForName(clock: ClockSinkParameters): ClockSinkParameters = { + require(clock.name.nonEmpty, "All clocks in clock group must have an assigned name") + val clockFreq = assigners.foldLeft(defaultFreq)( + (currentFreq, candidateFunc) => candidateFunc(clock.name.get).getOrElse(currentFreq)) + + clock.copy(take = clock.take.map(_.copy(freqMHz = clockFreq)).orElse(Some(ClockParameters(clockFreq)))) + } + + LazyModule(new ClockGroupParameterModifier(sinkFn = { s => s.copy(members = s.members.map(lookupFrequencyForName)) })).node + } +} diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala index 3de99e8e..6cf03e27 100644 --- a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala +++ b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala @@ -8,6 +8,9 @@ import freechips.rocketchip.prci._ import scala.collection.mutable +/** + * TODO: figure out how much division is acceptable in our simulators and redefine this. + */ object FrequencyUtils { def computeReferenceFrequencyMHz( requestedOutputs: Seq[ClockParameters], @@ -33,16 +36,26 @@ case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) take = Some(FrequencyUtils.computeReferenceFrequencyMHz(u.head.members.flatMap(_.take)))) } ) +/** + * Generates a digttal-divider-only PLL model that verilator can simulate. + * Inspects all take-specified frequencies in the output ClockGroup, calculates a + * fast reference clock (roughly LCM(requested frequencies)) which is passed up the + * diplomatic graph, and then generates dividers for each unique requested + * frequency. + */ + class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { val node = IdealizedPLLNode(pllName) lazy val module = new LazyRawModuleImp(this) { - require(node.out.size == 1, "Must use a ClockGroupAggregator") + require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator") val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head val referenceFreq = refSinkParam.take.get.freqMHz - val requestedFreqs = outSinkParams.members.map(m => m.name -> m.take) + println(s"Idealized PLL Frequency Summary") + println(s"-------------------------------") + println(s" Requested Reference Frequency: ${referenceFreq} MHz") val dividedClocks = mutable.HashMap[Int, Clock]() def instantiateDivider(div: Int): Clock = { @@ -57,8 +70,9 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex val requested = sinkP.take.get.freqMHz val div = Math.round(referenceFreq / requested).toInt val actual = referenceFreq / div.toDouble - println(s"Clock ${sinkBName}, requested freq: ${requested} MHz. Actual freq: ${actual} MHz via division of ${div}") + println(s" Output Clock ${sinkBName}: Requested: ${requested} MHz, Actual: ${actual} MHz (division of ${div})") sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div)) + sinkB.reset := refClock.reset } } } diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index a4e1af72..dd186828 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -174,19 +174,8 @@ class MMIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -// NOTE: This config doesn't work yet because SimWidgets in the TestHarness -// always get the TestHarness clock. The Tiles and Uncore receive the correct clocks class DividedClockRocketConfig extends Config( - new chipyard.config.WithTileDividedClock ++ // Put the Tile on its own clock domain - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - -// Multiclock Sketch -class ForcedClockRocketConfig extends Config( - new chipyard.config.WithForcedTileFrequency(200) ++ - new chipyard.config.WithIdealizedPLL ++ // Put the Tile on its own clock domain - //new chipyard.config.WithTileDividedClock ++ // Put the Tile on its own clock domain + new chipyard.config.WithTileFrequency(200.0) ++ new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) From ad147ec7f227abd1c02935e8c429280f00e45990 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 17 Sep 2020 11:39:01 -0700 Subject: [PATCH 201/457] [clocks] Remove dealiaser and node injector until they are needed --- .../chipyard/src/main/scala/Clocks.scala | 2 +- .../src/main/scala/ConfigFragments.scala | 20 +------- .../src/main/scala/GenericAttachParams.scala | 38 -------------- .../scala/clocking/ClockGroupDealiaser.scala | 50 ------------------- .../scala/clocking/ClockNodeInjectors.scala | 29 ----------- 5 files changed, 2 insertions(+), 137 deletions(-) delete mode 100644 generators/chipyard/src/main/scala/GenericAttachParams.scala delete mode 100644 generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala delete mode 100644 generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 609bf8a0..1d3a981e 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} import barstools.iocell.chisel._ -import chipyard.clocking.{IdealizedPLL, ClockGroupDealiaser, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} +import chipyard.clocking.{IdealizedPLL, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} /** * Chipyard provides three baseline, top-level reset schemes, set using the diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 94b6477b..19fe0630 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -31,8 +31,6 @@ import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingScheme // Imports for multiclock sketch import boom.common.{BoomTile, BoomTileParams} import ariane.{ArianeTile, ArianeTileParams} -import chipyard.{GenericallyAttachableTile, GenericCrossingParams} -import chipyard.clocking.{ClockNodeInjectionUtils } // ----------------------- // Common Config Fragments // ----------------------- @@ -169,22 +167,6 @@ class WithDMIDTM extends Config((site, here, up) => { class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None + }) - -// Multiclock sketch -//class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => { -// case TilesLocated(InSubsystem) => -// val genericAttachParams = up(TilesLocated(InSubsystem), site) map { -// case b: BoomTileAttachParams => GenericallyAttachableTile[BoomTile]( -// b.tileParams, GenericCrossingParams(b.crossingParams), b.lookup) -// case r: RocketTileAttachParams => GenericallyAttachableTile[RocketTile]( -// r.tileParams, GenericCrossingParams(r.crossingParams), r.lookup) -// case a: ArianeTileAttachParams => GenericallyAttachableTile[ArianeTile]( -// a.tileParams, GenericCrossingParams(a.crossingParams), a.lookup) -// case g: GenericallyAttachableTile[_] => g -// } -// genericAttachParams.map(p => p.copy(crossingParams = p.crossingParams.copy( -// injectClockNodeFunc = ClockNodeInjectionUtils.forceTakeFrequency(fMHz)))) -//}) - class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) diff --git a/generators/chipyard/src/main/scala/GenericAttachParams.scala b/generators/chipyard/src/main/scala/GenericAttachParams.scala deleted file mode 100644 index f90598af..00000000 --- a/generators/chipyard/src/main/scala/GenericAttachParams.scala +++ /dev/null @@ -1,38 +0,0 @@ - -package chipyard - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tile.{LookupByHartIdImpl, TileParams, InstantiableTileParams, BaseTile} - -import chipyard.clocking.ClockNodeInjectionUtils._ - -case class GenericCrossingParams( - crossingType: ClockCrossingType = SynchronousCrossing(), - master: TilePortParamsLike = TileMasterPortParams(), - slave: TilePortParamsLike = TileSlavePortParams(), - mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS, - injectClockNodeFunc: InjectClockNodeFunc = injectIdentityClockNode, - forceSeparateClockReset: Boolean = false) extends TileCrossingParamsLike { - - def injectClockNode(a: Attachable)(implicit p: Parameters) = injectClockNodeFunc(a, p) -} - -object GenericCrossingParams { - def apply(params: TileCrossingParamsLike): GenericCrossingParams = GenericCrossingParams( - params.crossingType, - params.master, - params.slave, - params.mmioBaseAddressPrefixWhere, - (a: Attachable, p: Parameters) => params.injectClockNode(a)(p), - params.forceSeparateClockReset) -} - -case class GenericallyAttachableTile[TT <: BaseTile]( - tileParams: InstantiableTileParams[TT], - crossingParams: GenericCrossingParams, - lookup: LookupByHartIdImpl) extends CanAttachTile { - type TileType = TT -} - diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala deleted file mode 100644 index 54b384e9..00000000 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala +++ /dev/null @@ -1,50 +0,0 @@ -package chipyard.clocking - -import chisel3._ - -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci._ - -/** - * Somewhat hacky. Since not all clocks in a clock group specify a taken frequency - * current, this LazyModule attempts to dealias them, by finding a specified - * clock with a matching name. - * - * Perhaps another, simpler solution would be to pass a default. - * - */ - -case class ClockGroupDealiaserNode()(implicit valName: ValName) - extends NexusNode(ClockGroupImp)( - dFn = { _ => ClockGroupSourceParameters() }, - uFn = { u => - require(u.size == 1) - val takenClocks = u.head.members.filter(_.take.nonEmpty) - require(takenClocks.nonEmpty, - "At least one sink clock in clock group must specify its take parameter") - u.head.copy(members = takenClocks) - }) - -class ClockGroupDealiaser(name: String)(implicit p: Parameters) extends LazyModule { - val node = ClockGroupDealiaserNode() - - lazy val module = new LazyRawModuleImp(this) { - require(node.out.size == 1 && node.in.size == 1, - "ClockGroupDealiaser requires a single ClockGroup, please use a ClockGroupAggregator") - val (outClocks, e @ ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head - val (inClocks, ClockGroupEdgeParameters(_, inSinkParams, _, _)) = node.in.head - val inMap = inClocks.member.data.zip(inSinkParams.members).map({ case (b, p) => p.name -> b}).toMap - - for (((outBName, outB), outName) <- outClocks.member.elements.zip(outSinkParams.members.map(_.name))) { - val inClock = inMap.getOrElse(outName, throw new Exception(""" - | No clock in input group with name option matching ${outName}. At least one clock - | with the same must specify a frequency in its take parameter.""".stripMargin)) - outB := inClock - } - } -} - -object ClockGroupDealiaser { - def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupDealiaser(valName.name)).node -} diff --git a/generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala b/generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala deleted file mode 100644 index 981ed327..00000000 --- a/generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala +++ /dev/null @@ -1,29 +0,0 @@ - -package chipyard.clocking - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.prci.{ClockNode, ClockTempNode, ClockAdapterNode, ClockParameters} -/** - * An adapter node hack c that just throws out the existing sink node - * clock parameters in favor of the provided ones. - */ -class ForceTakeClock(clockParams: Option[ClockParameters])(implicit p: Parameters, v: ValName) extends LazyModule { - val node = ClockAdapterNode(sinkFn = { s => s.copy(take = clockParams) }) - lazy val module = new LazyRawModuleImp(this) { - (node.out zip node.in) map { case ((o, _), (i, _)) => o := i } - } -} - -object ForceTakeClock { - def apply(clockParams: Option[ClockParameters])(implicit p: Parameters, v: ValName): ClockAdapterNode = - LazyModule(new ForceTakeClock(clockParams)).node -} - -object ClockNodeInjectionUtils { - type InjectClockNodeFunc = (Attachable, Parameters) => ClockNode - val injectIdentityClockNode: InjectClockNodeFunc = (a: Attachable, p: Parameters) => ClockTempNode() - def forceTakeFrequency(freqMHz: Double): InjectClockNodeFunc = - (a: Attachable, p: Parameters) => ForceTakeClock(Some(ClockParameters(freqMHz)))(p, ValName("ForcedTakeClock")) -} From 9135cda9597546805ca58fd9aeefb5c273d90593 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Thu, 17 Sep 2020 13:43:28 -0700 Subject: [PATCH 202/457] Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core. --- fpga/src/main/scala/arty/TestHarness.scala | 2 +- fpga/src/main/scala/arty/e300/IOBinders.scala | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 919e5c99..8f0b7143 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -26,7 +26,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val harnessClock = clock_32MHz val harnessReset = hReset val success = false.B - val dutReset = hReset + val dutReset = reset_core // must be after HasHarnessSignalReferences assignments ldut.harnessFunctions.foreach(_(this)) diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 8d866619..6cab4b1e 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -56,10 +56,8 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = system.aon.rsts.corerst - // Add in debug-controlled reset. - system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) + val io_async_corerst = IO(Input(Bool())).suggestName("core_reset") + system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20) Debug.connectDebugClockAndReset(system.debug, system.clock) //----------------------------------------------------------------------- @@ -186,6 +184,8 @@ class WithE300Connections extends OverrideIOBinder({ val harnessFn = (baseTh: HasHarnessSignalReferences) => { baseTh match { case th: ArtyShell => + io_async_corerst := th.reset_core + //----------------------------------------------------------------------- // Clock divider //----------------------------------------------------------------------- From aa355c7c1abb3980f28ba167b8ebac89b9255fb2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 18 Sep 2020 10:41:59 -0700 Subject: [PATCH 203/457] Bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 2b52057e..7b2691c9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2b52057e158fd91d44c6259aa08869622a88040a +Subproject commit 7b2691c935aef13fd9de0e8d95d99ad9bceaab2e From bbf941c865f660fbf15ddac2c4f579a55628191f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 18 Sep 2020 10:43:58 -0700 Subject: [PATCH 204/457] Bump Firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7b2691c9..3dbe8aee 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7b2691c935aef13fd9de0e8d95d99ad9bceaab2e +Subproject commit 3dbe8aee3f917079e7319391bac5d23d2ba5e6de From f36183d236ea6a7ea48041f5da084665c443d2fd Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 17 Sep 2020 12:17:02 -0700 Subject: [PATCH 205/457] [clocks] Update AssignerKey name and comment --- generators/chipyard/src/main/scala/Clocks.scala | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 1d3a981e..499d4844 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -82,20 +82,21 @@ object GenerateReset { case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.idealizedPLL) /** - * This is a dictionary of clock name to clock frequency in MHz. Names - * correspond to the IO coming off digital top. If the map is undefined for the given name, - * it will return a default value -- DFU. + * This is a Seq of assignment functions, that accept a clock name and return an optional frequency. + * Functions that appear later in this seq have higher precedence that earlier ones. + * If no function returns a non-empty value, the value specified in + * [[DefaultClockFrequencyKey]] will be used -- DFU. */ -case object ClockFrequencyAssignment extends Field[Seq[(String) => Option[Double]]](Seq.empty) +case object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty) case object DefaultClockFrequencyKey extends Field[Double](100.0) class ClockNameMatchesAssignment(name: String, fMHz: Double) extends Config((site, here, up) => { - case ClockFrequencyAssignment => up(ClockFrequencyAssignment, site) ++ + case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ Seq((cName: String) => if (cName == name) Some(fMHz) else None) }) class ClockNameContainsAssignment(name: String, fMHz: Double) extends Config((site, here, up) => { - case ClockFrequencyAssignment => up(ClockFrequencyAssignment, site) ++ + case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ Seq((cName: String) => if (cName.contains(name)) Some(fMHz) else None) }) @@ -115,7 +116,7 @@ object ClockingSchemeGenerators { val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) (aggregator - := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignment), p(DefaultClockFrequencyKey)) + := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) := IdealizedPLL() := referenceClockSource) From a43400acb9f0397c18c510d72827933fb1e65991 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 15:36:14 -0700 Subject: [PATCH 206/457] Update CI --- .circleci/config.yml | 94 +++++++++++++++++-- .circleci/defaults.sh | 6 +- .circleci/run-tests.sh | 14 ++- .../src/main/scala/config/SodorConfigs.scala | 30 +++--- generators/riscv-sodor | 2 +- 5 files changed, 124 insertions(+), 22 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 7b09791c..a695cf28 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,11 +262,31 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-ariane" - prepare-chipyard-sodor: + prepare-chipyard-sodor-stage1: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-sodor" + project-key: "chipyard-sodor-stage1" + prepare-chipyard-sodor-stage2: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage2" + prepare-chipyard-sodor-stage3: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage3" + prepare-chipyard-sodor-stage5: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage5" + prepare-chipyard-sodor-ucode: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-ucode" prepare-icenet: executor: main-env steps: @@ -395,11 +415,35 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" - chipyard-sodor-run-tests: + chipyard-sodor-stage1-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-sodor" + project-key: "chipyard-sodor-stage1" + timeout: "20m" + chipyard-sodor-stage2-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage2" + timeout: "20m" + chipyard-sodor-stage3-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage3" + timeout: "20m" + chipyard-sodor-stage5-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage5" + timeout: "20m" + chipyard-sodor-ucode-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-ucode" timeout: "20m" chipyard-nvdla-run-tests: executor: main-env @@ -522,7 +566,27 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-chipyard-sodor: + - prepare-chipyard-sodor-stage1: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage2: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage3: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage5: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-ucode: requires: - install-riscv-toolchain - install-verilator @@ -632,9 +696,25 @@ workflows: requires: - prepare-chipyard-ariane - - chipyard-sodor-run-tests: + - chipyard-sodor-stage1-run-tests: requires: - - prepare-chipyard-sodor + - prepare-chipyard-sodor-stage1 + + - chipyard-sodor-stage2-run-tests: + requires: + - prepare-chipyard-sodor-stage2 + + - chipyard-sodor-stage3-run-tests: + requires: + - prepare-chipyard-sodor-stage3 + + - chipyard-sodor-stage5-run-tests: + requires: + - prepare-chipyard-sodor-stage5 + + - chipyard-sodor-ucode-run-tests: + requires: + - prepare-chipyard-sodor-ucode - chipyard-nvdla-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 703737cd..62b9ceb4 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -69,4 +69,8 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" - +mapping["chipyard-sodor-stage1"]="SUB_PROJEET=Sodor1StageConfig" +mapping["chipyard-sodor-stage2"]="SUB_PROJEET=Sodor2StageConfig" +mapping["chipyard-sodor-stage3"]="SUB_PROJEET=Sodor3StageSinglePortConfig" +mapping["chipyard-sodor-stage5"]="SUB_PROJEET=Sodor5StageConfig" +mapping["chipyard-sodor-ucode"]="SUB_PROJEET=SodorUCodeConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index c0b932b6..cd4afd23 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -91,7 +91,19 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; - chipyard-sodor) + chipyard-sodor-stage1) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage2) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage3) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage5) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-ucode) run_asm ${mapping[$1]} ;; chipyard-nvdla) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index df386dd9..eb7b4086 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -5,43 +5,49 @@ import chisel3._ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( + // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor2StageConfig extends Config( + // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor3StageConfig extends Config( + // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor3StageSinglePortConfig extends Config( + // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor5StageConfig extends Config( + // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class SodorUCodeConfig extends Config( + // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 43985218..69df2b01 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 43985218b8c91c9206018177d81e37e27267dbf6 +Subproject commit 69df2b013f162cf4c450cdc3e7bbd6e7b9f2de16 From 56d1d5b500178af08f7233cfdb463ce8fd0e0e08 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 22:42:19 -0700 Subject: [PATCH 207/457] Fix CI errors --- .circleci/config.yml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 7e8219a3..be39e21a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -462,7 +462,19 @@ workflows: - chipyard-ariane-run-tests: requires: - prepare-chipyard-cores - - chipyard-sodor-run-tests: + - chipyard-sodor-stage1-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-stage2-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-stage3-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-stage5-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-ucode-run-tests: requires: - prepare-chipyard-cores From a02700a1d4a39d433b2e3a2b0bdfad176d9375ed Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 23:14:47 -0700 Subject: [PATCH 208/457] Add documentation for sodor --- docs/Generators/Sodor.rst | 17 +++++++++++++++++ docs/Generators/index.rst | 1 + generators/riscv-sodor | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 docs/Generators/Sodor.rst diff --git a/docs/Generators/Sodor.rst b/docs/Generators/Sodor.rst new file mode 100644 index 00000000..7f4282eb --- /dev/null +++ b/docs/Generators/Sodor.rst @@ -0,0 +1,17 @@ +Sodor Core +==================================== + +`Sodor `__ is a collection of 5 simple RV32MI cores designed for educational purpose. +The `Sodor core` is wrapped in an tile during generation so it can be used as a component within the `Rocket Chip SoC generator`. +The cores contain a small scratchpad memory to which the program are loaded through a TileLink slave port, and the cores **DO NOT** +support external memory. + +The five available cores and their corresponding generator configuration are: + +* 1-stage (essentially an ISA simulator) - ``Sodor1StageConfig`` +* 2-stage (demonstrates pipelining in Chisel) - ``Sodor2StageConfig`` +* 3-stage (uses sequential memory; supports both Harvard (``Sodor3StageConfig``) and Princeton (``Sodor3StageSinglePortConfig``) versions) +* 5-stage (can toggle between fully bypassed or fully interlocked) - ``Sodor5StageConfig`` +* "bus"-based micro-coded implementation - ``SodorUCodeConfig`` + +For more information, please refer to the `GitHub repository `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index be9c5e55..cebb17e5 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -29,4 +29,5 @@ so changes to the generators themselves will automatically be used when building SHA3 Ariane NVDLA + Sodor diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 69df2b01..12fa11e4 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 69df2b013f162cf4c450cdc3e7bbd6e7b9f2de16 +Subproject commit 12fa11e485c4854a48eec0561698dd0b32230243 From ae5fb8470bcfbd06772df0044a6a1a097648e749 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sat, 19 Sep 2020 10:27:20 -0700 Subject: [PATCH 209/457] Remove unnecessary CI tests --- .circleci/config.yml | 47 +++--------------------------------------- .circleci/defaults.sh | 6 +----- .circleci/run-tests.sh | 14 +------------ 3 files changed, 5 insertions(+), 62 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index be39e21a..4ee84ced 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -241,40 +241,12 @@ jobs: group-key: "group-cores" project-key: "chipyard-ariane" timeout: "30m" - chipyard-sodor-stage1-run-tests: + chipyard-sodor-run-tests: executor: main-env steps: - run-tests: group-key: "group-cores" - project-key: "chipyard-sodor-stage1" - timeout: "30m" - chipyard-sodor-stage2-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-stage2" - timeout: "30m" - chipyard-sodor-stage3-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-stage3" - timeout: "30m" - chipyard-sodor-stage5-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-stage5" - timeout: "30m" - chipyard-sodor-ucode-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-ucode" + project-key: "chipyard-sodor" timeout: "30m" chipyard-dmirocket-run-tests: executor: main-env @@ -462,22 +434,9 @@ workflows: - chipyard-ariane-run-tests: requires: - prepare-chipyard-cores - - chipyard-sodor-stage1-run-tests: + - chipyard-sodor-run-tests: requires: - prepare-chipyard-cores - - chipyard-sodor-stage2-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-sodor-stage3-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-sodor-stage5-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-sodor-ucode-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-dmirocket-run-tests: requires: - prepare-chipyard-peripherals diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 75101884..e3318d87 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -79,8 +79,4 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" -mapping["chipyard-sodor-stage1"]="SUB_PROJEET=Sodor1StageConfig" -mapping["chipyard-sodor-stage2"]="SUB_PROJEET=Sodor2StageConfig" -mapping["chipyard-sodor-stage3"]="SUB_PROJEET=Sodor3StageSinglePortConfig" -mapping["chipyard-sodor-stage5"]="SUB_PROJEET=Sodor5StageConfig" -mapping["chipyard-sodor-ucode"]="SUB_PROJEET=SodorUCodeConfig" +mapping["chipyard-sodor"]="CONFIG=Sodor5StageConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 37b22b70..da5029b5 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -94,19 +94,7 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv ;; - chipyard-sodor-stage1) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-stage2) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-stage3) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-stage5) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-ucode) + chipyard-sodor) run_asm ${mapping[$1]} ;; chipyard-nvdla) From 6c297e3179a7e32c00dd4a0edb8ed7729b6f2c05 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 22 Sep 2020 11:08:52 -0700 Subject: [PATCH 210/457] Fix smartelf2hex.sh creating files 64x the minimum size --- scripts/smartelf2hex.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh index 782977ff..e6fd1f7a 100755 --- a/scripts/smartelf2hex.sh +++ b/scripts/smartelf2hex.sh @@ -11,4 +11,6 @@ entry_dec=`bc <<< "ibase=16;$entry_hex"` length_hex=`echo "$segments" | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` -elf2hex 64 $power_2_length $binary $entry_dec +width=64 +depth=$((power_2_length / width)) +elf2hex $width $depth $binary $entry_dec From d5660c01f3ada775c671409e593826b56cd9f7bf Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 22 Sep 2020 12:58:34 -0700 Subject: [PATCH 211/457] Bump esp-isa-sim for loadmem-fix add TLS segments to smartelf2hex --- scripts/smartelf2hex.sh | 2 +- toolchains/esp-tools/riscv-isa-sim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh index e6fd1f7a..dd035690 100755 --- a/scripts/smartelf2hex.sh +++ b/scripts/smartelf2hex.sh @@ -8,7 +8,7 @@ binary=$1 segments=`readelf --segments --wide $binary` entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]` entry_dec=`bc <<< "ibase=16;$entry_hex"` -length_hex=`echo "$segments" | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` +length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` width=64 diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index aa332c6a..fa94e84d 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit aa332c6a9a5ec77a9b97cdb4a1978ad394b17f1e +Subproject commit fa94e84d4ff3e23ba909a63376b294e444234752 From 84195d28bb9894a039dda01d506a5a3a952084e1 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 23 Sep 2020 15:29:52 -0700 Subject: [PATCH 212/457] [clocks] Don't override existing take frequency if present. --- .../src/main/scala/clocking/ClockGroupNamePrefixer.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala index bf756003..a5618c2d 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala @@ -57,7 +57,12 @@ object ClockGroupFrequencySpecifier { val clockFreq = assigners.foldLeft(defaultFreq)( (currentFreq, candidateFunc) => candidateFunc(clock.name.get).getOrElse(currentFreq)) - clock.copy(take = clock.take.map(_.copy(freqMHz = clockFreq)).orElse(Some(ClockParameters(clockFreq)))) + clock.copy(take = clock.take match { + case Some(cp) => + println(s"Clock ${clock.name.get}: using diplomatically specified frequency of ${cp.freqMHz}.") + Some(cp) + case None => Some(ClockParameters(clockFreq)) + }) } LazyModule(new ClockGroupParameterModifier(sinkFn = { s => s.copy(members = s.members.map(lookupFrequencyForName)) })).node From 6641c1f983464b133114be6ead681f95559865c5 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 24 Sep 2020 22:42:49 -0700 Subject: [PATCH 213/457] Attempt to fix CI --- .circleci/check-commit.sh | 2 +- .circleci/defaults.sh | 4 ++-- generators/riscv-sodor | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 7824b943..2d393aae 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip") +submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "sodor") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e3318d87..1b41e395 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom" +grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -73,10 +73,10 @@ mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" +mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" -mapping["chipyard-sodor"]="CONFIG=Sodor5StageConfig" diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 12fa11e4..b36ce1a7 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 12fa11e485c4854a48eec0561698dd0b32230243 +Subproject commit b36ce1a7958a748c90508be6822a05c8208cd184 From 96bf702c3b12cd1c6ed73090904a3609fe85ee95 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 24 Sep 2020 23:23:11 -0700 Subject: [PATCH 214/457] [clocks] Factor out the PLL calculations into their own class --- .../src/main/scala/ConfigFragments.scala | 2 +- .../main/scala/clocking/IdealizedPLL.scala | 28 ++++++++++++++----- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 19fe0630..38dea871 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -26,7 +26,7 @@ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingSchemeKey, TestSuitesKey, TestSuiteHelper, ClockNameContainsAssignment} +import chipyard._ // Imports for multiclock sketch import boom.common.{BoomTile, BoomTileParams} diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala index 6cf03e27..44e58053 100644 --- a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala +++ b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import scala.collection.mutable +import scala.collection.immutable.ListMap /** * TODO: figure out how much division is acceptable in our simulators and redefine this. @@ -24,6 +25,23 @@ object FrequencyUtils { } } +class SimplePllConfiguration(val sinks: Seq[ClockSinkParameters]) { + val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz + val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*) + + def prettyPrint(pllName: String) { + val preamble = s""" + |${pllName} Frequency Summary + | Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin + val outputSummaries = sinkDividerMap.map { case (sink, division) => + val requested = sink.take.get.freqMHz + val actual = referenceFreqMHz / division.toDouble + s" Output clock ${sink.name.get}, requested: ${requested} MHz, actual: ${actual} MHz (division of ${division})" + } + println(preamble + outputSummaries.mkString("\n")) + } +} + case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) extends MixedNexusNode(ClockImp, ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, @@ -53,9 +71,8 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head val referenceFreq = refSinkParam.take.get.freqMHz - println(s"Idealized PLL Frequency Summary") - println(s"-------------------------------") - println(s" Requested Reference Frequency: ${referenceFreq} MHz") + val pllConfig = new SimplePllConfiguration(outSinkParams.members) + pllConfig.prettyPrint(pllName) val dividedClocks = mutable.HashMap[Int, Clock]() def instantiateDivider(div: Int): Clock = { @@ -67,10 +84,7 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex } for (((sinkBName, sinkB), sinkP) <- outClocks.member.elements.zip(outSinkParams.members)) { - val requested = sinkP.take.get.freqMHz - val div = Math.round(referenceFreq / requested).toInt - val actual = referenceFreq / div.toDouble - println(s" Output Clock ${sinkBName}: Requested: ${requested} MHz, Actual: ${actual} MHz (division of ${div})") + val div = pllConfig.sinkDividerMap(sinkP) sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div)) sinkB.reset := refClock.reset } From f6989a1968817daec39fd26f37001b93bbe6f853 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 24 Sep 2020 23:24:08 -0700 Subject: [PATCH 215/457] [clocks] Use the periphery frequency as the default --- generators/chipyard/src/main/scala/Clocks.scala | 2 +- generators/chipyard/src/main/scala/ConfigFragments.scala | 6 ++++++ .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 499d4844..531f6add 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -88,7 +88,7 @@ case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGener * [[DefaultClockFrequencyKey]] will be used -- DFU. */ case object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty) -case object DefaultClockFrequencyKey extends Field[Double](100.0) +case object DefaultClockFrequencyKey extends Field[Double]() class ClockNameMatchesAssignment(name: String, fMHz: Double) extends Config((site, here, up) => { case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 38dea871..df20af68 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -169,4 +169,10 @@ class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None }) + class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) + +class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { + case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble +}) + diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 950cb4b4..85d3961b 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -44,6 +44,7 @@ class AbstractConfig extends Config( new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified clocks will match the frequency specified by the pbus dtsFrequency parameter new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) From cc949aadab96c6bd2ba9281fa8cad93a8b5e5d76 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 24 Sep 2020 23:28:47 -0700 Subject: [PATCH 216/457] [clocking] Address some of Colin's PR comments --- generators/chipyard/src/main/scala/ConfigFragments.scala | 4 ---- .../chipyard/src/main/scala/clocking/IdealizedPLL.scala | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index df20af68..d7becac6 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -28,9 +28,6 @@ import sifive.blocks.devices.spi._ import chipyard._ -// Imports for multiclock sketch -import boom.common.{BoomTile, BoomTileParams} -import ariane.{ArianeTile, ArianeTileParams} // ----------------------- // Common Config Fragments // ----------------------- @@ -167,7 +164,6 @@ class WithDMIDTM extends Config((site, here, up) => { class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None - }) class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala index 44e58053..5b99a17b 100644 --- a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala +++ b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala @@ -55,7 +55,7 @@ case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) ) /** - * Generates a digttal-divider-only PLL model that verilator can simulate. + * Generates a digital-divider-only PLL model that verilator can simulate. * Inspects all take-specified frequencies in the output ClockGroup, calculates a * fast reference clock (roughly LCM(requested frequencies)) which is passed up the * diplomatic graph, and then generates dividers for each unique requested From 7b8a954d04ce8346b73786f2f892c4995d95462f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 24 Sep 2020 23:32:07 -0700 Subject: [PATCH 217/457] [firechip] Rework FireSim clocking to be more similar to default CY targets --- .../src/main/scala/BridgeBinders.scala | 12 +- .../firechip/src/main/scala/FireSim.scala | 185 +++++++++--------- .../src/main/scala/TargetConfigs.scala | 2 +- sims/firesim | 2 +- 4 files changed, 96 insertions(+), 105 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 8a4d0a69..9197215c 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -68,9 +68,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { class WithSerialBridge extends OverrideHarnessBinder({ (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => - withClockAndReset(p.clock, th.harnessReset) { - SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system)) - } + SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system)) } Nil } @@ -79,7 +77,7 @@ class WithSerialBridge extends OverrideHarnessBinder({ class WithNICBridge extends OverrideHarnessBinder({ (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { val p: Parameters = GetSystemParameters(system) - ports.map { n => withClockAndReset(n.clock, th.harnessReset) { NICBridge(n.clock, n.bits)(p) } } + ports.map { n => NICBridge(n.clock, n.bits)(p) } Nil } }) @@ -119,11 +117,7 @@ class WithFASEDBridge extends OverrideHarnessBinder({ class WithTracerVBridge extends ComposeHarnessBinder({ (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { - ports.map { p => - p.traces.map( - tileTrace => withClockAndReset(tileTrace.clock, tileTrace.reset) { TracerVBridge(tileTrace)(system.p) } - ) - } + ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) } Nil } }) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index d2ef4e60..d72ec467 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -8,14 +8,15 @@ import chisel3.experimental.{IO} import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule, InModuleBody} -import freechips.rocketchip.util.{ResetCatchAndSync} +import freechips.rocketchip.diplomacy.{LazyModule, InModuleBody, ValName} +import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} import chipyard._ import chipyard.harness._ import chipyard.iobinders._ +import chipyard.clocking.{FrequencyUtils, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier, SimplePllConfiguration} // Determines the number of times to instantiate the DUT in the harness. // Subsumes legacy supernode support @@ -25,16 +26,6 @@ class WithNumNodes(n: Int) extends Config((pname, site, here) => { case NumNodes => n }) -// Note, the main prerequisite for supporting an additional clock domain in a -// FireSim simulation is to supply an additional clock parameter -// (RationalClock) to the clock bridge (RationalClockBridge). The bridge -// produces a vector of clocks, based on the provided parameter list, which you -// may use freely without further modifications to your target design. -case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) { - def numClocks(): Int = additionalClocks.size + 1 -} -case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq())) - // Hacky: Set before each node is generated. Ideally we'd give IO binders // accesses to the the Harness's parameters instance. We could then alter that. object NodeIdx { @@ -43,107 +34,114 @@ object NodeIdx { def apply(): Int = idx } + +/** + * Under FireSim's current multiclock implementation there can be only a + * single clock bridge. This requires, therefore, that it be instantiated in + * the harness and reused across all supernode instances. This class attempts to + * memoize its instantiation such that it can be referenced from within a ClockScheme function. + */ +class ClockBridgeInstantiator { + private var _clockRecord: Option[RecordMap[Clock]] = None + + def getClockRecord: RecordMap[Clock] = _clockRecord.get + + def getClockRecordOrInstantiate(allClocks: Seq[RationalClock], baseClockName: String): RecordMap[Clock] = { + if (_clockRecord.isEmpty) { + require(allClocks.exists(_.name == baseClockName), + s"Provided base-clock name, ${baseClockName}, does not match a defined clock. Available clocks:\n " + + allClocks.map(_.name).mkString("\n ")) + + val baseClock = allClocks.find(_.name == baseClockName).get + val simplified = allClocks.map { c => + c.copy(multiplier = c.multiplier * baseClock.divisor, divisor = c.divisor * baseClock.multiplier) + .simplify + } + + /** + * Removes clocks that have the same frequency before instantiating the + * clock bridge to avoid unnecessary BUFGCE use. + */ + val distinct = simplified.foldLeft(Seq(RationalClock(baseClockName, 1, 1))) { case (list, candidate) => + if (list.exists { clock => clock.equalFrequency(candidate) }) list else list :+ candidate + } + + val clockBridge = Module(new RationalClockBridge(distinct)) + val cbVecTuples = distinct.zip(clockBridge.io.clocks) + val outputWire = Wire(RecordMap(allClocks.map { c => (c.name, Clock()) }:_*)) + for (parameter <- allClocks) { + val (_, cbClockField) = cbVecTuples.find(_._1.equalFrequency(parameter)).get + outputWire(parameter.name).get := cbClockField + } + _clockRecord = Some(outputWire) + } + getClockRecord + } +} + +case object ClockBridgeInstantiatorKey extends Field[ClockBridgeInstantiator](new ClockBridgeInstantiator) +case object FireSimBaseClockNameKey extends Field[String]("implicit_clock") + class WithFireSimSimpleClocks extends Config((site, here, up) => { case ClockingSchemeKey => { chiptop: ChipTop => implicit val p = chiptop.p + // Figure out what provides this in the chipyard scheme + implicit val valName = ValName("FireSimClocking") - val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) - chiptop.implicitClockSinkNode := implicitClockSourceNode - - // Drive the diplomaticclock graph of the DigitalTop (if present) - val simpleClockGroupSourceNode = chiptop.lazySystem match { - case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { - val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - l.asyncClockGroupsNode := n - Some(n) - } - case _ => None + // Requires existence of undriven asyncClockGroups in subsystem + val systemAsyncClockGroup = chiptop.lazySystem match { + case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => + l.asyncClockGroupsNode } + val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node + (chiptop.implicitClockSinkNode := ClockGroup() := aggregator) + (systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator) + + val inputClockSource = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + + (aggregator + := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) + := inputClockSource) + + InModuleBody { - val clock = IO(Input(Clock())).suggestName("clock") + val (clockGroupBundle, clockGroupEdge) = inputClockSource.out.head + val input_clocks = IO(Input(RecordMap((clockGroupEdge.sink.members.map { m => (m.name.get, Clock()) }):_* ))) + .suggestName("clocks") val reset = IO(Input(Reset())).suggestName("reset") - implicitClockSourceNode.out.unzip._1.map { o => - o.clock := clock - o.reset := reset + (clockGroupBundle.member.data zip input_clocks.data).foreach { case (clockBundle, inputClock) => + clockBundle.clock := inputClock } - simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => - out.member.data.foreach { o => - o.clock := clock - o.reset := reset + // Assign resets. The synchronization scheme is still WIP. + for ((name, clockBundle) <- clockGroupBundle.member.elements) { + if (name.contains("core")) { + clockBundle.reset := ResetCatchAndSync(clockBundle.clock, reset.asBool) + } else { + clockBundle.reset := reset } - }} + } + + val pllConfig = new SimplePllConfiguration(clockGroupEdge.sink.members) + pllConfig.prettyPrint("FireSim RationalClockBridge") + val rationalClockSpecs = for ((sinkP, division) <- pllConfig.sinkDividerMap) yield { + RationalClock(sinkP.name.get, 1, division) + } chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { - clock := th.harnessClock reset := th.harnessReset - Nil - }) - } - } -}) - -class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) - case ClockingSchemeKey => { chiptop: ChipTop => - implicit val p = chiptop.p - - val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) - chiptop.implicitClockSinkNode := implicitClockSourceNode - - // Drive the diplomaticclock graph of the DigitalTop (if present) - val simpleClockGroupSourceNode = chiptop.lazySystem match { - case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => { - val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - l.asyncClockGroupsNode := n - Some(n) - } - case _ => None - } - - InModuleBody { - val uncore_clock = IO(Input(Clock())).suggestName("uncore_clock") - val tile_clock = IO(Input(Clock())).suggestName("tile_clock") - val reset = IO(Input(Reset())).suggestName("reset") - - implicitClockSourceNode.out.unzip._1.map { o => - o.clock := uncore_clock - o.reset := reset - } - - simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle => - out.member.elements.map { case (name, data) => - // This is mega hacks, how are you actually supposed to do this? - if (name.contains("core")) { - data.clock := tile_clock - data.reset := ResetCatchAndSync(tile_clock, reset.asBool) - } else { - data.clock := uncore_clock - data.reset := reset - } - } - }} - - chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { - uncore_clock := th.harnessClock - reset := th.harnessReset - th match { - case f: FireSim => tile_clock := f.additionalClocks(0) - case _ => throw new Exception("FireSimMultiClock must be used with FireSim") - } - Nil - }) + input_clocks := p(ClockBridgeInstantiatorKey) + .getClockRecordOrInstantiate(rationalClockSpecs.toSeq, p(FireSimBaseClockNameKey)) + Nil }) } } }) class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSignalReferences { freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) - val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) - val harnessClock = clockBridge.io.clocks.head // This is the reference clock - val additionalClocks = clockBridge.io.clocks.tail + val harnessClock = Wire(Clock()) val harnessReset = WireInit(false.B) val peekPokeBridge = PeekPokeBridge(harnessClock, harnessReset) def dutReset = { require(false, "dutReset should not be used in Firesim"); false.B } @@ -165,8 +163,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna d.harnessFunctions.foreach(_(this)) ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) } - - NodeIdx.increment() } + harnessClock := p(ClockBridgeInstantiatorKey).getClockRecord("implicit_clock").get } diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 2dede960..fcacde8b 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -194,7 +194,7 @@ class FireSimArianeConfig extends Config( //* Multiclock Configurations //*********************************************************************************/ class FireSimMulticlockRocketConfig extends Config( - new WithFireSimRationalTileDomain(2, 1) ++ + new chipyard.config.WithTileFrequency(6400.0) ++ //lol new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ diff --git a/sims/firesim b/sims/firesim index c1cd3e5e..4342b333 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c1cd3e5e7013b30f30508c7f47ff13180949eafe +Subproject commit 4342b33301ae9b3f53b98ca3b1d1afff73d64997 From 1b3514f95f4eb58dc13b41093a3948f1ea0a27a0 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 25 Sep 2020 10:03:46 -0700 Subject: [PATCH 218/457] [clocks] Specify a default frequency for TraceGen --- generators/chipyard/src/main/scala/config/TracegenConfigs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 78cb6851..f9980bf6 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -10,6 +10,7 @@ class AbstractTraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.groundtest.GroundTestBaseConfig) From 67145c6ccd9edf7cf42592d6f50f7f115213e205 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 25 Sep 2020 10:05:28 -0700 Subject: [PATCH 219/457] [clocking] Fix FireSim clock look up --- generators/firechip/src/main/scala/FireSim.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index d72ec467..28daec52 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -68,8 +68,8 @@ class ClockBridgeInstantiator { val clockBridge = Module(new RationalClockBridge(distinct)) val cbVecTuples = distinct.zip(clockBridge.io.clocks) - val outputWire = Wire(RecordMap(allClocks.map { c => (c.name, Clock()) }:_*)) - for (parameter <- allClocks) { + val outputWire = Wire(RecordMap(simplified.map { c => (c.name, Clock()) }:_*)) + for (parameter <- simplified) { val (_, cbClockField) = cbVecTuples.find(_._1.equalFrequency(parameter)).get outputWire(parameter.name).get := cbClockField } From 5243ee2a35fd1ee2c3caba15df4e7eb0cc34d7a9 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 25 Sep 2020 20:36:07 -0700 Subject: [PATCH 220/457] Add HTIF args back to emulator.cc --- generators/utilities/src/main/resources/csrc/emulator.cc | 9 ++++++++- sims/verilator/Makefile | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 5e0ea38b..88a6b26d 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -163,6 +163,7 @@ int main(int argc, char** argv) #if VM_TRACE case 'v': { vcdfile_name = optarg; + // printf("%s\n", vcdfile_name); vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); if (!vcdfile) { std::cerr << "Unable to open " << optarg << " for VCD write\n"; @@ -258,6 +259,11 @@ done_processing: return 1; } + int htif_argc = 1 + argc - optind; + htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + htif_argv[0] = argv[0]; + for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; + if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -265,7 +271,7 @@ done_processing: srand48(random_seed); Verilated::randReset(2); - Verilated::commandArgs(argc, argv); + Verilated::commandArgs(htif_argc, htif_argv); TEST_HARNESS *tile = new TEST_HARNESS; #if VM_TRACE @@ -374,5 +380,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; + if (htif_argv) free(htif_argv); return ret; } diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 8c51098f..211b5676 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,7 +28,7 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -WAVEFORM_FLAG=-v $(sim_out_name).vcd +WAVEFORM_FLAG=-v$(sim_out_name).vcd # If verilator seed unspecified, verilator uses srand as random seed ifdef RANDOM_SEED From 751c0c300ef9e50ecc0805c566865ea2d043dbe0 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 25 Sep 2020 20:49:18 -0700 Subject: [PATCH 221/457] Remove comments --- generators/utilities/src/main/resources/csrc/emulator.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 88a6b26d..d6bca76b 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -163,7 +163,6 @@ int main(int argc, char** argv) #if VM_TRACE case 'v': { vcdfile_name = optarg; - // printf("%s\n", vcdfile_name); vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); if (!vcdfile) { std::cerr << "Unable to open " << optarg << " for VCD write\n"; From f7407709d2a51c5946e1b84e6420651de5cc5802 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 25 Sep 2020 21:31:12 -0700 Subject: [PATCH 222/457] Attempt to fix CI (2) --- .../chipyard/src/main/scala/config/SodorConfigs.scala | 6 ++++++ generators/testchipip | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index eb7b4086..ea245fbc 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -15,6 +16,7 @@ class Sodor1StageConfig extends Config( class Sodor2StageConfig extends Config( // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -23,6 +25,7 @@ class Sodor2StageConfig extends Config( class Sodor3StageConfig extends Config( // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -31,6 +34,7 @@ class Sodor3StageConfig extends Config( class Sodor3StageSinglePortConfig extends Config( // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -39,6 +43,7 @@ class Sodor3StageSinglePortConfig extends Config( class Sodor5StageConfig extends Config( // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -47,6 +52,7 @@ class Sodor5StageConfig extends Config( class SodorUCodeConfig extends Config( // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ diff --git a/generators/testchipip b/generators/testchipip index bdca33ec..bd0ff2d0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bdca33ec1684e6e00df2f5c9aebc0b41fb593585 +Subproject commit bd0ff2d0c61023549304709ce0d377a837564295 From 2aac38b4c81b9623d0a9112ce2dd10949f60b417 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 27 Sep 2020 23:15:10 -0700 Subject: [PATCH 223/457] Fix CI bug --- generators/utilities/src/main/resources/csrc/emulator.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index d6bca76b..a670147d 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -259,7 +259,7 @@ done_processing: } int htif_argc = 1 + argc - optind; - htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + char** htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); htif_argv[0] = argv[0]; for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; From a6ce85039142c9c1e6c14b4e4cabf10674b579d2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 29 Sep 2020 16:06:48 -0700 Subject: [PATCH 224/457] [clocks] ClockDividerN: make first output edge occur on first input edge --- .../chipyard/src/main/resources/vsrc/ClockDividerN.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv index 868b0eee..4d940d06 100644 --- a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv +++ b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv @@ -7,8 +7,10 @@ module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in); - localparam DIV_COUNTER_WIDTH = $clog2(DIV); + localparam CWIDTH = $clog2(DIV); localparam LOW_CYCLES = DIV / 2; + localparam HIGH_TRANSITION = LOW_CYCLES - 1; + localparam LOW_TRANSITION = DIV - 1; generate if (DIV == 1) begin @@ -17,19 +19,19 @@ module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in) clk_out = clk_in; end end else begin - reg [DIV_COUNTER_WIDTH - 1: 0] count = '0; + reg [CWIDTH - 1: 0] count = HIGH_TRANSITION[CWIDTH-1:0]; // The blocking assignment to clock out is used to conform what was done // in RC's clock dividers. // It should have the effect of preventing registers in the divided clock // domain latching register updates launched by the fast clock-domain edge // that occurs at the same simulated time (as the divided clock edge). always @(posedge clk_in) begin - if (count == (DIV - 1)) begin + if (count == LOW_TRANSITION[CWIDTH-1:0]) begin clk_out = 1'b0; count <= '0; end else begin - if (count == (LOW_CYCLES - 1)) begin + if (count == HIGH_TRANSITION[CWIDTH-1:0]) begin clk_out = 1'b1; end count <= count + 1'b1; From 5b414f58299b9f600e1220d77e2b0b92a7a47921 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 29 Sep 2020 16:59:37 -0700 Subject: [PATCH 225/457] [clocks] Emit frequency summary for divider-only PLL model --- .../src/main/scala/clocking/IdealizedPLL.scala | 17 +++++++++-------- .../firechip/src/main/scala/FireSim.scala | 3 +-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala index 5b99a17b..8dfc7908 100644 --- a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala +++ b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala @@ -5,6 +5,7 @@ import chisel3._ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ +import freechips.rocketchip.util.ElaborationArtefacts import scala.collection.mutable import scala.collection.immutable.ListMap @@ -25,21 +26,22 @@ object FrequencyUtils { } } -class SimplePllConfiguration(val sinks: Seq[ClockSinkParameters]) { +class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters]) { val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*) - def prettyPrint(pllName: String) { - val preamble = s""" + private val preamble = s""" |${pllName} Frequency Summary | Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin - val outputSummaries = sinkDividerMap.map { case (sink, division) => + private val outputSummaries = sinkDividerMap.map { case (sink, division) => val requested = sink.take.get.freqMHz val actual = referenceFreqMHz / division.toDouble s" Output clock ${sink.name.get}, requested: ${requested} MHz, actual: ${actual} MHz (division of ${division})" } - println(preamble + outputSummaries.mkString("\n")) - } + + val summaryString = preamble + outputSummaries.mkString("\n") + ElaborationArtefacts.add(s"${pllName}.freq-summary", summaryString) + println(summaryString) } case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) @@ -71,8 +73,7 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head val referenceFreq = refSinkParam.take.get.freqMHz - val pllConfig = new SimplePllConfiguration(outSinkParams.members) - pllConfig.prettyPrint(pllName) + val pllConfig = new SimplePllConfiguration(pllName, outSinkParams.members) val dividedClocks = mutable.HashMap[Int, Clock]() def instantiateDivider(div: Int): Clock = { diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 28daec52..90fd473a 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -124,8 +124,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { } } - val pllConfig = new SimplePllConfiguration(clockGroupEdge.sink.members) - pllConfig.prettyPrint("FireSim RationalClockBridge") + val pllConfig = new SimplePllConfiguration("FireSim RationalClockBridge", clockGroupEdge.sink.members) val rationalClockSpecs = for ((sinkP, division) <- pllConfig.sinkDividerMap) yield { RationalClock(sinkP.name.get, 1, division) } From ebfe3103a45d2b7b4e62609baa083fb4a20647a7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 29 Sep 2020 17:33:49 -0700 Subject: [PATCH 226/457] [clocks] IdealizedPll -> DividerOnlyClockGenerator --- generators/chipyard/src/main/scala/Clocks.scala | 12 ++++++------ ...PLL.scala => DividerOnlyClockGenerator.scala} | 16 ++++++++-------- 2 files changed, 14 insertions(+), 14 deletions(-) rename generators/chipyard/src/main/scala/clocking/{IdealizedPLL.scala => DividerOnlyClockGenerator.scala} (87%) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index b54d5c42..554e9905 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} import barstools.iocell.chisel._ -import chipyard.clocking.{IdealizedPLL, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} +import chipyard.clocking.{DividerOnlyClockGenerator, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} /** * Chipyard provides three baseline, top-level reset schemes, set using the @@ -79,12 +79,12 @@ object GenerateReset { } -case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.idealizedPLL) -/** +case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.dividerOnlyClockGenerator) +/* * This is a Seq of assignment functions, that accept a clock name and return an optional frequency. * Functions that appear later in this seq have higher precedence that earlier ones. * If no function returns a non-empty value, the value specified in - * [[DefaultClockFrequencyKey]] will be used -- DFU. + * [[DefaultClockFrequencyKey]] will be used. */ case object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty) case object DefaultClockFrequencyKey extends Field[Double]() @@ -100,7 +100,7 @@ class ClockNameContainsAssignment(name: String, fMHz: Double) extends Config((si }) object ClockingSchemeGenerators { - val idealizedPLL: ChipTop => Unit = { chiptop => + val dividerOnlyClockGenerator: ChipTop => Unit = { chiptop => implicit val p = chiptop.p // Requires existence of undriven asyncClockGroups in subsystem @@ -116,7 +116,7 @@ object ClockingSchemeGenerators { val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) (aggregator := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) - := IdealizedPLL() + := DividerOnlyClockGenerator() := referenceClockSource) diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala similarity index 87% rename from generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala rename to generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index 8dfc7908..4355fc71 100644 --- a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -26,12 +26,12 @@ object FrequencyUtils { } } -class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters]) { +class SimplePllConfiguration(name: String, val sinks: Seq[ClockSinkParameters]) { val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*) private val preamble = s""" - |${pllName} Frequency Summary + |${name} Frequency Summary | Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin private val outputSummaries = sinkDividerMap.map { case (sink, division) => val requested = sink.take.get.freqMHz @@ -40,11 +40,11 @@ class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters } val summaryString = preamble + outputSummaries.mkString("\n") - ElaborationArtefacts.add(s"${pllName}.freq-summary", summaryString) + ElaborationArtefacts.add(s"${name}.freq-summary", summaryString) println(summaryString) } -case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) +case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName) extends MixedNexusNode(ClockImp, ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { u => @@ -64,8 +64,8 @@ case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) * frequency. */ -class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { - val node = IdealizedPLLNode(pllName) +class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { + val node = DividerOnlyClockGeneratorNode(pllName) lazy val module = new LazyRawModuleImp(this) { require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator") @@ -92,6 +92,6 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex } } -object IdealizedPLL { - def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new IdealizedPLL(valName.name)).node +object DividerOnlyClockGenerator { + def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new DividerOnlyClockGenerator(valName.name)).node } From ef03a5efe0a652ff7fd19ff8b18e9661a12b8fcc Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 30 Sep 2020 14:36:45 -0700 Subject: [PATCH 227/457] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index bd0ff2d0..10351d36 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bd0ff2d0c61023549304709ce0d377a837564295 +Subproject commit 10351d36a961d89e6f5ac1177dff0e9f3efb8c0f From 7d7f7ae4a83f0177a16d8dd0e6aba42d91b3cebd Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 30 Sep 2020 14:43:29 -0700 Subject: [PATCH 228/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 54ffa13d..801baeb9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 54ffa13d980609549be47222a284521b73e56188 +Subproject commit 801baeb901c207beb0511311e09ae10e0dbb8b5f From 2f5790d6111913462006fa7b06e9c42f4663c972 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 30 Sep 2020 12:04:22 -0700 Subject: [PATCH 229/457] Add model multi-threading annotations (ignored by default) to FireChip --- .../firechip/src/main/scala/BridgeBinders.scala | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 653f8026..5a0b4837 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -18,7 +18,7 @@ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvon import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} -import midas.targetutils.{MemModelAnnotation} +import midas.targetutils.{FAMEModelAnnotation, MemModelAnnotation, EnableModelMultiThreadingAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey import tracegen.{TraceGenSystemModuleImp} @@ -156,6 +156,20 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ } }) +class WithFireSimFAME5 extends ComposeIOBinder({ + (system: HasTilesModuleImp) => { + system.outer.tiles.map { + case b: BoomTile => + annotate(FAMEModelAnnotation(b.module)) + annotate(EnableModelMultiThreadingAnnotation(b.module)) + case r: RocketTile => + annotate(FAMEModelAnnotation(r.module)) + annotate(EnableModelMultiThreadingAnnotation(r.module)) + } + (Nil, Nil) + } +}) + // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( new WithSerialBridge ++ @@ -164,6 +178,7 @@ class WithDefaultFireSimBridges extends Config( new WithBlockDeviceBridge ++ new WithFASEDBridge ++ new WithFireSimMultiCycleRegfile ++ + new WithFireSimFAME5 ++ new WithTracerVBridge ++ new WithFireSimIOCellModels ) From 6c33672c664b7990cd443f27d93c977c55817c01 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 1 Oct 2020 10:08:39 -0700 Subject: [PATCH 230/457] Bump Sodor submodule after merge --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index b36ce1a7..d92a8476 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit b36ce1a7958a748c90508be6822a05c8208cd184 +Subproject commit d92a8476e4afbae189381d708136aef7d3970952 From 93a06cc5e7ceeb888cb32f6e3efd0418083f6d38 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 1 Oct 2020 10:11:04 -0700 Subject: [PATCH 231/457] Fix CI master check --- .circleci/check-commit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 2d393aae..68cc975c 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "sodor") +submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then From 489ae695fc8427b7dca264916ce6844f81d59e11 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 10:19:43 -0700 Subject: [PATCH 232/457] Add tile-resetter to all designs --- .../chipyard/src/main/scala/Clocks.scala | 18 +++++++++++++++--- generators/testchipip | 2 +- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 554e9905..8dfb9ac6 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -5,12 +5,13 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci._ -import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} +import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, InstantiatesTiles} import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody, LazyModule} import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} import barstools.iocell.chisel._ +import testchipip.{TLTileResetCtrl} import chipyard.clocking.{DividerOnlyClockGenerator, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} @@ -109,9 +110,20 @@ object ClockingSchemeGenerators { l.asyncClockGroupsNode } + // Add a control register for each tile's reset + val resetSetter = chiptop.lazySystem match { + case sys: BaseSubsystem with InstantiatesTiles => TLTileResetCtrl(sys) + case _ => ClockGroupEphemeralNode() + } + val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node - chiptop.implicitClockSinkNode := ClockGroup() := aggregator - systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator + (chiptop.implicitClockSinkNode + := ClockGroup() + := aggregator) + (systemAsyncClockGroup + := resetSetter + := ClockGroupNamePrefixer() + := aggregator) val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) (aggregator diff --git a/generators/testchipip b/generators/testchipip index bdca33ec..89b528de 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bdca33ec1684e6e00df2f5c9aebc0b41fb593585 +Subproject commit 89b528decffa8fd33f21dd7a6feabb639274f99a From 164617e2d64c716643dfff5925c450c502e9609f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 10:20:10 -0700 Subject: [PATCH 233/457] Fix no-mbus example design --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 11399a62..ab0e16ec 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -117,6 +117,7 @@ class LoopbackNICRocketConfig extends Config( // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ From 79042e4ce86302a7335ab49e9c703a181a237bef Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 10:21:43 -0700 Subject: [PATCH 234/457] Bump to support firesim simulation of no-AXI4DRAM designs --- generators/firechip/src/main/scala/BridgeBinders.scala | 9 +++++---- sims/firesim | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 653f8026..1f8bb418 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} import freechips.rocketchip.amba.axi4.{AXI4Bundle} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart._ @@ -67,9 +67,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { class WithSerialBridge extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { - ports.map { p => - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset) - SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system)) + ports.map { port => + implicit val p = GetSystemParameters(system) + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) + SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) } Nil } diff --git a/sims/firesim b/sims/firesim index 801baeb9..ef615d35 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 801baeb901c207beb0511311e09ae10e0dbb8b5f +Subproject commit ef615d35da118e73f5128d373f17b80884100773 From 3d0022667a905321e4d0af8dc0f1b5672d330e10 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 22:43:43 -0700 Subject: [PATCH 235/457] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 89b528de..b3aa1bea 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 89b528decffa8fd33f21dd7a6feabb639274f99a +Subproject commit b3aa1bea536ee96a1e69796d35f7651a314c2f6a From afc085a5f4e072195726b33d989d1523346adbfb Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sun, 4 Oct 2020 18:13:47 -0700 Subject: [PATCH 236/457] Removed AON block from E300 design. Debug over JTAG still functioning. --- fpga/src/main/scala/arty/e300/Configs.scala | 3 --- fpga/src/main/scala/arty/e300/DigitalTop.scala | 2 -- fpga/src/main/scala/arty/e300/IOBinders.scala | 14 -------------- 3 files changed, 19 deletions(-) diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/e300/Configs.scala index dd9213fc..ee90848e 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.spi._ @@ -38,8 +37,6 @@ class E300DevKitExtra extends Config((site, here, up) => { UARTParams(address = 0x10023000)) case PeripheryI2CKey => List( I2CParams(address = 0x10016000)) - case PeripheryMockAONKey => - MockAONParams(address = 0x10000000) case DTSTimebase => BigInt(32768) case JtagDTMKey => new JtagDTMConfig ( idcodeVersion = 2, diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala index 1bda2680..f7d4d8e7 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -14,10 +14,8 @@ import chipyard.{DigitalTop, DigitalTopModule} // ------------------------------------ class E300DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.mockaon.HasPeripheryMockAON { override lazy val module = new E300DigitalTopModule(this) } class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 6cab4b1e..6675c325 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -12,7 +12,6 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.jtag._ import sifive.blocks.devices.pinctrl._ @@ -31,7 +30,6 @@ class WithE300Connections extends OverrideIOBinder({ with HasPeripheryDebugModuleImp with HasPeripheryPWMModuleImp with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp with HasPeripheryI2CModuleImp) => { implicit val p: Parameters = GetSystemParameters(system) @@ -52,7 +50,6 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") @@ -174,7 +171,6 @@ class WithE300Connections extends OverrideIOBinder({ // AON Pads -- direct connection is OK because // EnhancedPin is hard-coded in MockAONPads // and thus there is no .fromPort method. - io_aon <> system.aon.pins //----------------------------------------------------------------------- //----------------------------------------------------------------------- @@ -322,12 +318,6 @@ class WithE300Connections extends OverrideIOBinder({ IOBUF(th.btn_1, io_gpio.pins(30)) IOBUF(th.btn_2, io_gpio.pins(31)) - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe - attach(th.btn_3, iobuf_btn_3.io.IO) - io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX @@ -343,16 +333,12 @@ class WithE300Connections extends OverrideIOBinder({ // Use the LEDs for some more useful debugging things IOBUF(th.led_0, th.ck_rst) IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) IOBUF(th.led_3, io_gpio.pins(14)) //--------------------------------------------------------------------- // Unconnected inputs //--------------------------------------------------------------------- - io_aon.erst_n.i.ival := ~th.reset_periph - io_aon.lfextclk.i.ival := slow_clock - io_aon.pmu.vddpaden.i.ival := 1.U } Nil From 355e4ba60640724c4325f248e19982ec4e8bf4f4 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 5 Oct 2020 10:49:04 -0700 Subject: [PATCH 237/457] Change to filter all arguments that begin with a '-' --- generators/utilities/src/main/resources/csrc/emulator.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index a670147d..f3c6dbdb 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -258,10 +258,11 @@ done_processing: return 1; } - int htif_argc = 1 + argc - optind; - char** htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + int htif_argc = 1; + char** htif_argv = new char*[argc]; htif_argv[0] = argv[0]; - for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; + for (int i = 1; i < argc; i++) + if (argv[i][0] != '-') htif_argv[htif_argc++] = argv[i]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -379,6 +380,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) free(htif_argv); + if (htif_argv) delete[] htif_argv; return ret; } From 9664b848e945dc2eda242d7a0309a01a2a5f9ff9 Mon Sep 17 00:00:00 2001 From: dunn Date: Tue, 6 Oct 2020 11:20:27 -0700 Subject: [PATCH 238/457] Pointing common.mk's SOURCE_DIR to subdirectories of fpga, to avoid circular dependency caused by pointing to fpga, which contains generated-src. --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index ee290ddc..dba98751 100644 --- a/common.mk +++ b/common.mk @@ -58,7 +58,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk # Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources From 5282965b5b52da2ede3ee2ec0ac5093b93fccd6a Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Tue, 6 Oct 2020 15:50:11 -0700 Subject: [PATCH 239/457] Filter specified HTIF arguments and plusargs only --- .../src/main/resources/csrc/emulator.cc | 23 +++++++++++++------ 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index f3c6dbdb..f42f5bce 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -123,6 +123,10 @@ int main(int argc, char** argv) #endif int verilog_plusargs_legal = 1; + int verilated_argc = 1; + char** verilated_argv = new char*[argc]; + verilated_argv[0] = argv[0]; + opterr = 1; while (1) { @@ -195,9 +199,15 @@ int main(int argc, char** argv) else if (arg.substr(0, 12) == "+cycle-count") c = 'c'; else if (arg == "+permissive") + { c = 'p'; + verilated_argv[verilated_argc++] = optarg; + } else if (arg == "+permissive-off") + { c = 'o'; + verilated_argv[verilated_argc++] = optarg; + } // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { @@ -213,6 +223,7 @@ int main(int argc, char** argv) verilog_plusargs_legal = 0; } else { c = 'P'; + verilated_argv[verilated_argc++] = optarg; } goto retry; } @@ -235,6 +246,7 @@ int main(int argc, char** argv) c = '?'; } else { c = 'p'; + verilated_argv[verilated_argc++] = optarg; } } goto retry; @@ -258,11 +270,8 @@ done_processing: return 1; } - int htif_argc = 1; - char** htif_argv = new char*[argc]; - htif_argv[0] = argv[0]; - for (int i = 1; i < argc; i++) - if (argv[i][0] != '-') htif_argv[htif_argc++] = argv[i]; + // Copy the binary file name into the verilator argument stack + while (optind < argc) verilated_argv[verilated_argc++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -271,7 +280,7 @@ done_processing: srand48(random_seed); Verilated::randReset(2); - Verilated::commandArgs(htif_argc, htif_argv); + Verilated::commandArgs(verilated_argc, verilated_argv); TEST_HARNESS *tile = new TEST_HARNESS; #if VM_TRACE @@ -380,6 +389,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) delete[] htif_argv; + if (verilated_argv) delete[] verilated_argv; return ret; } From a67318928a377c6cf4d8ac8ea6fc7ca48ac71116 Mon Sep 17 00:00:00 2001 From: dunn Date: Wed, 7 Oct 2020 09:02:30 -0700 Subject: [PATCH 240/457] Bumping submodules to upstream dev's commits. --- generators/icenet | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- tools/barstools | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/icenet b/generators/icenet index 705ca506..277a9080 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 705ca50690383aa589dc560a5e7c152af04c46ad +Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 diff --git a/generators/testchipip b/generators/testchipip index 1e7373f6..10351d36 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 1e7373f6398c198e2dee2bcf692917ec2ac21b53 +Subproject commit 10351d36a961d89e6f5ac1177dff0e9f3efb8c0f diff --git a/sims/firesim b/sims/firesim index 05edd6be..801baeb9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 05edd6be8c0464ea53a664a2164d3eba6a7f62aa +Subproject commit 801baeb901c207beb0511311e09ae10e0dbb8b5f diff --git a/tools/barstools b/tools/barstools index aa1c90c4..4a5c75fc 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit aa1c90c4ccb73c2c379550f3296892cc81e8a195 +Subproject commit 4a5c75fcf85f03af858f1d7db04303d4b0733de7 From 392d5b0801c77960c578293445fe24240f3482a9 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 30 Sep 2020 13:18:44 -0700 Subject: [PATCH 241/457] [clocking] Synchronize all output clocks from DividerOnly generator --- .../chipyard/src/main/scala/Clocks.scala | 5 ++-- .../clocking/DividerOnlyClockGenerator.scala | 5 ++++ .../scala/clocking/ResetSynchronizer.scala | 30 +++++++++++++++++++ .../firechip/src/main/scala/FireSim.scala | 13 ++------ 4 files changed, 41 insertions(+), 12 deletions(-) create mode 100644 generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 554e9905..4219c914 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -8,11 +8,11 @@ import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody, LazyModule} -import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} +import freechips.rocketchip.util.{ResetCatchAndSync} import barstools.iocell.chisel._ -import chipyard.clocking.{DividerOnlyClockGenerator, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} +import chipyard.clocking._ /** * Chipyard provides three baseline, top-level reset schemes, set using the @@ -116,6 +116,7 @@ object ClockingSchemeGenerators { val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) (aggregator := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) + := ClockGroupResetSynchronizer() := DividerOnlyClockGenerator() := referenceClockSource) diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index 4355fc71..fb816c35 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -62,6 +62,10 @@ case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValN * fast reference clock (roughly LCM(requested frequencies)) which is passed up the * diplomatic graph, and then generates dividers for each unique requested * frequency. + * + * Output resets are not synchronized to generated clocks and should be + * synchronized by the user in a manner they see fit. + * */ class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { @@ -87,6 +91,7 @@ class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName for (((sinkBName, sinkB), sinkP) <- outClocks.member.elements.zip(outSinkParams.members)) { val div = pllConfig.sinkDividerMap(sinkP) sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div)) + // Reset handling and synchronization is expected to be handled by a downstream node sinkB.reset := refClock.reset } } diff --git a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala new file mode 100644 index 00000000..13a593c5 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala @@ -0,0 +1,30 @@ + +package chipyard.clocking + +import chisel3._ + +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.util.{ResetCatchAndSync} + +/** + * Instantiates a reset synchronizer on all clock-reset pairs in a clock group + */ +class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { + val node = ClockGroupIdentityNode() + lazy val module = new LazyRawModuleImp(this) { + (node.out zip node.in).map { case ((oG, _), (iG, _)) => + (oG.member.data zip iG.member.data).foreach { case (o, i) => + o.clock := i.clock + o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) + } + } + } +} + +object ClockGroupResetSynchronizer { + def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node +} + + diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 90fd473a..cfca74f8 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -16,7 +16,7 @@ import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock import chipyard._ import chipyard.harness._ import chipyard.iobinders._ -import chipyard.clocking.{FrequencyUtils, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier, SimplePllConfiguration} +import chipyard.clocking._ // Determines the number of times to instantiate the DUT in the harness. // Subsumes legacy supernode support @@ -101,6 +101,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { val inputClockSource = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) (aggregator + := ClockGroupResetSynchronizer() := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) := inputClockSource) @@ -113,15 +114,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { (clockGroupBundle.member.data zip input_clocks.data).foreach { case (clockBundle, inputClock) => clockBundle.clock := inputClock - } - - // Assign resets. The synchronization scheme is still WIP. - for ((name, clockBundle) <- clockGroupBundle.member.elements) { - if (name.contains("core")) { - clockBundle.reset := ResetCatchAndSync(clockBundle.clock, reset.asBool) - } else { - clockBundle.reset := reset - } + clockBundle.reset := reset } val pllConfig = new SimplePllConfiguration("FireSim RationalClockBridge", clockGroupEdge.sink.members) From 252f9c6a121889367f1c86354fab8710be1a37c1 Mon Sep 17 00:00:00 2001 From: dunn Date: Wed, 7 Oct 2020 11:55:16 -0700 Subject: [PATCH 242/457] Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging. --- fpga/src/main/scala/arty/TestHarness.scala | 25 +++++++++++++++---- .../chipyard/src/main/scala/DigitalTop.scala | 3 --- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 8f0b7143..cd327243 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -2,13 +2,25 @@ package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{Analog} - +import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} - +import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} - import chipyard.{BuildTop, HasHarnessSignalReferences} +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} + +trait HasTestHarnessFunctions { + val lazySystem: LazyModule + val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] + val portMap = scala.collection.mutable.Map[String, Seq[Data]]() +} + +trait HasHarnessSignalReferences { + def harnessClock: Clock + def harnessReset: Reset + def dutReset: Reset + def success: Bool +} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { @@ -29,6 +41,9 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val dutReset = reset_core // must be after HasHarnessSignalReferences assignments - ldut.harnessFunctions.foreach(_(this)) + ldut match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } } diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 868286eb..c0ac1ff7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -32,12 +32,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp - with testchipip.CanHavePeripheryBlockDeviceModuleImp - with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop From 399b909dec01e32d6c122a626bebabf8c775bf54 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Wed, 7 Oct 2020 20:50:26 -0400 Subject: [PATCH 243/457] Bump firemarshal to v1.10.0 --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index 83b86610..45aebace 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 83b866104c6860b5d03989a6cf8439aa6934b398 +Subproject commit 45aebace86d3a46c357337a19d4c8e894a5d0ed4 From 30b278687b09a09a8806526fce9754efccf64247 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 9 Oct 2020 07:13:55 -0700 Subject: [PATCH 244/457] [clocking] Also aggregate clocks in AsyncClockGroup --- generators/chipyard/src/main/scala/Clocks.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 4219c914..bee73b69 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -111,7 +111,7 @@ object ClockingSchemeGenerators { val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node chiptop.implicitClockSinkNode := ClockGroup() := aggregator - systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator + systemAsyncClockGroup :*= ClockGroupNamePrefixer() :*= aggregator val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) (aggregator From 986b5831c871d74608f689c6f9c978ec394d0572 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 9 Oct 2020 07:23:17 -0700 Subject: [PATCH 245/457] [clocking] Sketch out a topology that puts the MBUS is a separate domain --- .../src/main/scala/CustomBusTopologies.scala | 100 ++++++++++++++++++ .../src/main/scala/HarnessBinders.scala | 12 +-- .../chipyard/src/main/scala/IOBinders.scala | 30 ++++-- .../main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 2 + .../src/main/scala/BridgeBinders.scala | 4 +- .../src/main/scala/TargetConfigs.scala | 6 ++ generators/testchipip | 2 +- 8 files changed, 138 insertions(+), 20 deletions(-) create mode 100644 generators/chipyard/src/main/scala/CustomBusTopologies.scala diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala new file mode 100644 index 00000000..5dbcfe1d --- /dev/null +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -0,0 +1,100 @@ + +package chipyard + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.{Location, Symmetric} +import freechips.rocketchip.subsystem._ + +// I'm putting this code here temporarily as I think it should be a candidate +// for upstreaming based on input from Henry Cook, but don't wnat to deal with +// an RC branch just yet. + +// For subsystem/BusTopology.scala + +/** + * Keys that serve as a means to define crossing types from a Parameters instance + */ +case object SubsystemCrossingParamsKey extends Field[SubsystemCrossingParams](SubsystemCrossingParams()) +case object MemoryBusCrossingTypeKey extends Field[ClockCrossingType](NoCrossing) + +// Biancolin: This, modified from Henry's email +/** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ +case class CoherentBusTopologyParams( + sbus: SystemBusParams, // TODO remove this after better width propagation + mbus: MemoryBusParams, + l2: BankedL2Params, + sbusToMbusXType: ClockCrossingType = NoCrossing +) extends TLBusWrapperTopology( + instantiations = (if (l2.nBanks == 0) Nil else List( + (MBUS, mbus), + (L2, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, l2.nBanks, L2.name)(l2.coherenceManager)))), + connections = if (l2.nBanks == 0) Nil else List( + (SBUS, L2, TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()), + (L2, MBUS, TLBusWrapperConnection.crossTo( + xType = sbusToMbusXType, + driveClockFromMaster = Some(true), + nodeBinding = BIND_QUERY)) + ) +) + +// For subsystem/Configs.scala + +class WithCoherentBusTopology extends Config((site, here, up) => { + case TLNetworkTopologyLocated(InSubsystem) => List( + JustOneBusTopologyParams(sbus = site(SystemBusKey)), + HierarchicalBusTopologyParams( + pbus = site(PeripheryBusKey), + fbus = site(FrontBusKey), + cbus = site(ControlBusKey), + xTypes = SubsystemCrossingParams()), + CoherentBusTopologyParams( + sbus = site(SystemBusKey), + mbus = site(MemoryBusKey), + l2 = site(BankedL2Key), + sbusToMbusXType = site(MemoryBusCrossingTypeKey))) +}) + +/** + * Mixins to specify crossing types between the 5 traditional TL buses + * + * Note: these presuppose the legacy connections between buses and set + * parameters in SubsystemCrossingParams; they may not be resuable in custom + * topologies (but you can specify the desired crossings in your topology). + * + * @param xType The clock crossing type + * + */ +class WithMemoryBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case MemoryBusCrossingTypeKey => xType +}) + +class WithFrontBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) + .copy(fbusToSbusXType = xType) +}) + +class WithControlBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) + .copy(sbusToCbusXType = xType) +}) + +class WithPeripheryBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) + .copy(cbusToPbusXType = xType) +}) + +/** + * Mixins to set the dtsFrequency field of BusParams -- these will percolate it'st way + * through the diplomatic clock graph to the clock sources. + */ +class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) +}) +class WithMemoryBusFrequency(freq: BigInt) extends Config((site, here, up) => { + case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(freq)) +}) + +class WithRationalMemoryBusCrossing extends WithMemoryBusCrossingType(RationalCrossing(Symmetric)) +class WithAsynchrousMemoryBusCrossing extends WithMemoryBusCrossingType(AsynchronousCrossing()) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index e5cfacfb..b5992c7b 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -125,11 +125,11 @@ class WithSimNetwork extends OverrideHarnessBinder({ }) class WithSimAXIMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) - withClockAndReset(port.clock, th.harnessReset) { + withClockAndReset(port.clock, port.reset) { Module(mem.module).suggestName("mem") } mem.io_axi4.head <> port.bits @@ -139,7 +139,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({ }) class WithBlackBoxSimMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size @@ -147,18 +147,18 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)).suggestName("simdram") mem.io.axi <> port.bits mem.io.clock := port.clock - mem.io.reset := th.harnessReset + mem.io.reset := port.reset } Nil } }) class WithSimAXIMMIO extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) - withClockAndReset(port.clock, th.harnessReset) { + withClockAndReset(port.clock, port.reset) { Module(mmio_mem.module).suggestName("mmio_mem") } mmio_mem.io_axi4.head <> port.bits diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 4a31e2c0..1ba6c0a9 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -108,14 +108,23 @@ class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implici }) object BoreHelper { - def apply(name: String, source: Clock): Clock = { - val clock_io = IO(Output(Clock())).suggestName(name) - val clock_wire = Wire(Clock()).suggestName(s"chiptop_${name}") - dontTouch(clock_wire) - clock_wire := false.B.asClock // necessary for BoringUtils to work properly - BoringUtils.bore(source, Seq(clock_wire)) - clock_io := clock_wire - clock_io + def apply[T <: Data](name: String, source: T): T = { + val (io, wire) = source match { + case c: Clock => + val wire = Wire(Clock()) + wire := false.B.asClock + (IO(Output(Clock())), wire) + case r: Reset => + val wire = Wire(Reset()) + wire := false.B + (IO(Output(Reset())), wire) + } + io.suggestName(name) + wire.suggestName(s"chiptop_${name}") + dontTouch(wire) + BoringUtils.bore(source, Seq(wire)) + io := wire + io.asInstanceOf[source.type] } } @@ -257,10 +266,11 @@ class WithSerialTLIOCells extends OverrideIOBinder({ class WithAXI4MemPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort) => { - val ports: Seq[ClockedIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") + val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") p.bits <> m p.clock := BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) + p.reset := BoreHelper("axi4_mem_reset", system.asInstanceOf[BaseSubsystem].mbus.module.reset) p }) (ports, Nil) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 9b04788c..c4b1c9cf 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -49,6 +49,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new chipyard.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 11399a62..e89727f1 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -178,6 +178,8 @@ class DividedClockRocketConfig extends Config( new chipyard.config.WithTileFrequency(200.0) ++ new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.WithMemoryBusFrequency(50 * 1000 * 1000) ++ + new chipyard.WithAsynchrousMemoryBusCrossing ++ new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 5a0b4837..8fa0b54e 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -97,14 +97,14 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({ }) class WithFASEDBridge extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { implicit val p: Parameters = GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) => val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, axi4.bits.ar.bits.addr.getWidth, axi4.bits.ar.bits.id.getWidth) system match { - case s: BaseSubsystem => FASEDBridge(axi4.clock, axi4.bits, th.harnessReset.asBool, + case s: BaseSubsystem => FASEDBridge(axi4.clock, axi4.bits, axi4.reset.asBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)), diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index b70ef647..6ff5065f 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -73,6 +73,12 @@ class WithFireSimConfigTweaks extends Config( // Optional*: Removing this will require adjusting the UART baud rate and // potential target-software changes to properly capture UART output new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ + // Optional: Removing these two configs will result in the FASED timing model running + // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. + // 1 GHz matches the FASED default, using some other frequency will require + // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. + new chipyard.config.WithMemoryBusFrequency(1000 * 1000 * 1000) ++ + new chipyard.config.WithAsynchrousMemoryBusCrossing ++ // Required: Existing FAME-1 transform cannot handle black-box clock gates new WithoutClockGating ++ // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) diff --git a/generators/testchipip b/generators/testchipip index 10351d36..b3987a3a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 10351d36a961d89e6f5ac1177dff0e9f3efb8c0f +Subproject commit b3987a3a784c7175c81aa58016fb3e2df58924c2 From d71c3b6357597da5aca589ee0dda1b7e5f4fe79a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Oct 2020 11:22:55 -0700 Subject: [PATCH 246/457] Unify htif implementation with firesim --- generators/testchipip | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/testchipip b/generators/testchipip index b3aa1bea..9cf31ace 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b3aa1bea536ee96a1e69796d35f7651a314c2f6a +Subproject commit 9cf31acea528543896f04457573454a3e51f1e6a diff --git a/sims/firesim b/sims/firesim index ef615d35..dd20a99f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ef615d35da118e73f5128d373f17b80884100773 +Subproject commit dd20a99f33eba31ffa2d6c7e9fc914445224d4e9 From 25129c27ca20870518161228723e6d55fb31f9de Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Oct 2020 13:07:42 -0700 Subject: [PATCH 247/457] Add testchip_fesvr to uncondtionally used resources --- generators/utilities/src/main/scala/Simulator.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index b2982db7..02224fdb 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -83,6 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { } def resources(sim: Simulator): Seq[String] = Seq( "/testchipip/csrc/SimSerial.cc", + "/testchipip/csrc/testchip_fesvr.cc", + "/testchipip/csrc/testchip_fesvr.h", "/testchipip/csrc/SimDRAM.cc", "/testchipip/csrc/mm.h", "/testchipip/csrc/mm.cc", From 0c46ed167633ebe948ac746f9e0eccd9ab69b361 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 9 Oct 2020 09:34:20 -0700 Subject: [PATCH 248/457] Rename testchip_fesvr to testchip_tsi --- generators/testchipip | 2 +- generators/utilities/src/main/scala/Simulator.scala | 4 ++-- sims/firesim | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/testchipip b/generators/testchipip index 9cf31ace..56bfaa3f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 9cf31acea528543896f04457573454a3e51f1e6a +Subproject commit 56bfaa3f9bcd11206d93fdfa3c8e7656665e462a diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index 02224fdb..f40ad032 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -83,8 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { } def resources(sim: Simulator): Seq[String] = Seq( "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/testchip_fesvr.cc", - "/testchipip/csrc/testchip_fesvr.h", + "/testchipip/csrc/testchip_tsi.cc", + "/testchipip/csrc/testchip_tsi.h", "/testchipip/csrc/SimDRAM.cc", "/testchipip/csrc/mm.h", "/testchipip/csrc/mm.cc", diff --git a/sims/firesim b/sims/firesim index dd20a99f..6318184f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit dd20a99f33eba31ffa2d6c7e9fc914445224d4e9 +Subproject commit 6318184f304315a94b5eb5c670f0eec1a3205f59 From 7d1a1539e6b716e79725974ae9ebe6cace0f07a2 Mon Sep 17 00:00:00 2001 From: dunn Date: Fri, 9 Oct 2020 23:17:36 -0700 Subject: [PATCH 249/457] Initial pass at HarnessBinders for Arty. --- .../main/scala/arty/{e300 => }/Configs.scala | 8 +- .../scala/arty/{e300 => }/DigitalTop.scala | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 73 +++++++++++++++++++ .../scala/arty/{e300 => }/IOBinders.scala | 2 +- 4 files changed, 81 insertions(+), 4 deletions(-) rename fpga/src/main/scala/arty/{e300 => }/Configs.scala (92%) rename fpga/src/main/scala/arty/{e300 => }/DigitalTop.scala (94%) create mode 100644 fpga/src/main/scala/arty/HarnessBinders.scala rename fpga/src/main/scala/arty/{e300 => }/IOBinders.scala (99%) diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/Configs.scala similarity index 92% rename from fpga/src/main/scala/arty/e300/Configs.scala rename to fpga/src/main/scala/arty/Configs.scala index ee90848e..e074dd03 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,6 +16,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import chipyard.{BuildSystem} +import chipyard.iobinders class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( @@ -51,7 +52,10 @@ class WithE300System extends Config((site, here, up) => { class E300ArtyDevKitConfig extends Config( new WithE300System ++ - new WithE300Connections ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ + new WithArtyJTAGHarnessBinder ++ + new WithArtyUARTHarnessBinder ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/DigitalTop.scala similarity index 94% rename from fpga/src/main/scala/arty/e300/DigitalTop.scala rename to fpga/src/main/scala/arty/DigitalTop.scala index f7d4d8e7..858b6215 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/DigitalTop.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import chisel3._ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala new file mode 100644 index 00000000..0d9a8399 --- /dev/null +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -0,0 +1,73 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{Analog} + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.jtag.{JTAGIO} +import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.subsystem._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ + +import barstools.iocell.chisel._ + +import testchipip._ + +import chipyard.harness.OverrideHarnessBinder +import chipyard.HasHarnessSignalReferences +import chipyard.iobinders.GetSystemParameters + +import tracegen.{TraceGenSystemModuleImp} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} + +import scala.reflect.{ClassTag} + +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + + + +class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + ports.map { + case d: ClockedDMIIO => + // Want to error here. + case j: JTAGIO => + //val dtm_success = WireInit(false.B) + //when (dtm_success) { th.success := true.B } + //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + + j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + + IOBUF(th.jd_5, j.TMS) + PULLUP(th.jd_5) + + IOBUF(th.jd_4, j.TDI) + PULLUP(th.jd_4) + + IOBUF(th.jd_0, j.TDO) + + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) + + IOBUF(th.jd_1, j.TRSTn) + PULLUP(th.jd_1) + } + Nil + } +}) + +class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { + //UARTAdapter.connect(ports)(system.p) + IOBUF(th.ck_io(2), ports.txd) + IOBUF(th.ck_io(3), ports.rxd) + Nil + } +}) \ No newline at end of file diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala similarity index 99% rename from fpga/src/main/scala/arty/e300/IOBinders.scala rename to fpga/src/main/scala/arty/IOBinders.scala index 6675c325..2b4b332b 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{attach, IO} From 54acfe71fce0983c9760b7bead421292767f96c0 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sat, 10 Oct 2020 13:45:27 -0700 Subject: [PATCH 250/457] Some HarnessBinder testing with Jerry's debug suggestions. --- fpga/src/main/scala/arty/HarnessBinders.scala | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 0d9a8399..4ee847a5 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -30,44 +30,44 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - - class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { - ports.map { - case d: ClockedDMIIO => - // Want to error here. - case j: JTAGIO => - //val dtm_success = WireInit(false.B) - //when (dtm_success) { th.success := true.B } - //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => { + // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + // ports.map { + // case d: ClockedDMIIO => + // // Want to error here. + // case j: JTAGIO => + // //val dtm_success = WireInit(false.B) + // //when (dtm_success) { th.success := true.B } + // //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) - j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + // j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - IOBUF(th.jd_5, j.TMS) - PULLUP(th.jd_5) + // IOBUF(th.jd_5, j.TMS) + // PULLUP(th.jd_5) - IOBUF(th.jd_4, j.TDI) - PULLUP(th.jd_4) + // IOBUF(th.jd_4, j.TDI) + // PULLUP(th.jd_4) - IOBUF(th.jd_0, j.TDO) + // IOBUF(th.jd_0, j.TDO) - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) + // // mimic putting a pullup on this line (part of reset vote) + // th.SRST_n := IOBUF(th.jd_6) + // PULLUP(th.jd_6) - IOBUF(th.jd_1, j.TRSTn) - PULLUP(th.jd_1) - } + // IOBUF(th.jd_1, j.TRSTn) + // PULLUP(th.jd_1) + // } Nil } }) class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { - //UARTAdapter.connect(ports)(system.p) - IOBUF(th.ck_io(2), ports.txd) - IOBUF(th.ck_io(3), ports.rxd) + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { + // UARTAdapter.connect(ports)(system.p) + // IOBUF(th.ck_io(2), ports.txd) + // IOBUF(th.ck_io(3), ports.rxd) Nil } }) \ No newline at end of file From dca56cd858f5f7b4e7e17e531833b50de6480e72 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sat, 10 Oct 2020 19:55:02 -0700 Subject: [PATCH 251/457] Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala. --- fpga/src/main/scala/arty/Configs.scala | 4 +- fpga/src/main/scala/arty/HarnessBinders.scala | 4 +- fpga/src/main/scala/arty/IOBinders.scala | 351 ------------------ fpga/src/main/scala/arty/TestHarness.scala | 15 +- 4 files changed, 5 insertions(+), 369 deletions(-) delete mode 100644 fpga/src/main/scala/arty/IOBinders.scala diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index e074dd03..e96bcd9c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -52,10 +52,10 @@ class WithE300System extends Config((site, here, up) => { class E300ArtyDevKitConfig extends Config( new WithE300System ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 4ee847a5..3dd380ea 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -31,7 +31,7 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => { + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { // ports.map { // case d: ClockedDMIIO => @@ -63,7 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ }) class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // UARTAdapter.connect(ports)(system.p) // IOBUF(th.ck_io(2), ports.txd) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala deleted file mode 100644 index 2b4b332b..00000000 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ /dev/null @@ -1,351 +0,0 @@ -package chipyard.fpga.arty - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} - -class WithE300Connections extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryDebugModuleImp - with HasPeripheryPWMModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryI2CModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // E300DigitalTop <-> ChipTop connections - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - - object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } - } - - val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") - val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") - val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") - val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - - val io_async_corerst = IO(Input(Bool())).suggestName("core_reset") - system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20) - Debug.connectDebugClockAndReset(system.debug, system.clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = system.uart - val sys_pwm = system.pwm - val sys_spi = system.spi - val sys_i2c = system.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- system.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- system.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = system.gpio(0).iof_0.get - val iof_1 = system.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io_gpio, system.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) - - // JTAG Debug Interface - val sjtag = system.debug.get.systemjtag.get - JTAGPinsFromPort(io_jtag, sjtag.jtag) - sjtag.reset := io_jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io_ndreset := system.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // Harness Function (ArtyHarness <-> ChipTop) - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - val harnessFn = (baseTh: HasHarnessSignalReferences) => { - baseTh match { case th: ArtyShell => - - io_async_corerst := th.reset_core - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = chisel3.util.Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - withClockAndReset(th.clock_32MHz, th.ck_rst) { - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(th.qspi_sck, io_qspi.sck) - IOBUF(th.qspi_cs, io_qspi.cs(0)) - - IOBUF(th.qspi_dq(0), io_qspi.dq(0)) - IOBUF(th.qspi_dq(1), io_qspi.dq(1)) - IOBUF(th.qspi_dq(2), io_qspi.dq(2)) - IOBUF(th.qspi_dq(3), io_qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - - IOBUF(th.jd_5, io_jtag.TMS) - PULLUP(th.jd_5) - - IOBUF(th.jd_4, io_jtag.TDI) - PULLUP(th.jd_4) - - IOBUF(th.jd_0, io_jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) - io_jtag_reset := jtag_power_on_reset - - // debug reset - th.dut_ndreset := io_ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to th.ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := io_gpio.pins(16).o.oval - iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, th.uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(th.sw_3) - io_gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & io_gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) - - IOBUF(th.uart_rxd_out, io_gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(th.ck_io(2), io_gpio.pins(18)) - IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) - IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) - IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) - IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) - IOBUF(th.ck_io(7), io_gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) - IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) - IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO - IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK - - io_gpio.pins(6).i.ival := 0.U - io_gpio.pins(7).i.ival := 0.U - io_gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) - IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) - IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(th.led0_r, io_gpio.pins(1)) - IOBUF(th.led0_g, io_gpio.pins(2)) - IOBUF(th.led0_b, io_gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(th.led1_r, io_gpio.pins(19)) - IOBUF(th.led1_g, io_gpio.pins(21)) - IOBUF(th.led1_b, io_gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(th.led2_r, io_gpio.pins(11)) - IOBUF(th.led2_g, io_gpio.pins(12)) - IOBUF(th.led2_b, io_gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(th.btn_0, io_gpio.pins(15)) - IOBUF(th.btn_1, io_gpio.pins(30)) - IOBUF(th.btn_2, io_gpio.pins(31)) - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX - IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(th.ck_ss, io_gpio.pins(26)) - IOBUF(th.ck_mosi, io_gpio.pins(27)) - IOBUF(th.ck_miso, io_gpio.pins(28)) - IOBUF(th.ck_sck, io_gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(th.led_0, th.ck_rst) - IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_3, io_gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - } - - Nil - } - } - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index cd327243..76dc6a3c 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -6,22 +6,9 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import chipyard.{BuildTop, HasHarnessSignalReferences} +import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} -trait HasTestHarnessFunctions { - val lazySystem: LazyModule - val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] - val portMap = scala.collection.mutable.Map[String, Seq[Data]]() -} - -trait HasHarnessSignalReferences { - def harnessClock: Clock - def harnessReset: Reset - def dutReset: Reset - def success: Bool -} - class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") From 895dcd6831c7fbcfaf74da5a080c45f0a6ebe55d Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sun, 11 Oct 2020 11:12:33 -0700 Subject: [PATCH 252/457] referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue. --- fpga/src/main/scala/arty/HarnessBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 3dd380ea..89105d78 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -30,7 +30,7 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} -class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ +class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { // ports.map { @@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ } }) -class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ +class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // UARTAdapter.connect(ports)(system.p) @@ -70,4 +70,4 @@ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ // IOBUF(th.ck_io(3), ports.rxd) Nil } -}) \ No newline at end of file +}) From d958b8e1aab749161f92bfeac954f9d49fd3abc1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 12 Oct 2020 17:45:07 -0700 Subject: [PATCH 253/457] [ci skip] Update smartelf2hex to use MemSiz instead of FileSiz elf2hex writes zeros to a segment for which MemSize > FileSize, which adheres to the ELF spec. Thus, we should calculate the total size of the file from the MemSize of the last segment, rather than the FileSize. --- scripts/smartelf2hex.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh index dd035690..cc2ea2f8 100755 --- a/scripts/smartelf2hex.sh +++ b/scripts/smartelf2hex.sh @@ -8,7 +8,7 @@ binary=$1 segments=`readelf --segments --wide $binary` entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]` entry_dec=`bc <<< "ibase=16;$entry_hex"` -length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` +length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,7 -d' '` length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` width=64 From 8257775e96650c83b232aa921a8e53038be153fb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 12 Oct 2020 21:50:50 -0700 Subject: [PATCH 254/457] Connect DDR from harness --- fpga/src/main/scala/vcu118/TestHarness.scala | 29 +++++++++++++------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d4e299a5..4275f68d 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -6,6 +6,7 @@ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} +import freechips.rocketchip.tilelink._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ @@ -155,16 +156,24 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar /*** Experimental DDR ***/ - //val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + val ddrWrangler = LazyModule(new ResetWrangler) + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) - //topDesign match { case lazyDut: VCU118Platform => - // lazyDut.lazySystem match { case lazyDutWBus: BaseSubsystem => - // lazyDutWBus { - // InModuleBody { - // ddrPlaced.overlayOutput.ddr := lazyDutWBus.mbus.toDRAMController(Some("xilinxvcu118mig"))() - // } - // } - // } - //} + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: VCU118Platform => + td.lazySystem match { case lsys: chipyard.CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + val bundles = ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> dutMod.io_tl_mem + } + } + ddrPlaced.overlayOutput.ddr := ddrClient } From 9c298eedfe539e05aa409d4b60595f5a0ab2ada1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Oct 2020 15:10:41 -0700 Subject: [PATCH 255/457] Support evaluation of HarnessBinders in LazyModule context --- .../src/main/scala/HarnessBinders.scala | 75 ++++++++++--------- .../chipyard/src/main/scala/IOBinders.scala | 46 +++++------- .../chipyard/src/main/scala/TestHarness.scala | 2 +- .../src/main/scala/BridgeBinders.scala | 16 ++-- 4 files changed, 66 insertions(+), 73 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index e5cfacfb..6f7d2dd8 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.harness import chisel3._ -import chisel3.experimental.{Analog} +import chisel3.experimental.{Analog, BaseModule} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -33,40 +33,41 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer object ApplyHarnessBinders { - def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { + def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters) = { val pm = portMap.withDefaultValue(Nil) - map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + p(HarnessBinders).map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } } } -class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { +class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: S => p}) + val pts = ports.collect({case p: U => p}) require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - t match { - case system: T => fn(system, th, pts) + val upfn = up(HarnessBinders, site)(tag.runtimeClass.toString) + th match { + case th: S => + t match { + case system: T => composer(upfn)(system, th, pts) + case _ => Nil + } case _ => Nil } }) ) }) -class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { - case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> - ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: S => p}) - require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - t match { - case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts) - case _ => Nil - } - }) - ) -}) +class OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) + (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => fn) + +class ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) + (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => (t, th, p) => upfn(t, th, p) ++ fn(t, th, p)) + class WithGPIOTiedOff extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => { + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Analog]) => { ports.foreach { _ <> AnalogConst(0) } Nil } @@ -74,7 +75,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({ // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { UARTAdapter.connect(ports)(system.p) Nil } @@ -82,14 +83,14 @@ class WithUARTAdapter extends OverrideHarnessBinder({ // DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ - (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { + (system: HasPeripherySPIFlashModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p) Nil } }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } Nil @@ -97,7 +98,7 @@ class WithSimBlockDevice extends OverrideHarnessBinder({ }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } Nil @@ -105,7 +106,7 @@ class WithBlockDeviceModel extends OverrideHarnessBinder({ }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => withClockAndReset(n.clock, th.harnessReset) { @@ -117,7 +118,7 @@ class WithLoopbackNIC extends OverrideHarnessBinder({ }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } Nil @@ -125,7 +126,7 @@ class WithSimNetwork extends OverrideHarnessBinder({ }) class WithSimAXIMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) @@ -139,7 +140,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({ }) class WithBlackBoxSimMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size @@ -154,7 +155,7 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ }) class WithSimAXIMMIO extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MMIOPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) @@ -168,21 +169,21 @@ class WithSimAXIMMIO extends OverrideHarnessBinder({ }) class WithTieOffInterrupts extends OverrideHarnessBinder({ - (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => { + (system: HasExtInterruptsModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UInt]) => { ports.foreach { _ := 0.U } Nil } }) class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ - (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveSlaveAXI4Port, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { ports.foreach({ p => p := DontCare; p.bits.tieoff() }) Nil } }) class WithSimDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case d: ClockedDMIIO => val dtm_success = WireInit(false.B) @@ -198,7 +199,7 @@ class WithSimDebug extends OverrideHarnessBinder({ }) class WithTiedOffDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case j: JTAGIO => j.TCK := true.B.asClock @@ -224,7 +225,7 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -234,7 +235,7 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ }) class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -245,14 +246,14 @@ class WithSimSerial extends OverrideHarnessBinder({ }) class WithTraceGenSuccess extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { + (system: TraceGenSystemModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } Nil } }) class WithSimDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 4a31e2c0..5259cbb1 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -72,41 +72,33 @@ object GetSystemParameters { } } -class IOBinder(f: (View, View, View) => PartialFunction[Any, Any]) extends Config(f) +class IOBinder[T, S <: Data](composer: (Any => (Seq[Data], Seq[IOCell])) => T => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((t: Any) => { + val upfn = up(IOBinders, site)(tag.runtimeClass.toString) + t match { + case system: T => composer(upfn)(system) + case _ => (Nil, Nil) + } + }) + ) +}) + // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { - t match { - case system: T => - val (ports, cells) = fn(system) - (ports, cells) - case _ => (Nil, Nil) - } - }) - ) -}) +class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => fn) + // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { - t match { - case system: T => - val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) - val h = fn(system) - val ports = r._1 ++ h._1 - val cells = r._2 ++ h._2 - (ports, cells) - case _ => (Nil, Nil) - } - }) - ) +class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => t => { + val r = upfn(t) + val h = fn(t) + (r._1 ++ h._1, r._2 ++ h._2) }) + object BoreHelper { def apply(name: String, source: Clock): Clock = { val clock_io = IO(Output(Clock())).suggestName(name) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 2faff565..64b889e3 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -44,7 +44,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) } } diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 444c7b33..2fa49fc3 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -66,7 +66,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -77,7 +77,7 @@ class WithSerialBridge extends OverrideHarnessBinder({ }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: FireSim, ports: Seq[ClockedIO[NICIOvonly]]) => { val p: Parameters = GetSystemParameters(system) ports.map { n => NICBridge(n.clock, n.bits)(p) } Nil @@ -85,12 +85,12 @@ class WithNICBridge extends OverrideHarnessBinder({ }) class WithUARTBridge extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => + (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: FireSim, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) } Nil @@ -98,7 +98,7 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({ }) class WithFASEDBridge extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedIO[AXI4Bundle]]) => { implicit val p: Parameters = GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) => val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, @@ -118,20 +118,20 @@ class WithFASEDBridge extends OverrideHarnessBinder({ }) class WithTracerVBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) } Nil } }) class WithDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => + (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil }) class WithTraceGenBridge extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => + (system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) => ports.map { p => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil }) From 5bbd8654470a004c1f06cb7abd5f9060b64e24b3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 13 Oct 2020 16:18:00 -0700 Subject: [PATCH 256/457] Add MMC Device section to the DTS --- .gitmodules | 2 +- fpga/src/main/scala/vcu118/Platform.scala | 12 ++++++++++-- generators/sifive-blocks | 2 +- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index ea3cb2c7..f406a5c2 100644 --- a/.gitmodules +++ b/.gitmodules @@ -21,7 +21,7 @@ url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks - url = https://github.com/sifive/sifive-blocks.git + url = https://github.com/abejgonzalez/sifive-blocks.git [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index bdacdf42..342f7328 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -3,7 +3,7 @@ package chipyard.fpga.vcu118 import chisel3._ import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyScope, InModuleBody, BundleBridgeSource, ValName} +import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.tilelink.{TLBundle} @@ -23,10 +23,18 @@ trait HasVCU118PlatformIO { val io_tl_mem: HeterogeneousBag[TLBundle] } -class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope { +class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope with BindingScope { val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") + // add MMC to the DTS + lazySystem match { case lsys: HasPeripherySPI => + val mmcDev = new MMCDevice(lsys.tlspi.head.device, 1) + ResourceBinding { + Resource(mmcDev, "reg").bind(ResourceAddress(0)) + } + } + override lazy val module = new VCU118PlatformModule(this) } diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c240e629..413e0a88 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c240e629e2fc111cbb12e4fe707be898b5204984 +Subproject commit 413e0a88a4e48b1966b9444d613a7f3a776e65aa From 211c33f996dd39aeba923b1373c016ee8642f24d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 14 Oct 2020 14:42:45 -0700 Subject: [PATCH 257/457] Address comments in #690 --- .../src/main/scala/ConfigFragments.scala | 47 +++++++++++++- .../src/main/scala/CustomBusTopologies.scala | 62 ++++--------------- .../chipyard/src/main/scala/IOBinders.scala | 7 ++- .../main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 5 +- .../firechip/src/main/scala/FireSim.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 14 ++--- generators/testchipip | 2 +- 8 files changed, 74 insertions(+), 67 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index d7becac6..e66dfb4a 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -5,13 +5,13 @@ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Field, Parameters, Config} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy.{LazyModule, ValName} +import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.tilelink.{BootROMLocated} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.groundtest.{GroundTestSubsystem} import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} -import freechips.rocketchip.util.{AsyncResetReg} +import freechips.rocketchip.util.{AsyncResetReg, Symmetric} import freechips.rocketchip.prci._ import testchipip._ @@ -172,3 +172,46 @@ class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble }) +/** + * Mixins to specify crossing types between the 5 traditional TL buses + * + * Note: these presuppose the legacy connections between buses and set + * parameters in SubsystemCrossingParams; they may not be resuable in custom + * topologies (but you can specify the desired crossings in your topology). + * + * @param xType The clock crossing type + * + */ + +class WithSbusToMbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SbusToMbusXTypeKey => xType +}) +class WithSbusToCbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SbusToCbusXTypeKey => xType +}) +class WithCbusToPbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case CbusToPbusXTypeKey => xType +}) +class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case FbusToSbusXTypeKey => xType +}) + +/** + * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way + * up the diplomatic graph to the clock sources. + */ +class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case SystemBusKey => up(SystemBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case ControlBusKey => up(ControlBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) + +class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) +class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing()) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index 5dbcfe1d..c1c09285 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -16,12 +16,14 @@ import freechips.rocketchip.subsystem._ /** * Keys that serve as a means to define crossing types from a Parameters instance */ -case object SubsystemCrossingParamsKey extends Field[SubsystemCrossingParams](SubsystemCrossingParams()) -case object MemoryBusCrossingTypeKey extends Field[ClockCrossingType](NoCrossing) +case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing) +case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing) +case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) +case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) // Biancolin: This, modified from Henry's email /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ -case class CoherentBusTopologyParams( +case class CoherentMulticlockBusTopologyParams( sbus: SystemBusParams, // TODO remove this after better width propagation mbus: MemoryBusParams, l2: BankedL2Params, @@ -41,60 +43,20 @@ case class CoherentBusTopologyParams( // For subsystem/Configs.scala -class WithCoherentBusTopology extends Config((site, here, up) => { +class WithMulticlockCoherentBusTopology extends Config((site, here, up) => { case TLNetworkTopologyLocated(InSubsystem) => List( JustOneBusTopologyParams(sbus = site(SystemBusKey)), HierarchicalBusTopologyParams( pbus = site(PeripheryBusKey), fbus = site(FrontBusKey), cbus = site(ControlBusKey), - xTypes = SubsystemCrossingParams()), - CoherentBusTopologyParams( + xTypes = SubsystemCrossingParams( + sbusToCbusXType = site(SbusToCbusXTypeKey), + cbusToPbusXType = site(CbusToPbusXTypeKey), + fbusToSbusXType = site(FbusToSbusXTypeKey))), + CoherentMulticlockBusTopologyParams( sbus = site(SystemBusKey), mbus = site(MemoryBusKey), l2 = site(BankedL2Key), - sbusToMbusXType = site(MemoryBusCrossingTypeKey))) + sbusToMbusXType = site(SbusToMbusXTypeKey))) }) - -/** - * Mixins to specify crossing types between the 5 traditional TL buses - * - * Note: these presuppose the legacy connections between buses and set - * parameters in SubsystemCrossingParams; they may not be resuable in custom - * topologies (but you can specify the desired crossings in your topology). - * - * @param xType The clock crossing type - * - */ -class WithMemoryBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case MemoryBusCrossingTypeKey => xType -}) - -class WithFrontBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) - .copy(fbusToSbusXType = xType) -}) - -class WithControlBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) - .copy(sbusToCbusXType = xType) -}) - -class WithPeripheryBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) - .copy(cbusToPbusXType = xType) -}) - -/** - * Mixins to set the dtsFrequency field of BusParams -- these will percolate it'st way - * through the diplomatic clock graph to the clock sources. - */ -class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) -}) -class WithMemoryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(freq)) -}) - -class WithRationalMemoryBusCrossing extends WithMemoryBusCrossingType(RationalCrossing(Symmetric)) -class WithAsynchrousMemoryBusCrossing extends WithMemoryBusCrossingType(AsynchronousCrossing()) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1ba6c0a9..8537b418 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -112,6 +112,8 @@ object BoreHelper { val (io, wire) = source match { case c: Clock => val wire = Wire(Clock()) + // Provide a dummy assignment to prevent FIRRTL invalid assignment + // errors prior to running the wiring pass wire := false.B.asClock (IO(Output(Clock())), wire) case r: Reset => @@ -269,8 +271,9 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({ val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) => val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") p.bits <> m - p.clock := BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) - p.reset := BoreHelper("axi4_mem_reset", system.asInstanceOf[BaseSubsystem].mbus.module.reset) + val mbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS) + p.clock := BoreHelper("axi4_mem_clock", mbus.module.clock) + p.reset := BoreHelper("axi4_mem_reset", mbus.module.reset) p }) (ports, Nil) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index c4b1c9cf..301c03d7 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -49,6 +49,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new chipyard.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e89727f1..a056ec32 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -178,8 +178,9 @@ class DividedClockRocketConfig extends Config( new chipyard.config.WithTileFrequency(200.0) ++ new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.WithMemoryBusFrequency(50 * 1000 * 1000) ++ - new chipyard.WithAsynchrousMemoryBusCrossing ++ + new chipyard.config.WithMemoryBusFrequency(50.0) ++ + new chipyard.config.WithAsynchrousMemoryBusCrossing ++ + new testchipip.WithAsynchronousSerialSlaveCrossing ++ new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index cfca74f8..15defa66 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -96,7 +96,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node (chiptop.implicitClockSinkNode := ClockGroup() := aggregator) - (systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator) + (systemAsyncClockGroup :*= ClockGroupNamePrefixer() :*= aggregator) val inputClockSource = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 6ff5065f..ee231419 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -37,10 +37,6 @@ class WithBootROM extends Config((site, here, up) => { } }) -class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) -}) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) @@ -72,13 +68,15 @@ class WithFireSimConfigTweaks extends Config( new WithBootROM ++ // Optional*: Removing this will require adjusting the UART baud rate and // potential target-software changes to properly capture UART output - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - // Optional: Removing these two configs will result in the FASED timing model running + new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + // Optional: These three configs put the DRAM memory system in it's own clock domian. + // Removing the first config will result in the FASED timing model running // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. // 1 GHz matches the FASED default, using some other frequency will require // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. - new chipyard.config.WithMemoryBusFrequency(1000 * 1000 * 1000) ++ + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new chipyard.config.WithAsynchrousMemoryBusCrossing ++ + new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Required: Existing FAME-1 transform cannot handle black-box clock gates new WithoutClockGating ++ // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) @@ -133,7 +131,7 @@ class FireSimSmallSystemConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ + new chipyard.WithPeripheryBusFrequency(3200.0) ++ new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ diff --git a/generators/testchipip b/generators/testchipip index b3987a3a..51240a9a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b3987a3a784c7175c81aa58016fb3e2df58924c2 +Subproject commit 51240a9a892e871a20f3038ea6bc4293318d73db From 5f488bc0688d0f16edf551412ac0b4087bcb8110 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 14 Oct 2020 14:44:48 -0700 Subject: [PATCH 258/457] Bump FireSim for multiclock FAME1 xform fix --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 801baeb9..64b55aff 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 801baeb901c207beb0511311e09ae10e0dbb8b5f +Subproject commit 64b55aff3997d4cee4494eef72c2f1a15b3002b2 From dda7622c29c1bd00abdb74bcd7251915886ed323 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 14:49:22 -0700 Subject: [PATCH 259/457] temp commit --- fpga/src/main/scala/arty/TestHarness.scala | 68 +- fpga/src/main/scala/arty/e300/Configs.scala | 144 ++-- .../src/main/scala/arty/e300/DigitalTop.scala | 46 +- fpga/src/main/scala/arty/e300/IOBinders.scala | 730 +++++++++--------- fpga/src/main/scala/vcu118/Configs.scala | 28 +- fpga/src/main/scala/vcu118/Platform.scala | 81 -- fpga/src/main/scala/vcu118/TestHarness.scala | 130 +--- .../chipyard/src/main/scala/ChipTop.scala | 4 +- 8 files changed, 529 insertions(+), 702 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/Platform.scala diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 919e5c99..6571f3d6 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -1,34 +1,34 @@ -package chipyard.fpga.arty - -import chisel3._ -import chisel3.experimental.{Analog} - -import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} - -import chipyard.{BuildTop, HasHarnessSignalReferences} - -class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { - - val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") - - // turn IO clock into Reset type - val hReset = Wire(Reset()) - hReset := ck_rst - - // default to 32MHz clock - withClockAndReset(clock_32MHz, hReset) { - val dut = Module(ldut.module) - } - - val harnessClock = clock_32MHz - val harnessReset = hReset - val success = false.B - val dutReset = hReset - - // must be after HasHarnessSignalReferences assignments - ldut.harnessFunctions.foreach(_(this)) -} - +//package chipyard.fpga.arty +// +//import chisel3._ +//import chisel3.experimental.{Analog} +// +//import freechips.rocketchip.diplomacy.{LazyModule} +//import freechips.rocketchip.config.{Parameters} +// +//import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +// +//import chipyard.{BuildTop, HasHarnessSignalReferences} +// +//class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { +// +// val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") +// +// // turn IO clock into Reset type +// val hReset = Wire(Reset()) +// hReset := ck_rst +// +// // default to 32MHz clock +// withClockAndReset(clock_32MHz, hReset) { +// val dut = Module(ldut.module) +// } +// +// val harnessClock = clock_32MHz +// val harnessReset = hReset +// val success = false.B +// val dutReset = hReset +// +// // must be after HasHarnessSignalReferences assignments +// ldut.harnessFunctions.foreach(_(this)) +//} +// diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/e300/Configs.scala index dd9213fc..9e04d8df 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -1,72 +1,72 @@ -// See LICENSE for license details. -package chipyard.fpga.arty.e300 - -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} -import freechips.rocketchip.system._ -import freechips.rocketchip.tile._ - -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ - -import chipyard.{BuildSystem} - -class E300DevKitExtra extends Config((site, here, up) => { - case PeripheryGPIOKey => List( - GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) - case PeripheryPWMKey => List( - PWMParams(address = 0x10015000, cmpWidth = 8), - PWMParams(address = 0x10025000, cmpWidth = 16), - PWMParams(address = 0x10035000, cmpWidth = 16)) - case PeripherySPIKey => List( - SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), - SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) - case PeripherySPIFlashKey => List( - SPIFlashParams( - fAddress = 0x20000000, - rAddress = 0x10014000, - defaultSampleDel = 3)) - case PeripheryUARTKey => List( - UARTParams(address = 0x10013000), - UARTParams(address = 0x10023000)) - case PeripheryI2CKey => List( - I2CParams(address = 0x10016000)) - case PeripheryMockAONKey => - MockAONParams(address = 0x10000000) - case DTSTimebase => BigInt(32768) - case JtagDTMKey => new JtagDTMConfig ( - idcodeVersion = 2, - idcodePartNum = 0x000, - idcodeManufId = 0x489, - debugIdleCycles = 5) -}) - -class WithE300System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) -}) - -class E300ArtyDevKitConfig extends Config( - new WithE300System ++ - new WithE300Connections ++ - new E300DevKitExtra ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) +//// See LICENSE for license details. +//package chipyard.fpga.arty.e300 +// +//import freechips.rocketchip.config._ +//import freechips.rocketchip.subsystem._ +//import freechips.rocketchip.devices.debug._ +//import freechips.rocketchip.devices.tilelink._ +//import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +//import freechips.rocketchip.system._ +//import freechips.rocketchip.tile._ +// +//import sifive.blocks.devices.mockaon._ +//import sifive.blocks.devices.gpio._ +//import sifive.blocks.devices.pwm._ +//import sifive.blocks.devices.spi._ +//import sifive.blocks.devices.uart._ +//import sifive.blocks.devices.i2c._ +// +//import chipyard.{BuildSystem} +// +//class E300DevKitExtra extends Config((site, here, up) => { +// case PeripheryGPIOKey => List( +// GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) +// case PeripheryPWMKey => List( +// PWMParams(address = 0x10015000, cmpWidth = 8), +// PWMParams(address = 0x10025000, cmpWidth = 16), +// PWMParams(address = 0x10035000, cmpWidth = 16)) +// case PeripherySPIKey => List( +// SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), +// SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) +// case PeripherySPIFlashKey => List( +// SPIFlashParams( +// fAddress = 0x20000000, +// rAddress = 0x10014000, +// defaultSampleDel = 3)) +// case PeripheryUARTKey => List( +// UARTParams(address = 0x10013000), +// UARTParams(address = 0x10023000)) +// case PeripheryI2CKey => List( +// I2CParams(address = 0x10016000)) +// case PeripheryMockAONKey => +// MockAONParams(address = 0x10000000) +// case DTSTimebase => BigInt(32768) +// case JtagDTMKey => new JtagDTMConfig ( +// idcodeVersion = 2, +// idcodePartNum = 0x000, +// idcodeManufId = 0x489, +// debugIdleCycles = 5) +//}) +// +//class WithE300System extends Config((site, here, up) => { +// case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) +//}) +// +//class E300ArtyDevKitConfig extends Config( +// new WithE300System ++ +// new WithE300Connections ++ +// new E300DevKitExtra ++ +// new chipyard.config.WithBootROM ++ +// new chipyard.config.WithL2TLBs(1024) ++ +// new freechips.rocketchip.subsystem.With1TinyCore ++ +// new freechips.rocketchip.subsystem.WithNBanks(0) ++ +// new freechips.rocketchip.subsystem.WithNoMemPort ++ +// new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ +// new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ +// new freechips.rocketchip.subsystem.WithJtagDTM ++ +// new freechips.rocketchip.subsystem.WithNoMMIOPort ++ +// new freechips.rocketchip.subsystem.WithNoSlavePort ++ +// new freechips.rocketchip.subsystem.WithInclusiveCache ++ +// new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ +// new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ +// new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala index 1bda2680..45018c00 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -1,23 +1,23 @@ -package chipyard.fpga.arty.e300 - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// E300 DigitalTop -// ------------------------------------ - -class E300DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.mockaon.HasPeripheryMockAON -{ - override lazy val module = new E300DigitalTopModule(this) -} - -class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp +//package chipyard.fpga.arty.e300 +// +//import chisel3._ +// +//import freechips.rocketchip.subsystem._ +//import freechips.rocketchip.system._ +//import freechips.rocketchip.config.Parameters +//import freechips.rocketchip.devices.tilelink._ +// +//import chipyard.{DigitalTop, DigitalTopModule} +// +//// ------------------------------------ +//// E300 DigitalTop +//// ------------------------------------ +// +//class E300DigitalTop(implicit p: Parameters) extends DigitalTop +// with sifive.blocks.devices.mockaon.HasPeripheryMockAON +//{ +// override lazy val module = new E300DigitalTopModule(this) +//} +// +//class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) +// with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 8d866619..82da669c 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -1,365 +1,365 @@ -package chipyard.fpga.arty.e300 - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} - -class WithE300Connections extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryDebugModuleImp - with HasPeripheryPWMModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp - with HasPeripheryI2CModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // E300DigitalTop <-> ChipTop connections - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - - object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } - } - - val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") - val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") - val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") - val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") - val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = system.aon.rsts.corerst - // Add in debug-controlled reset. - system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) - Debug.connectDebugClockAndReset(system.debug, system.clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = system.uart - val sys_pwm = system.pwm - val sys_spi = system.spi - val sys_i2c = system.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- system.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- system.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = system.gpio(0).iof_0.get - val iof_1 = system.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io_gpio, system.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) - - // JTAG Debug Interface - val sjtag = system.debug.get.systemjtag.get - JTAGPinsFromPort(io_jtag, sjtag.jtag) - sjtag.reset := io_jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io_ndreset := system.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - io_aon <> system.aon.pins - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // Harness Function (ArtyHarness <-> ChipTop) - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - val harnessFn = (baseTh: HasHarnessSignalReferences) => { - baseTh match { case th: ArtyShell => - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = chisel3.util.Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - withClockAndReset(th.clock_32MHz, th.ck_rst) { - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(th.qspi_sck, io_qspi.sck) - IOBUF(th.qspi_cs, io_qspi.cs(0)) - - IOBUF(th.qspi_dq(0), io_qspi.dq(0)) - IOBUF(th.qspi_dq(1), io_qspi.dq(1)) - IOBUF(th.qspi_dq(2), io_qspi.dq(2)) - IOBUF(th.qspi_dq(3), io_qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - - IOBUF(th.jd_5, io_jtag.TMS) - PULLUP(th.jd_5) - - IOBUF(th.jd_4, io_jtag.TDI) - PULLUP(th.jd_4) - - IOBUF(th.jd_0, io_jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) - io_jtag_reset := jtag_power_on_reset - - // debug reset - th.dut_ndreset := io_ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to th.ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := io_gpio.pins(16).o.oval - iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, th.uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(th.sw_3) - io_gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & io_gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) - - IOBUF(th.uart_rxd_out, io_gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(th.ck_io(2), io_gpio.pins(18)) - IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) - IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) - IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) - IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) - IOBUF(th.ck_io(7), io_gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) - IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) - IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO - IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK - - io_gpio.pins(6).i.ival := 0.U - io_gpio.pins(7).i.ival := 0.U - io_gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) - IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) - IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(th.led0_r, io_gpio.pins(1)) - IOBUF(th.led0_g, io_gpio.pins(2)) - IOBUF(th.led0_b, io_gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(th.led1_r, io_gpio.pins(19)) - IOBUF(th.led1_g, io_gpio.pins(21)) - IOBUF(th.led1_b, io_gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(th.led2_r, io_gpio.pins(11)) - IOBUF(th.led2_g, io_gpio.pins(12)) - IOBUF(th.led2_b, io_gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(th.btn_0, io_gpio.pins(15)) - IOBUF(th.btn_1, io_gpio.pins(30)) - IOBUF(th.btn_2, io_gpio.pins(31)) - - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe - attach(th.btn_3, iobuf_btn_3.io.IO) - io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX - IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(th.ck_ss, io_gpio.pins(26)) - IOBUF(th.ck_mosi, io_gpio.pins(27)) - IOBUF(th.ck_miso, io_gpio.pins(28)) - IOBUF(th.ck_sck, io_gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(th.led_0, th.ck_rst) - IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) - IOBUF(th.led_3, io_gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - io_aon.erst_n.i.ival := ~th.reset_periph - io_aon.lfextclk.i.ival := slow_clock - io_aon.pmu.vddpaden.i.ival := 1.U - } - - Nil - } - } - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - +//package chipyard.fpga.arty.e300 +// +//import chisel3._ +//import chisel3.experimental.{attach, IO} +// +//import freechips.rocketchip.util._ +//import freechips.rocketchip.devices.debug._ +//import freechips.rocketchip.subsystem.{NExtTopInterrupts} +// +//import sifive.blocks.devices.gpio._ +//import sifive.blocks.devices.uart._ +//import sifive.blocks.devices.spi._ +//import sifive.blocks.devices.pwm._ +//import sifive.blocks.devices.i2c._ +//import sifive.blocks.devices.mockaon._ +//import sifive.blocks.devices.jtag._ +//import sifive.blocks.devices.pinctrl._ +// +//import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +//import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} +// +//import chipsalliance.rocketchip.config._ +// +//import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} +//import chipyard.{HasHarnessSignalReferences} +// +//class WithE300Connections extends OverrideIOBinder({ +// (system: HasPeripheryGPIOModuleImp +// with HasPeripheryUARTModuleImp +// with HasPeripherySPIModuleImp +// with HasPeripheryDebugModuleImp +// with HasPeripheryPWMModuleImp +// with HasPeripherySPIFlashModuleImp +// with HasPeripheryMockAONModuleImp +// with HasPeripheryI2CModuleImp) => { +// +// implicit val p: Parameters = GetSystemParameters(system) +// +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// // E300DigitalTop <-> ChipTop connections +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// +// object PinGen { +// def apply(): BasePin = { +// val pin = new BasePin() +// pin +// } +// } +// +// val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") +// val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") +// val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") +// val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") +// val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") +// val io_ndreset = IO(Output(Bool())).suggestName("ndreset") +// +// // This needs to be de-asserted synchronously to the coreClk. +// val async_corerst = system.aon.rsts.corerst +// // Add in debug-controlled reset. +// system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) +// Debug.connectDebugClockAndReset(system.debug, system.clock) +// +// //----------------------------------------------------------------------- +// // Check for unsupported rocket-chip connections +// //----------------------------------------------------------------------- +// +// require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); +// +// //----------------------------------------------------------------------- +// // Build GPIO Pin Mux +// //----------------------------------------------------------------------- +// // Pin Mux for UART, SPI, PWM +// // First convert the System outputs into "IOF" using the respective *GPIOPort +// // converters. +// +// val sys_uart = system.uart +// val sys_pwm = system.pwm +// val sys_spi = system.spi +// val sys_i2c = system.i2c +// +// val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} +// val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} +// val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} +// val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} +// +// (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } +// (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// +// //----------------------------------------------------------------------- +// // Default Pin connections before attaching pinmux +// +// for (iof_0 <- system.gpio(0).iof_0.get) { +// iof_0.default() +// } +// +// for (iof_1 <- system.gpio(0).iof_1.get) { +// iof_1.default() +// } +// +// //----------------------------------------------------------------------- +// +// val iof_0 = system.gpio(0).iof_0.get +// val iof_1 = system.gpio(0).iof_1.get +// +// // SPI1 (0 is the dedicated) +// BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) +// BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) +// BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) +// BasePinToIOF(spi_pins(0).sck, iof_0(5)) +// BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) +// BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) +// BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) +// BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) +// BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) +// +// // SPI2 +// BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) +// BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) +// BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) +// BasePinToIOF(spi_pins(1).sck, iof_0(29)) +// BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) +// BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) +// +// // I2C +// if (p(PeripheryI2CKey).length == 1) { +// BasePinToIOF(i2c_pins(0).sda, iof_0(12)) +// BasePinToIOF(i2c_pins(0).scl, iof_0(13)) +// } +// +// // UART0 +// BasePinToIOF(uart_pins(0).rxd, iof_0(16)) +// BasePinToIOF(uart_pins(0).txd, iof_0(17)) +// +// // UART1 +// BasePinToIOF(uart_pins(1).rxd, iof_0(24)) +// BasePinToIOF(uart_pins(1).txd, iof_0(25)) +// +// //PWM +// BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) +// BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) +// BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) +// BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) +// +// BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) +// BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) +// BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) +// BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) +// +// BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) +// BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) +// BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) +// BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) +// +// //----------------------------------------------------------------------- +// // Drive actual Pads +// //----------------------------------------------------------------------- +// +// // Result of Pin Mux +// GPIOPinsFromPort(io_gpio, system.gpio(0)) +// +// // Dedicated SPI Pads +// SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) +// +// // JTAG Debug Interface +// val sjtag = system.debug.get.systemjtag.get +// JTAGPinsFromPort(io_jtag, sjtag.jtag) +// sjtag.reset := io_jtag_reset +// sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) +// +// io_ndreset := system.debug.get.ndreset +// +// // AON Pads -- direct connection is OK because +// // EnhancedPin is hard-coded in MockAONPads +// // and thus there is no .fromPort method. +// io_aon <> system.aon.pins +// +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// // Harness Function (ArtyHarness <-> ChipTop) +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// val harnessFn = (baseTh: HasHarnessSignalReferences) => { +// baseTh match { case th: ArtyShell => +// +// //----------------------------------------------------------------------- +// // Clock divider +// //----------------------------------------------------------------------- +// val slow_clock = Wire(Bool()) +// +// // Divide clock by 256, used to generate 32.768 kHz clock for AON block +// withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { +// val clockToggleReg = RegInit(false.B) +// val (_, slowTick) = chisel3.util.Counter(true.B, 256) +// when (slowTick) {clockToggleReg := ~clockToggleReg} +// slow_clock := clockToggleReg +// } +// +// //----------------------------------------------------------------------- +// // DUT +// //----------------------------------------------------------------------- +// withClockAndReset(th.clock_32MHz, th.ck_rst) { +// +// //--------------------------------------------------------------------- +// // SPI flash IOBUFs +// //--------------------------------------------------------------------- +// +// IOBUF(th.qspi_sck, io_qspi.sck) +// IOBUF(th.qspi_cs, io_qspi.cs(0)) +// +// IOBUF(th.qspi_dq(0), io_qspi.dq(0)) +// IOBUF(th.qspi_dq(1), io_qspi.dq(1)) +// IOBUF(th.qspi_dq(2), io_qspi.dq(2)) +// IOBUF(th.qspi_dq(3), io_qspi.dq(3)) +// +// //--------------------------------------------------------------------- +// // JTAG IOBUFs +// //--------------------------------------------------------------------- +// +// io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt +// +// IOBUF(th.jd_5, io_jtag.TMS) +// PULLUP(th.jd_5) +// +// IOBUF(th.jd_4, io_jtag.TDI) +// PULLUP(th.jd_4) +// +// IOBUF(th.jd_0, io_jtag.TDO) +// +// // mimic putting a pullup on this line (part of reset vote) +// th.SRST_n := IOBUF(th.jd_6) +// PULLUP(th.jd_6) +// +// // jtag reset +// val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) +// io_jtag_reset := jtag_power_on_reset +// +// // debug reset +// th.dut_ndreset := io_ndreset +// +// //--------------------------------------------------------------------- +// // Assignment to package pins +// //--------------------------------------------------------------------- +// // Pins IO0-IO13 +// // +// // FTDI UART TX/RX are not connected to th.ck_io[0,1] +// // the way they are on Arduino boards. We copy outgoing +// // data to both places, switch 3 (sw[3]) determines whether +// // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) +// +// val iobuf_ck0 = Module(new IOBUF()) +// iobuf_ck0.io.I := io_gpio.pins(16).o.oval +// iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe +// attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX +// +// val iobuf_uart_txd = Module(new IOBUF()) +// iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval +// iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe +// attach(iobuf_uart_txd.io.IO, th.uart_txd_in) +// +// // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] +// val sw_3_in = IOBUF(th.sw_3) +// io_gpio.pins(16).i.ival := Mux(sw_3_in, +// iobuf_ck0.io.O & io_gpio.pins(16).o.ie, +// iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) +// +// IOBUF(th.uart_rxd_out, io_gpio.pins(17)) +// +// // Shield header row 0: PD2-PD7 +// IOBUF(th.ck_io(2), io_gpio.pins(18)) +// IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) +// IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) +// IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) +// IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) +// IOBUF(th.ck_io(7), io_gpio.pins(23)) +// +// // Header row 1: PB0-PB5 +// IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) +// IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) +// IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) +// IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) +// IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO +// IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK +// +// io_gpio.pins(6).i.ival := 0.U +// io_gpio.pins(7).i.ival := 0.U +// io_gpio.pins(8).i.ival := 0.U +// +// // Header row 3: A0-A5 (we don't support using them as analog inputs) +// // just treat them as regular digital GPIOs +// IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) +// IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) +// IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) +// IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA +// IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL +// +// // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty +// // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active +// IOBUF(th.led0_r, io_gpio.pins(1)) +// IOBUF(th.led0_g, io_gpio.pins(2)) +// IOBUF(th.led0_b, io_gpio.pins(3)) +// +// // Note that this is the one which is actually connected on the HiFive/Crazy88 +// // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active +// IOBUF(th.led1_r, io_gpio.pins(19)) +// IOBUF(th.led1_g, io_gpio.pins(21)) +// IOBUF(th.led1_b, io_gpio.pins(22)) +// +// // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active +// IOBUF(th.led2_r, io_gpio.pins(11)) +// IOBUF(th.led2_g, io_gpio.pins(12)) +// IOBUF(th.led2_b, io_gpio.pins(13)) +// +// // Only 19 out of 20 shield pins connected to GPIO pins +// // Shield pin A5 (pin 14) left unconnected +// // The buttons are connected to some extra GPIO pins not connected on the +// // HiFive1 board +// IOBUF(th.btn_0, io_gpio.pins(15)) +// IOBUF(th.btn_1, io_gpio.pins(30)) +// IOBUF(th.btn_2, io_gpio.pins(31)) +// +// val iobuf_btn_3 = Module(new IOBUF()) +// iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval +// iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe +// attach(th.btn_3, iobuf_btn_3.io.IO) +// io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie +// +// // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 +// IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX +// IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX +// +// // SPI2 pins mapped to 6 pin ICSP connector (standard on later +// // arduinos) These are connected to some extra GPIO pins not connected +// // on the HiFive1 board +// IOBUF(th.ck_ss, io_gpio.pins(26)) +// IOBUF(th.ck_mosi, io_gpio.pins(27)) +// IOBUF(th.ck_miso, io_gpio.pins(28)) +// IOBUF(th.ck_sck, io_gpio.pins(29)) +// +// // Use the LEDs for some more useful debugging things +// IOBUF(th.led_0, th.ck_rst) +// IOBUF(th.led_1, th.SRST_n) +// IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) +// IOBUF(th.led_3, io_gpio.pins(14)) +// +// //--------------------------------------------------------------------- +// // Unconnected inputs +// //--------------------------------------------------------------------- +// +// io_aon.erst_n.i.ival := ~th.reset_periph +// io_aon.lfextclk.i.ival := slow_clock +// io_aon.pmu.vddpaden.i.ival := 1.U +// } +// +// Nil +// } +// } +// +// Seq((Nil, Nil, Some(harnessFn))) +// } +//}) +// diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ab087afa..feaa0484 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -23,20 +23,18 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} import chipyard.fpga.vcu118.bringup.{BringupGPIOs} -class WithChipyardBuildTop extends Config((site, here, up) => { - case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } -}) +import chipyard.harness._ class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) - case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), - SPIParams(rAddress = BigInt(0x64004000L))) - case VCU118ShellPMOD => "SDIO" - case PeripheryI2CKey => List( - I2CParams(address = BigInt(0x64005000L))) +// case PeripherySPIKey => List( +// SPIParams(rAddress = BigInt(0x64001000L)), +// SPIParams(rAddress = BigInt(0x64004000L))) +// case VCU118ShellPMOD => "SDIO" +// case PeripheryI2CKey => List( +// I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) @@ -72,8 +70,18 @@ class SmallModifications extends Config((site, here, up) => { class FakeBringupConfig extends Config( + new WithBringupUART ++ + //new WithBringupSPI ++ + //new WithBringupI2C ++ + new WithBringupGPIO ++ + new chipyard.iobinders.WithUARTIOCells ++ + //new WithSPICells ++ + //new WithI2CCells ++ + new chipyard.iobinders.WithGPIOCells ++ + //new WithBringupDDR ++ new WithBringupPeripherals ++ - new WithChipyardBuildTop ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala deleted file mode 100644 index 342f7328..00000000 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ /dev/null @@ -1,81 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ -import chisel3.experimental.{Analog, IO, DataMirror} - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import chipyard.{BuildSystem} - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -trait HasVCU118PlatformIO { - val io_uart: Seq[UARTPortIO] - val io_spi: Seq[SPIPortIO] - val io_i2c: Seq[I2CPort] - val io_gpio: Seq[GPIOPortIO] - val io_tl_mem: HeterogeneousBag[TLBundle] -} - -class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope with BindingScope { - - val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") - - // add MMC to the DTS - lazySystem match { case lsys: HasPeripherySPI => - val mmcDev = new MMCDevice(lsys.tlspi.head.device, 1) - ResourceBinding { - Resource(mmcDev, "reg").bind(ResourceAddress(0)) - } - } - - override lazy val module = new VCU118PlatformModule(this) -} - -class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) - with HasVCU118PlatformIO { - - val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => - val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") } - (io_uart_pins_temp zip sys.uart).map { case (io, sysio) => - io <> sysio - } - io_uart_pins_temp - } - - val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp => - val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") } - (io_spi_pins_temp zip sys.spi).map { case (io, sysio) => - io <> sysio - } - io_spi_pins_temp - } - - val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp => - val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") } - (io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) => - io <> sysio - } - io_i2c_pins_temp - } - - val io_gpio = _outer.lazySystem.module match { case sys: HasPeripheryGPIOModuleImp => - val io_gpio_pins_temp = p(PeripheryGPIOKey).zipWithIndex.map { case (p, i) => IO(new GPIOPortIO(p)).suggestName(s"gpio_$i") } - (io_gpio_pins_temp zip sys.gpio).map { case (io, sysio) => - io <> sysio - } - io_gpio_pins_temp - } - - val io_tl_mem = _outer.lazySystem match { case sys: chipyard.CanHaveMasterTLMemPort => - val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](sys.mem_tl)).suggestName("tl_slave") - io_tl_mem_pins_temp <> sys.mem_tl - io_tl_mem_pins_temp - } -} diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 4275f68d..d371aced 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -19,10 +19,12 @@ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} +import chipyard.harness._ +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions} case object DUTFrequencyKey extends Field[Double](100.0) -class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell { +class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell with HasHarnessSignalReferences { def dp = designParameters @@ -58,122 +60,20 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar } } - /*** UART ***/ - require(dp(PeripheryUARTKey).size == 2) + lazy val harnessClock = InModuleBody { + dutClock.in.head._1.clock + }.getWrappedValue + lazy val harnessReset = InModuleBody { + WireInit(dutClock.in.head._1.reset) + }.getWrappedValue + lazy val dutReset = harnessReset + lazy val success = InModuleBody { false.B }.getWrappedValue - // 1st UART goes to the VCU118 dedicated UART - - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) - dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_uart_bb.bundle <> dutMod.io_uart.head + topDesign match { case d: HasTestHarnessFunctions => + InModuleBody { + d.harnessFunctions.foreach(_(this)) } + ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) } - - // 2nd UART goes to the FMC UART - - val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - - val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_uart_bb_2.bundle <> dutMod.io_uart.last - } - } - - /*** SPI ***/ - require(dp(PeripherySPIKey).size == 2) - - // 1st SPI goes to the VCU118 SDIO port - - val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) - val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_spi_bb.bundle <> dutMod.io_spi.head - } - } - - // TODO: No access to the TLSPI node... - //val mmcDev = new MMCDevice(sdio_placed.device, 1) - //ResourceBinding { - // Resource(mmcDev, "reg").bind(ResourceAddress(0)) - //} - - // 2nd SPI goes to the ADI port - - val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - - val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) - val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_spi_bb_2.bundle <> dutMod.io_spi.last - } - } - - // TODO: No access to the TLSPI node... - //val adiDev = new chipyard.fpga.vcu118.bringup.ADISPIDevice(adi_placed.device, 1) - //ResourceBinding { - // Resource(adiDev, "reg").bind(ResourceAddress(0)) - //} - - /*** I2C ***/ - require(dp(PeripheryI2CKey).size == 1) - - val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) - - val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_i2c_bb.bundle <> dutMod.io_i2c.head - } - } - - /*** GPIO ***/ - val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 - val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) - }) - - val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => - placer.place(GPIODesignInput(params, io_gpio_bb(i))) - } - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - (io_gpio_bb zip dutMod.io_gpio).map { case (bb_io, dut_io) => - bb_io.bundle <> dut_io - } - } - } - - /*** Experimental DDR ***/ - - val ddrWrangler = LazyModule(new ResetWrangler) - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) - - // connect 1 mem. channel to the FPGA DDR - val inParams = topDesign match { case td: VCU118Platform => - td.lazySystem match { case lsys: chipyard.CanHaveMasterTLMemPort => - lsys.memTLNode.edges.in(0) - } - } - val ddrClient = TLClientNode(Seq(inParams.master)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - val bundles = ddrClient.out.map(_._1) - val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) - bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } - ddrClientBundle <> dutMod.io_tl_mem - } - } - ddrPlaced.overlayOutput.ddr := ddrClient } diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 1cef2180..b86b6b07 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{ResetCatchAndSync} import chipyard.iobinders._ @@ -23,7 +23,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) * drive clock and reset generation */ -class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions { +class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions with BindingScope { // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) val iocells = ArrayBuffer.empty[IOCell] From 949d60597fb4d930e985cdc4c935683649fe11d4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 14:50:38 -0700 Subject: [PATCH 260/457] Revert "Support evaluation of HarnessBinders in LazyModule context" This reverts commit 9c298eedfe539e05aa409d4b60595f5a0ab2ada1. --- .../src/main/scala/HarnessBinders.scala | 75 +++++++++---------- .../chipyard/src/main/scala/IOBinders.scala | 36 +++++---- .../chipyard/src/main/scala/TestHarness.scala | 2 +- .../src/main/scala/BridgeBinders.scala | 16 ++-- 4 files changed, 68 insertions(+), 61 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 6f7d2dd8..e5cfacfb 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.harness import chisel3._ -import chisel3.experimental.{Analog, BaseModule} +import chisel3.experimental.{Analog} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -33,41 +33,40 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer object ApplyHarnessBinders { - def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters) = { + def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { val pm = portMap.withDefaultValue(Nil) - p(HarnessBinders).map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } } } -class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) extends Config((site, here, up) => { +class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: U => p}) + val pts = ports.collect({case p: S => p}) require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - val upfn = up(HarnessBinders, site)(tag.runtimeClass.toString) - th match { - case th: S => - t match { - case system: T => composer(upfn)(system, th, pts) - case _ => Nil - } + t match { + case system: T => fn(system, th, pts) case _ => Nil } }) ) }) -class OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) - (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) - extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => fn) - -class ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) - (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) - extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => (t, th, p) => upfn(t, th, p) ++ fn(t, th, p)) - +class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { + case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> + ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val pts = ports.collect({case p: S => p}) + require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") + t match { + case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts) + case _ => Nil + } + }) + ) +}) class WithGPIOTiedOff extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Analog]) => { + (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => { ports.foreach { _ <> AnalogConst(0) } Nil } @@ -75,7 +74,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({ // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { UARTAdapter.connect(ports)(system.p) Nil } @@ -83,14 +82,14 @@ class WithUARTAdapter extends OverrideHarnessBinder({ // DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ - (system: HasPeripherySPIFlashModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { + (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p) Nil } }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } Nil @@ -98,7 +97,7 @@ class WithSimBlockDevice extends OverrideHarnessBinder({ }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } Nil @@ -106,7 +105,7 @@ class WithBlockDeviceModel extends OverrideHarnessBinder({ }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => withClockAndReset(n.clock, th.harnessReset) { @@ -118,7 +117,7 @@ class WithLoopbackNIC extends OverrideHarnessBinder({ }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } Nil @@ -126,7 +125,7 @@ class WithSimNetwork extends OverrideHarnessBinder({ }) class WithSimAXIMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) @@ -140,7 +139,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({ }) class WithBlackBoxSimMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size @@ -155,7 +154,7 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ }) class WithSimAXIMMIO extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MMIOPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) @@ -169,21 +168,21 @@ class WithSimAXIMMIO extends OverrideHarnessBinder({ }) class WithTieOffInterrupts extends OverrideHarnessBinder({ - (system: HasExtInterruptsModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UInt]) => { + (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => { ports.foreach { _ := 0.U } Nil } }) class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ - (system: CanHaveSlaveAXI4Port, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { ports.foreach({ p => p := DontCare; p.bits.tieoff() }) Nil } }) class WithSimDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case d: ClockedDMIIO => val dtm_success = WireInit(false.B) @@ -199,7 +198,7 @@ class WithSimDebug extends OverrideHarnessBinder({ }) class WithTiedOffDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case j: JTAGIO => j.TCK := true.B.asClock @@ -225,7 +224,7 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -235,7 +234,7 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ }) class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -246,14 +245,14 @@ class WithSimSerial extends OverrideHarnessBinder({ }) class WithTraceGenSuccess extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Bool]) => { + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } Nil } }) class WithSimDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 5259cbb1..4a31e2c0 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -72,33 +72,41 @@ object GetSystemParameters { } } -class IOBinder[T, S <: Data](composer: (Any => (Seq[Data], Seq[IOCell])) => T => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class IOBinder(f: (View, View, View) => PartialFunction[Any, Any]) extends Config(f) + +// This macro overrides previous matches on some Top mixin. This is useful for +// binders which drive IO, since those typically cannot be composed +class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { - val upfn = up(IOBinders, site)(tag.runtimeClass.toString) t match { - case system: T => composer(upfn)(system) + case system: T => + val (ports, cells) = fn(system) + (ports, cells) case _ => (Nil, Nil) } }) ) }) - -// This macro overrides previous matches on some Top mixin. This is useful for -// binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => fn) - - // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => t => { - val r = upfn(t) - val h = fn(t) - (r._1 ++ h._1, r._2 ++ h._2) +class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((t: Any) => { + t match { + case system: T => + val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) + val h = fn(system) + val ports = r._1 ++ h._1 + val cells = r._2 ++ h._2 + (ports, cells) + case _ => (Nil, Nil) + } + }) + ) }) - object BoreHelper { def apply(name: String, source: Clock): Clock = { val clock_io = IO(Output(Clock())).suggestName(name) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 64b889e3..2faff565 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -44,7 +44,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) } } diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 2fa49fc3..444c7b33 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -66,7 +66,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -77,7 +77,7 @@ class WithSerialBridge extends OverrideHarnessBinder({ }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: FireSim, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { val p: Parameters = GetSystemParameters(system) ports.map { n => NICBridge(n.clock, n.bits)(p) } Nil @@ -85,12 +85,12 @@ class WithNICBridge extends OverrideHarnessBinder({ }) class WithUARTBridge extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: FireSim, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) } Nil @@ -98,7 +98,7 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({ }) class WithFASEDBridge extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { implicit val p: Parameters = GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) => val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, @@ -118,20 +118,20 @@ class WithFASEDBridge extends OverrideHarnessBinder({ }) class WithTracerVBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) } Nil } }) class WithDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil }) class WithTraceGenBridge extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) => + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => ports.map { p => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil }) From 9c8d2948af1c6f82243002b6ae12d10200f4af58 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 14 Oct 2020 15:33:32 -0700 Subject: [PATCH 261/457] [firechip] Fix a broken config --- generators/firechip/src/main/scala/TargetConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index ee231419..6441136f 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithBootROM ++ - new chipyard.WithPeripheryBusFrequency(3200.0) ++ + new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ From dcac9b79dfb222218023372a0a335647466ec310 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 16:15:10 -0700 Subject: [PATCH 262/457] Basic working with UART --- fpga/Makefile | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 6 +- fpga/src/main/scala/vcu118/TestHarness.scala | 116 +++++++++++++++---- 3 files changed, 98 insertions(+), 26 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index f3f6308b..643e0c67 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -26,7 +26,7 @@ CONFIG := FakeBringupConfig CONFIG_PACKAGE := chipyard.fpga.vcu118 GENERATOR_PACKAGE := chipyard TB := none # unused -TOP := VCU118Platform +TOP := ChipTop # setup the board to use BOARD ?= arty diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index feaa0484..efb2c551 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -73,11 +73,11 @@ class FakeBringupConfig extends Config( new WithBringupUART ++ //new WithBringupSPI ++ //new WithBringupI2C ++ - new WithBringupGPIO ++ - new chipyard.iobinders.WithUARTIOCells ++ + //new WithBringupGPIO ++ + new WithUARTIOPassthrough ++ //new WithSPICells ++ //new WithI2CCells ++ - new chipyard.iobinders.WithGPIOCells ++ + //new chipyard.iobinders.WithGPIOCells ++ //new WithBringupDDR ++ new WithBringupPeripherals ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d371aced..ea8d4b0c 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -20,14 +20,31 @@ import sifive.blocks.devices.gpio._ import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} import chipyard.harness._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop} case object DUTFrequencyKey extends Field[Double](100.0) -class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell with HasHarnessSignalReferences { +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { def dp = designParameters + val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO" + val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") + + // Order matters; ddr depends on sys_clock + val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput())) + val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None + val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) + val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput())) + val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) + val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) + val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) + + val topDesign = LazyModule(p(BuildTop)(dp)) + + // place all clocks in the shell + dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } + /*** Connect/Generate clocks ***/ // connect to the PLL that will generate multiple clocks @@ -44,13 +61,13 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL - InModuleBody { - topDesign.module match { case td: LazyModuleImp => { - td.clock := dutClock.in.head._1.clock - td.reset := dutClock.in.head._1.reset - } - } - } + //InModuleBody { + // topDesign.module match { case td: LazyModuleImp => { + // td.clock := dutClock.in.head._1.clock + // td.reset := dutClock.in.head._1.reset + // } + // } + //} // connect ref clock to dummy sink node ref_clock.get() match { @@ -60,20 +77,75 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar } } - lazy val harnessClock = InModuleBody { - dutClock.in.head._1.clock - }.getWrappedValue - lazy val harnessReset = InModuleBody { - WireInit(dutClock.in.head._1.reset) - }.getWrappedValue - lazy val dutReset = harnessReset - lazy val success = InModuleBody { false.B }.getWrappedValue + // extra overlays - topDesign match { case d: HasTestHarnessFunctions => - InModuleBody { - d.harnessFunctions.foreach(_(this)) - } - ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) + /*** UART ***/ + + // 1st UART goes to the VCU118 dedicated UART + + // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design + // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + + // 2nd UART goes to the FMC UART + + val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) + + val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) + dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + + /*** GPIO ***/ + + val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { + val maxGPIOSupport = 32 + val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) + Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) + }) + + val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + placer.place(GPIODesignInput(params, io_gpio_bb(i))) } + + // module implementation + override lazy val module = new VCU118FPGATestHarnessImp(this) } +class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { + + val outer = _outer + + val reset = IO(Input(Bool())) + _outer.xdc.addPackagePin(reset, "L19") + _outer.xdc.addIOStandard(reset, "LVCMOS12") + + val reset_ibuf = Module(new IBUF) + reset_ibuf.io.I := reset + + val sysclk: Clock = _outer.sys_clock.get() match { + case Some(x: SysClockVCU118PlacedOverlay) => x.clock + } + + val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) + _outer.sdc.addAsyncPath(Seq(powerOnReset)) + + val ereset: Bool = _outer.chiplink.get() match { + case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n + case _ => false.B + } + + _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) + + // cy stuff + val harnessClock = _outer.dutClock.in.head._1.clock + val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) + val dutReset = harnessReset + val success = false.B + + // harness binders are non-lazy + _outer.topDesign match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } +} From 7f387a254b25951f9038a93bfab10833bdb6c5ee Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 23:09:49 -0700 Subject: [PATCH 263/457] Working up until the MMC attachment --- fpga/Makefile | 8 +- .../vcu118/{ => bringup}/BringupGPIOs.scala | 0 .../scala/vcu118/{ => bringup}/Configs.scala | 31 +++--- .../vcu118/{ => bringup}/CustomOverlays.scala | 0 .../scala/vcu118/bringup/HarnessBinders.scala | 94 +++++++++++++++++++ .../main/scala/vcu118/bringup/IOBinders.scala | 90 ++++++++++++++++++ .../vcu118/{ => bringup}/TestHarness.scala | 50 ++++++++-- 7 files changed, 248 insertions(+), 25 deletions(-) rename fpga/src/main/scala/vcu118/{ => bringup}/BringupGPIOs.scala (100%) rename fpga/src/main/scala/vcu118/{ => bringup}/Configs.scala (85%) rename fpga/src/main/scala/vcu118/{ => bringup}/CustomOverlays.scala (100%) create mode 100644 fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala create mode 100644 fpga/src/main/scala/vcu118/bringup/IOBinders.scala rename fpga/src/main/scala/vcu118/{ => bringup}/TestHarness.scala (74%) diff --git a/fpga/Makefile b/fpga/Makefile index 643e0c67..e6bc426a 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -19,11 +19,11 @@ include $(base_dir)/variables.mk # default variables to build the arty example SUB_PROJECT := fpga SBT_PROJECT := fpga_platforms -MODEL := VCU118FPGATestHarness -VLOG_MODEL := VCU118FPGATestHarness -MODEL_PACKAGE := chipyard.fpga.vcu118 +MODEL := BringupVCU118FPGATestHarness +VLOG_MODEL := BringupVCU118FPGATestHarness +MODEL_PACKAGE := chipyard.fpga.vcu118.bringup CONFIG := FakeBringupConfig -CONFIG_PACKAGE := chipyard.fpga.vcu118 +CONFIG_PACKAGE := chipyard.fpga.vcu118.bringup GENERATOR_PACKAGE := chipyard TB := none # unused TOP := ChipTop diff --git a/fpga/src/main/scala/vcu118/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala similarity index 100% rename from fpga/src/main/scala/vcu118/BringupGPIOs.scala rename to fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala similarity index 85% rename from fpga/src/main/scala/vcu118/Configs.scala rename to fpga/src/main/scala/vcu118/bringup/Configs.scala index efb2c551..9a34b198 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -1,5 +1,4 @@ -// See LICENSE for license details. -package chipyard.fpga.vcu118 +package chipyard.fpga.vcu118.bringup import math.min @@ -29,12 +28,12 @@ class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) -// case PeripherySPIKey => List( -// SPIParams(rAddress = BigInt(0x64001000L)), -// SPIParams(rAddress = BigInt(0x64004000L))) -// case VCU118ShellPMOD => "SDIO" -// case PeripheryI2CKey => List( -// I2CParams(address = BigInt(0x64005000L))) + case PeripherySPIKey => List( + SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64004000L))) + case VCU118ShellPMOD => "SDIO" + case PeripheryI2CKey => List( + I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) @@ -71,14 +70,16 @@ class SmallModifications extends Config((site, here, up) => { class FakeBringupConfig extends Config( new WithBringupUART ++ - //new WithBringupSPI ++ - //new WithBringupI2C ++ - //new WithBringupGPIO ++ + new WithBringupSPI ++ + new WithBringupI2C ++ + new WithBringupGPIO ++ + new WithBringupDDR ++ new WithUARTIOPassthrough ++ - //new WithSPICells ++ - //new WithI2CCells ++ - //new chipyard.iobinders.WithGPIOCells ++ - //new WithBringupDDR ++ + new WithSPIIOPassthrough ++ + //new WithMMCSPIDTS ++ + new WithI2CIOPassthrough ++ + new WithGPIOIOPassthrough ++ + new WithTLIOPassthrough ++ new WithBringupPeripherals ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala similarity index 100% rename from fpga/src/main/scala/vcu118/CustomOverlays.scala rename to fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala new file mode 100644 index 00000000..efe805cd --- /dev/null +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -0,0 +1,94 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ +import chisel3.experimental.{Analog, IO} + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ + +import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} +import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} +import chipyard.harness._ + +/*** UART ***/ +class WithBringupUART extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 2) + + vcu118th.outer.io_uart_bb.bundle <> ports.head + vcu118th.outer.io_uart_bb_2.bundle <> ports.last + } } + + Nil + } +}) + +/*** SPI ***/ +class WithBringupSPI extends OverrideHarnessBinder({ + (system: HasPeripherySPIModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 2) + + vcu118th.outer.io_spi_bb.bundle <> ports.head + vcu118th.outer.io_spi_bb_2.bundle <> ports.last + } } + + Nil + } +}) + +/*** I2C ***/ +class WithBringupI2C extends OverrideHarnessBinder({ + (system: HasPeripheryI2CModuleImp, th: HasHarnessSignalReferences, ports: Seq[I2CPort]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 1) + + vcu118th.outer.io_i2c_bb.bundle <> ports.head + } } + + Nil + } +}) + +/*** GPIO ***/ +class WithBringupGPIO extends OverrideHarnessBinder({ + (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => + bb_io.bundle <> dut_io + } + } } + + Nil + } +}) + +/*** Experimental DDR ***/ +class WithBringupDDR extends OverrideHarnessBinder({ + (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 1) + + val bundles = vcu118th.outer.ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> ports.head + } } + + Nil + } +}) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala new file mode 100644 index 00000000..d10f5500 --- /dev/null +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -0,0 +1,90 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ +import chisel3.util.experimental.{BoringUtils} +import chisel3.experimental.{Analog, IO, DataMirror} + +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.jtag.{JTAGIO} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} +import freechips.rocketchip.util._ +import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ +import tracegen.{TraceGenSystemModuleImp} + +import barstools.iocell.chisel._ + +import testchipip._ +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} + +import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort} +import chipyard.iobinders.{OverrideIOBinder} + +class WithUARTIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } + (io_uart_pins_temp zip system.uart).map { case (io, sysio) => + io <> sysio + } + (io_uart_pins_temp, Nil) + } +}) + +class WithGPIOIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp) => { + val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") } + (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) => + io <> sysio + } + (io_gpio_pins_temp, Nil) + } +}) + +class WithSPIIOPassthrough extends OverrideIOBinder({ + (system: HasPeripherySPIModuleImp) => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } +}) + +//class WithMMCSPIDTS extends OverrideIOBinder({ +// (system: HasPeripherySPI) => { +// +// val mmcDev = new MMCDevice(system.tlspi.head.device, 1) +// ResourceBinding { +// Resource(mmcDev, "reg").bind(ResourceAddress(0)) +// } +// +// (Nil, Nil) +// } +//}) + +class WithI2CIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryI2CModuleImp) => { + val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } + (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) => + io <> sysio + } + (io_i2c_pins_temp, Nil) + } +}) + +class WithTLIOPassthrough extends OverrideIOBinder({ + (system: CanHaveMasterTLMemPort) => { + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> system.mem_tl + (Seq(io_tl_mem_pins_temp), Nil) + } +}) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala similarity index 74% rename from fpga/src/main/scala/vcu118/TestHarness.scala rename to fpga/src/main/scala/vcu118/bringup/TestHarness.scala index ea8d4b0c..28e42e3c 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.vcu118 +package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{Analog, IO} @@ -18,13 +18,12 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} import chipyard.harness._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} case object DUTFrequencyKey extends Field[Double](100.0) -class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { +class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { def dp = designParameters @@ -81,6 +80,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** UART ***/ + require(dp(PeripheryUARTKey).size == 2) + // 1st UART goes to the VCU118 dedicated UART // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design @@ -95,6 +96,29 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + /*** SPI ***/ + + require(dp(PeripherySPIKey).size == 2) + + // 1st SPI goes to the VCU118 SDIO port + + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) + val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) + + // 2nd SPI goes to the ADI port + + val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) + + val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) + val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) + + /*** I2C ***/ + + val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) + + val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) + dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) + /*** GPIO ***/ val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { @@ -108,11 +132,25 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S placer.place(GPIODesignInput(params, io_gpio_bb(i))) } + /*** DDR ***/ + + val ddrWrangler = LazyModule(new ResetWrangler) + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) + + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + ddrPlaced.overlayOutput.ddr := ddrClient + // module implementation - override lazy val module = new VCU118FPGATestHarnessImp(this) + override lazy val module = new BringupVCU118FPGATestHarnessImp(this) } -class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { +class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { val outer = _outer From 4a317b0cab4c4f15d6240a2a309036e720cc4790 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Thu, 15 Oct 2020 17:07:20 +0000 Subject: [PATCH 264/457] differentiate default config package delimiter --- common.mk | 2 +- .../chipyard/src/main/scala/stage/ChipyardAnnotations.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/common.mk b/common.mk index f8bd4cf4..8ebc262c 100644 --- a/common.mk +++ b/common.mk @@ -110,7 +110,7 @@ generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) --target-dir $(build_dir) \ --name $(long_name) \ --top-module $(MODEL_PACKAGE).$(MODEL) \ - --legacy-configs $(CONFIG_PACKAGE).$(CONFIG)) + --legacy-configs $(CONFIG_PACKAGE):$(CONFIG)) .PHONY: firrtl firrtl: $(FIRRTL_FILE) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala index d75c11a1..5d8b128c 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -12,10 +12,10 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio new ShellOption[String]( longOption = "legacy-configs", toAnnotationSeq = a => { - val split = a.split('.') - val packageName = split.init.mkString(".") + val split = a.split(':') + val packageName = split.head val configs = split.last.split("_") - Seq(new ConfigsAnnotation(configs map { config => s"${packageName}.${config}" } )) + Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } )) }, helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", shortOption = Some("LC") From 2c935b4ad7fff2a0e6a5c2028f8f4511c8b4b5b5 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Thu, 15 Oct 2020 17:07:51 +0000 Subject: [PATCH 265/457] pull firesim mem model config into firesim tweaks --- generators/firechip/src/main/scala/TargetConfigs.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index b70ef647..c7aa556d 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -66,6 +66,8 @@ class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small") // Tweaks that are generally applied to all firesim configs class WithFireSimConfigTweaks extends Config( + // Required: Bake in the default FASED memory model + new WithDefaultMemModel ++ // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset new WithFireSimSimpleClocks ++ // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source From 20d3b9f9ce0a46bd6160cd7f16eb682593bb634e Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Thu, 15 Oct 2020 17:08:06 +0000 Subject: [PATCH 266/457] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 6318184f..b35e8142 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6318184f304315a94b5eb5c670f0eec1a3205f59 +Subproject commit b35e81422c355031ae90b895f4ecb85d6b20af06 From c7a197d79a4273dacc040a2a1c33c2d31dff03c2 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Thu, 15 Oct 2020 17:51:28 +0000 Subject: [PATCH 267/457] docs --- .../FPGA-Accelerated-Simulation.rst | 22 +++++++++++++------ 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 82692643..c46c0fb5 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -46,7 +46,20 @@ and proceed with the rest of the tutorial. Running your Design in FireSim ------------------------------ -Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireSim is simple. We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. +Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireSim is simple, and can be done either throught the traditional configuration system or through FireSim's build recipes scheme. + +A FireSim simulation requires 3 additional config fragments: + +* ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. +* ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. This config fragment is currently included by default within ``WithFireSimConfigTweaks``, so it isn't neccessary to add in separately, but it is required if you choose not to use ``WithFireSimConfigTweaks``. +* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSim documentation for details. + + +The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme. +After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to you custom configuration as if they were listed in a custom Chisel custom config class definition. For example, if you would like to convert the Chipyard LargeBoomConfig to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firsim`` scala package, and therefore there do not need to be prefixed with the full class name, and opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name. + +An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments. +We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. .. literalinclude:: ../../generators/firechip/src/main/scala/TargetConfigs.scala @@ -54,9 +67,4 @@ Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireS :start-after: DOC include start: firesimconfig :end-before: DOC include end: firesimconfig - -Only 3 additional config fragments are needed. - -* ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. -* ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. -* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSim documentation for details. +While this option seems to require the maintainance of additiona configuraiton code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``) From 6479d54f53f5a71ef9fa04c0a8178a1457c766e5 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Thu, 15 Oct 2020 17:53:25 +0000 Subject: [PATCH 268/457] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index b35e8142..b9a9061b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b35e81422c355031ae90b895f4ecb85d6b20af06 +Subproject commit b9a9061b0b23e85daf4d6f3904e10a97680fbb56 From fd4a70dfb64d95e950ac2222c60170d8f3551f45 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Thu, 15 Oct 2020 18:04:31 +0000 Subject: [PATCH 269/457] docs typos --- docs/Simulation/FPGA-Accelerated-Simulation.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index c46c0fb5..40432e51 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -56,7 +56,7 @@ A FireSim simulation requires 3 additional config fragments: The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme. -After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to you custom configuration as if they were listed in a custom Chisel custom config class definition. For example, if you would like to convert the Chipyard LargeBoomConfig to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firsim`` scala package, and therefore there do not need to be prefixed with the full class name, and opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name. +After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package, and therefore there do not need to be prefixed with the full class name, and opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name. An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments. We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. @@ -67,4 +67,4 @@ We are using the same target (top) RTL, and only need to specify a new set of co :start-after: DOC include start: firesimconfig :end-before: DOC include end: firesimconfig -While this option seems to require the maintainance of additiona configuraiton code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``) +While this option seems to require the maintenance of additional configuration code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``) From 74c1c9d7aba6df6157da3719f0247687e2ed4e33 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 15 Oct 2020 10:00:07 -0700 Subject: [PATCH 270/457] Punch out reset in AXI4MMIO IOBinder --- generators/chipyard/src/main/scala/IOBinders.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 8537b418..87480bfc 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -282,10 +282,12 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { - val ports: Seq[ClockedIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") + val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") p.bits <> m - p.clock := BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) + val mbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS) + p.clock := BoreHelper("axi4_mmio_clock", mbus.module.clock) + p.reset := BoreHelper("axi4_mmio_reset", mbus.module.reset) p }) (ports, Nil) From b747116363f98d0b2770071b6a434f9c6b34afa5 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 15 Oct 2020 10:00:53 -0700 Subject: [PATCH 271/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index a8900919..89a2ac93 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a8900919cbc826e8e1610805c4229e31a849ad3c +Subproject commit 89a2ac931eddcff72db47006bf863aa201dad206 From 9ba4918cb863294844a3b16cddede8b4a7d752dd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 15 Oct 2020 11:46:42 -0700 Subject: [PATCH 272/457] Inject MMCDevice into TLSPI Node --- fpga/src/main/scala/vcu118/bringup/Configs.scala | 10 +++++++--- fpga/src/main/scala/vcu118/bringup/IOBinders.scala | 12 ------------ generators/sifive-blocks | 2 +- 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 9a34b198..f0dd91cc 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -6,7 +6,7 @@ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ @@ -20,7 +20,6 @@ import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} -import chipyard.fpga.vcu118.bringup.{BringupGPIOs} import chipyard.harness._ @@ -29,7 +28,12 @@ class WithBringupPeripherals extends Config((site, here, up) => { UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64001000L), + injectFunc = Some((spi: TLSPI) => { + ResourceBinding { + Resource(new MMCDevice(spi.device, 1), "reg").bind(ResourceAddress(0)) + } + })), SPIParams(rAddress = BigInt(0x64004000L))) case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index d10f5500..ece212bb 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -59,18 +59,6 @@ class WithSPIIOPassthrough extends OverrideIOBinder({ } }) -//class WithMMCSPIDTS extends OverrideIOBinder({ -// (system: HasPeripherySPI) => { -// -// val mmcDev = new MMCDevice(system.tlspi.head.device, 1) -// ResourceBinding { -// Resource(mmcDev, "reg").bind(ResourceAddress(0)) -// } -// -// (Nil, Nil) -// } -//}) - class WithI2CIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryI2CModuleImp) => { val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 413e0a88..ed9f63f9 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 413e0a88a4e48b1966b9444d613a7f3a776e65aa +Subproject commit ed9f63f9f5b9209c9e5ef2adfd063d6669691d79 From 84e0bf7338d1802dea6bc4bcd5f7127bcab7ab3f Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Thu, 15 Oct 2020 12:25:39 -0700 Subject: [PATCH 273/457] Don't annotate cores with FAMEModelAnnotations --- generators/firechip/src/main/scala/BridgeBinders.scala | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 760e89c3..110afda8 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -18,7 +18,7 @@ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvon import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} -import midas.targetutils.{FAMEModelAnnotation, MemModelAnnotation, EnableModelMultiThreadingAnnotation} +import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey import tracegen.{TraceGenSystemModuleImp} @@ -161,10 +161,8 @@ class WithFireSimFAME5 extends ComposeIOBinder({ (system: HasTilesModuleImp) => { system.outer.tiles.map { case b: BoomTile => - annotate(FAMEModelAnnotation(b.module)) annotate(EnableModelMultiThreadingAnnotation(b.module)) case r: RocketTile => - annotate(FAMEModelAnnotation(r.module)) annotate(EnableModelMultiThreadingAnnotation(r.module)) } (Nil, Nil) From 6eaac63e1be4035a395f3bf8e6c490794c58fad8 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Fri, 16 Oct 2020 06:34:26 +0000 Subject: [PATCH 274/457] address PR comments --- docs/Simulation/FPGA-Accelerated-Simulation.rst | 8 ++++---- .../src/main/scala/stage/ChipyardAnnotations.scala | 1 + sims/firesim | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 40432e51..86f0eb8b 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -46,17 +46,17 @@ and proceed with the rest of the tutorial. Running your Design in FireSim ------------------------------ -Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireSim is simple, and can be done either throught the traditional configuration system or through FireSim's build recipes scheme. +Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireSim is simple, and can be done either through the traditional configuration system or through FireSim's build-recipes scheme. A FireSim simulation requires 3 additional config fragments: -* ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. -* ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. This config fragment is currently included by default within ``WithFireSimConfigTweaks``, so it isn't neccessary to add in separately, but it is required if you choose not to use ``WithFireSimConfigTweaks``. +* ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. This is composed of multiple smaller config fragments. For example, the removal of clock-gating (using the ``WithoutClockGating`` config fragment) which is required for correct functioning of the compiler. This config fragment also includes other config fragments such as the inclusion of UART in the design, which although may technically be optional,is *strongly* recommended. +* ``WithDefaultMemModel`` provides a default configuration for FASED memory models in the FireSim simulation. See the FireSim documentation for details. This config fragment is currently included by default within ``WithFireSimConfigTweaks``, so it isn't neccessary to add in separately, but it is required if you choose not to use ``WithFireSimConfigTweaks``. * ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSim documentation for details. The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme. -After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package, and therefore there do not need to be prefixed with the full class name, and opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name. +After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name. An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments. We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala index 5d8b128c..b1300031 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -13,6 +13,7 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio longOption = "legacy-configs", toAnnotationSeq = a => { val split = a.split(':') + assert(split.length == 2) val packageName = split.head val configs = split.last.split("_") Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } )) diff --git a/sims/firesim b/sims/firesim index b9a9061b..0e4787a0 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b9a9061b0b23e85daf4d6f3904e10a97680fbb56 +Subproject commit 0e4787a04a3d4a0cade9b0c7070b3d67f6679fea From 8de7aa8d69956f2ddc46b11220f3a8b08a8852ad Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Fri, 16 Oct 2020 18:18:35 +0000 Subject: [PATCH 275/457] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 0e4787a0..f0257a3f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 0e4787a04a3d4a0cade9b0c7070b3d67f6679fea +Subproject commit f0257a3f737a73373d0f589e7d19ef6a0b4b1d32 From 9927231bc42f2405151f67e26396f686f2bfaa46 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 17 Oct 2020 22:47:50 -0700 Subject: [PATCH 276/457] Support lazy-iobinders --- .../chipyard/src/main/scala/ChipTop.scala | 15 +- .../src/main/scala/HarnessBinders.scala | 79 ++--- .../chipyard/src/main/scala/IOBinders.scala | 282 ++++++++++-------- .../chipyard/src/main/scala/TestHarness.scala | 7 +- .../src/main/scala/BridgeBinders.scala | 16 +- .../firechip/src/main/scala/FireSim.scala | 4 +- 6 files changed, 214 insertions(+), 189 deletions(-) diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 1cef2180..e7456d80 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -23,12 +23,10 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) * drive clock and reset generation */ -class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions { - // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) - val iocells = ArrayBuffer.empty[IOCell] - +class ChipTop(implicit p: Parameters) extends LazyModule + with HasTestHarnessFunctions with HasIOBinders { // The system module specified by BuildSystem - val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") + lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") // The implicitClockSinkNode provides the implicit clock and reset for the System val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) @@ -45,13 +43,6 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc val implicit_clock = implicitClockSinkNode.in.head._1.clock val implicit_reset = implicitClockSinkNode.in.head._1.reset - - // Note: IOBinders cannot rely on the implicit clock/reset, as this is a LazyRawModuleImp - val (_ports, _iocells, _portMap) = ApplyIOBinders(lazySystem, p(IOBinders)) - // We ignore _ports for now... - iocells ++= _iocells - portMap ++= _portMap - // Connect the implicit clock/reset, if present lazySystem.module match { case l: LazyModuleImp => { l.clock := implicit_clock diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index e5cfacfb..c5b95f75 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.harness import chisel3._ -import chisel3.experimental.{Analog} +import chisel3.experimental.{Analog, BaseModule} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -31,42 +31,42 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]]().withDefaultValue((t: Any, th: HasHarnessSignalReferences, d: Seq[Data]) => Nil) ) - object ApplyHarnessBinders { - def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { + def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters) = { val pm = portMap.withDefaultValue(Nil) - map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + p(HarnessBinders).map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } } } -class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { +class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: S => p}) + val pts = ports.collect({case p: U => p}) require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - t match { - case system: T => fn(system, th, pts) + val upfn = up(HarnessBinders, site)(tag.runtimeClass.toString) + th match { + case th: S => + t match { + case system: T => composer(upfn)(system, th, pts) + case _ => Nil + } case _ => Nil } }) ) }) -class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { - case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> - ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: S => p}) - require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - t match { - case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts) - case _ => Nil - } - }) - ) -}) +class OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) + (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => fn) + +class ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) + (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => (t, th, p) => upfn(t, th, p) ++ fn(t, th, p)) + class WithGPIOTiedOff extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => { + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Analog]) => { ports.foreach { _ <> AnalogConst(0) } Nil } @@ -74,7 +74,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({ // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { UARTAdapter.connect(ports)(system.p) Nil } @@ -82,14 +82,14 @@ class WithUARTAdapter extends OverrideHarnessBinder({ // DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ - (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { + (system: HasPeripherySPIFlashModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p) Nil } }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } Nil @@ -97,7 +97,7 @@ class WithSimBlockDevice extends OverrideHarnessBinder({ }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } Nil @@ -105,7 +105,7 @@ class WithBlockDeviceModel extends OverrideHarnessBinder({ }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => withClockAndReset(n.clock, th.harnessReset) { @@ -117,7 +117,7 @@ class WithLoopbackNIC extends OverrideHarnessBinder({ }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } Nil @@ -125,7 +125,7 @@ class WithSimNetwork extends OverrideHarnessBinder({ }) class WithSimAXIMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) @@ -139,7 +139,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({ }) class WithBlackBoxSimMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size @@ -154,7 +154,7 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ }) class WithSimAXIMMIO extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MMIOPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) @@ -168,26 +168,27 @@ class WithSimAXIMMIO extends OverrideHarnessBinder({ }) class WithTieOffInterrupts extends OverrideHarnessBinder({ - (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => { + (system: HasExtInterruptsModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UInt]) => { ports.foreach { _ := 0.U } Nil } }) class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ - (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveSlaveAXI4Port, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { ports.foreach({ p => p := DontCare; p.bits.tieoff() }) Nil } }) class WithSimDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebug, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + implicit val p: Parameters = GetSystemParameters(system) ports.map { case d: ClockedDMIIO => val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } - val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success) + val dtm = Module(new SimDTM).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success) case j: JTAGIO => val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } @@ -198,7 +199,7 @@ class WithSimDebug extends OverrideHarnessBinder({ }) class WithTiedOffDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebug, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case j: JTAGIO => j.TCK := true.B.asClock @@ -224,7 +225,7 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -234,7 +235,7 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ }) class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -245,14 +246,14 @@ class WithSimSerial extends OverrideHarnessBinder({ }) class WithTraceGenSuccess extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { + (system: TraceGenSystemModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } Nil } }) class WithSimDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 4a31e2c0..b083b5c0 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -1,17 +1,17 @@ package chipyard.iobinders import chisel3._ -import chisel3.util.experimental.{BoringUtils} import chisel3.experimental.{Analog, IO, DataMirror} import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} +import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.util._ +import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} import sifive.blocks.devices.gpio._ @@ -28,6 +28,12 @@ import chipyard.GlobalResetSchemeKey import scala.reflect.{ClassTag} +object IOBinderTypes { + type IOBinderTuple = (Seq[Data], Seq[IOCell]) + type IOBinderFunction = (Boolean, =>Any) => ModuleValue[IOBinderTuple] +} +import IOBinderTypes._ + // System for instantiating binders based // on the scala type of the Target (_not_ its IO). This avoids needing to // duplicate harnesses (essentially test harnesses) for each target. @@ -40,21 +46,30 @@ import scala.reflect.{ClassTag} // You can add your own binder by adding a new (key, fn) pair, typically by using // the OverrideIOBinder or ComposeIOBinder macros -case object IOBinders extends Field[Map[String, (Any) => (Seq[Data], Seq[IOCell])]]( - Map[String, (Any) => (Seq[Data], Seq[IOCell])]().withDefaultValue((Any) => (Nil, Nil)) +case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]]( + Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil) ) -object ApplyIOBinders { - def apply(sys: LazyModule, map: Map[String, (Any) => (Seq[Data], Seq[IOCell])]): - (Iterable[Data], Iterable[IOCell], Map[String, Seq[Data]]) = { - val lzy = map.map({ case (s,f) => s -> f(sys) }) - val imp = map.map({ case (s,f) => s -> f(sys.module) }) - val unzipped = (lzy.values ++ imp.values).unzip - val ports: Iterable[Data] = unzipped._1.flatten - val cells: Iterable[IOCell] = unzipped._2.flatten - val portMap: Map[String, Seq[Data]] = map.keys.map(k => k -> (lzy(k)._1 ++ imp(k)._1)).toMap - (ports, cells, portMap) - } +abstract trait HasIOBinders { this: LazyModule => + val lazySystem: LazyModule + private val iobinders = p(IOBinders) + // Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the + // context of a LazyRawModuleImp + private val lzy = iobinders.map({ case (s,fns) => s -> fns.map(f => f(true, lazySystem)) }) + private val imp = iobinders.map({ case (s,fns) => s -> fns.map(f => f(false, lazySystem.module)) }) + + private lazy val lzyFlattened: Map[String, IOBinderTuple] = lzy.map({ + case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten) + }) + private lazy val impFlattened: Map[String, IOBinderTuple] = imp.map({ + case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten) + }) + + // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) + lazy val iocells = (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer + + // A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports + lazy val portMap = iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap } // Note: The parameters instance is accessible only through LazyModule @@ -72,52 +87,46 @@ object GetSystemParameters { } } -class IOBinder(f: (View, View, View) => PartialFunction[Any, Any]) extends Config(f) - -// This macro overrides previous matches on some Top mixin. This is useful for -// binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { - t match { - case system: T => - val (ports, cells) = fn(system) - (ports, cells) - case _ => (Nil, Nil) - } - }) - ) +class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString))) }) -// This macro composes with previous matches on some Top mixin. This is useful for -// annotation-like binders, since those can typically be composed -class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { - t match { - case system: T => - val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) - val h = fn(system) - val ports = r._1 ++ h._1 - val cells = r._2 ++ h._2 - (ports, cells) - case _ => (Nil, Nil) - } - }) - ) -}) +class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T]( + up => (if (composes) up else Nil) ++ Seq(((_, t) => { InModuleBody { + t match { + case system: T => fn(system) + case _ => (Nil, Nil) + } + }}): IOBinderFunction) +) -object BoreHelper { - def apply(name: String, source: Clock): Clock = { - val clock_io = IO(Output(Clock())).suggestName(name) - val clock_wire = Wire(Clock()).suggestName(s"chiptop_${name}") - dontTouch(clock_wire) - clock_wire := false.B.asClock // necessary for BoringUtils to work properly - BoringUtils.bore(source, Seq(clock_wire)) - clock_io := clock_wire - clock_io - } -} + +class LazyIOBinder[T](composes: Boolean, fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends IOBinder[T]( + up => (if (composes) up else Nil) ++ Seq(((isLazy, t) => { + val empty = new ModuleValue[IOBinderTuple] { + def getWrappedValue: IOBinderTuple = (Nil, Nil) + } + if (isLazy) { + t match { + case system: T => fn(system) + case _ => empty + } + } else { + empty + } + }): IOBinderFunction) +) + +// The "Override" binders override any previous IOBinders (lazy or concrete) defined on the same trait. +// The "Compose" binders do not override previously defined IOBinders on the same trait +// The default IOBinders evaluate only in the concrete "ModuleImp" phase of elaboration +// The "Lazy" IOBinders evaluate in the LazyModule phase, but can also generate hardware through InModuleBody + +class OverrideIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](false, fn) +class ComposeIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](true, fn) + +class OverrideLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](false, fn) +class ComposeLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](true, fn) case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) @@ -194,55 +203,55 @@ class WithExtInterruptIOCells extends OverrideIOBinder({ }) -class WithDebugIOCells extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { - system.debug.map({ debug => - val p = system.p - val tlbus = system.outer.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere) - val debug_clock = Wire(Clock()).suggestName("debug_clock") - val debug_reset = Wire(Reset()).suggestName("debug_reset") - debug_clock := false.B.asClock // must provide default assignment to avoid firrtl unassigned error - debug_reset := false.B // must provide default assignment to avoid firrtl unassigned error - BoringUtils.bore(tlbus.module.clock, Seq(debug_clock)) - BoringUtils.bore(tlbus.module.reset, Seq(debug_reset)) +class WithDebugIOCells extends OverrideLazyIOBinder({ + (system: HasPeripheryDebug) => { + implicit val p = GetSystemParameters(system) + val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere) + val clockSinkNode = system.debugOpt.map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) + clockSinkNode.map(_ := tlbus.fixedClockNode) + def clockBundle = clockSinkNode.get.in.head._1 - // We never use the PSDIO, so tie it off on-chip - system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } - system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := debug_reset.asBool } } - system.debug.map { d => - // Tie off extTrigger - d.extTrigger.foreach { t => - t.in.req := false.B - t.out.ack := t.out.req + + InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => { + system.debug.map({ debug => + // We never use the PSDIO, so tie it off on-chip + system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } + system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := clockBundle.reset.asBool } } + system.debug.map { d => + // Tie off extTrigger + d.extTrigger.foreach { t => + t.in.req := false.B + t.out.ack := t.out.req + } + // Tie off disableDebug + d.disableDebug.foreach { d => d := false.B } + // Drive JTAG on-chip IOs + d.systemjtag.map { j => + j.reset := clockBundle.reset + j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) + j.version := p(JtagDTMKey).idcodeVersion.U(4.W) + } } - // Tie off disableDebug - d.disableDebug.foreach { d => d := false.B } - // Drive JTAG on-chip IOs - d.systemjtag.map { j => - j.reset := debug_reset - j.mfr_id := system.p(JtagDTMKey).idcodeManufId.U(11.W) - j.part_number := system.p(JtagDTMKey).idcodePartNum.U(16.W) - j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W) + Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock) + + // Add IOCells for the DMI/JTAG/APB ports + val dmiTuple = debug.clockeddmi.map { d => + IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) } - } - Debug.connectDebugClockAndReset(Some(debug), debug_clock)(system.p) - // Add IOCells for the DMI/JTAG/APB ports - val dmiTuple = debug.clockeddmi.map { d => - IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) - } + val jtagTuple = debug.systemjtag.map { j => + IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + } - val jtagTuple = debug.systemjtag.map { j => - IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) - } + val apbTuple = debug.apb.map { a => + IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + } - val apbTuple = debug.apb.map { a => - IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) - } - - val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq - (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq) - }).getOrElse((Nil, Nil)) + val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq + (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq) + }).getOrElse((Nil, Nil)) + }}} } }) @@ -255,39 +264,60 @@ class WithSerialTLIOCells extends OverrideIOBinder({ }) -class WithAXI4MemPunchthrough extends OverrideIOBinder({ +class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveMasterAXI4MemPort) => { - val ports: Seq[ClockedIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") - p.bits <> m - p.clock := BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) - p - }) - (ports, Nil) + implicit val p: Parameters = GetSystemParameters(system) + val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) + clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].mbus.fixedClockNode) + def clockBundle = clockSinkNode.get.in.head._1 + + InModuleBody { + val ports: Seq[ClockedIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") + p.bits <> m + p.clock := clockBundle.clock + p + }) + (ports, Nil) + } } }) -class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ +class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { - val ports: Seq[ClockedIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") - p.bits <> m - p.clock := BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) - p - }) - (ports, Nil) + implicit val p: Parameters = GetSystemParameters(system) + val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) + clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].mbus.fixedClockNode) + def clockBundle = clockSinkNode.get.in.head._1 + + InModuleBody { + val ports: Seq[ClockedIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") + p.bits <> m + p.clock := clockBundle.clock + p + }) + (ports, Nil) + } } }) -class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4Port) => { - val ports: Seq[ClockedIO[AXI4Bundle]] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}") - m <> p.bits - p.clock := BoreHelper("axi4_fbus_clock", system.asInstanceOf[BaseSubsystem].fbus.module.clock) - p - }) - (ports, Nil) +class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({ + (system: CanHaveSlaveAXI4Port) => { + implicit val p: Parameters = GetSystemParameters(system) + val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) + clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].fbus.fixedClockNode) + def clockBundle = clockSinkNode.get.in.head._1 + + InModuleBody { + val ports: Seq[ClockedIO[AXI4Bundle]] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}") + m <> p.bits + p.clock := clockBundle.clock + p + }) + (ports, Nil) + } } }) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 2faff565..9c5c9d2c 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} +import chipyard.iobinders.HasIOBinders // ------------------------------- // Chipyard Test Harness @@ -14,9 +15,7 @@ import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p)) trait HasTestHarnessFunctions { - val lazySystem: LazyModule val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] - val portMap = scala.collection.mutable.Map[String, Seq[Data]]() } trait HasHarnessSignalReferences { @@ -44,7 +43,9 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } + lazyDut match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) } } diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 444c7b33..2fa49fc3 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -66,7 +66,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -77,7 +77,7 @@ class WithSerialBridge extends OverrideHarnessBinder({ }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: FireSim, ports: Seq[ClockedIO[NICIOvonly]]) => { val p: Parameters = GetSystemParameters(system) ports.map { n => NICBridge(n.clock, n.bits)(p) } Nil @@ -85,12 +85,12 @@ class WithNICBridge extends OverrideHarnessBinder({ }) class WithUARTBridge extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => + (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: FireSim, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) } Nil @@ -98,7 +98,7 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({ }) class WithFASEDBridge extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedIO[AXI4Bundle]]) => { implicit val p: Parameters = GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) => val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, @@ -118,20 +118,20 @@ class WithFASEDBridge extends OverrideHarnessBinder({ }) class WithTracerVBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) } Nil } }) class WithDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => + (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil }) class WithTraceGenBridge extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => + (system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) => ports.map { p => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil }) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 90fd473a..70116456 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -160,7 +160,9 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna lazyModule match { case d: HasTestHarnessFunctions => require(d.harnessFunctions.size == 1, "There should only be 1 harness function to connect clock+reset") d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } + lazyModule match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) } NodeIdx.increment() } From 035e2e43158d7cb7aa79600cd1a7450b576dd105 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 17 Oct 2020 22:55:07 -0700 Subject: [PATCH 277/457] Add test for make TOP=DigitalTop --- .circleci/defaults.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 1b41e395..e628de7b 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor" +grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -59,6 +59,7 @@ mapping["chipyard-rocket"]="" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" +mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" From c5e3ad0a016b33ddc8b6685ea3786591988c96ca Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 19 Oct 2020 15:32:48 +0000 Subject: [PATCH 278/457] Bump tcip and fsim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 44649158..1c76c446 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 44649158c0bd0eaf19e82fac3668e5e643beabf7 +Subproject commit 1c76c446dab42b782f8128c3e7e56b4e9ab104d7 From f3d666d2b7675eebbe890b530a9de2a25cdd8588 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 19 Oct 2020 10:16:44 -0700 Subject: [PATCH 279/457] Clarify HarnessBinders ClassTag naming --- generators/chipyard/src/main/scala/HarnessBinders.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index c5b95f75..3cf70f3e 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -38,12 +38,13 @@ object ApplyHarnessBinders { } } -class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) extends Config((site, here, up) => { - case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> +// The ClassTags here are necessary to overcome issues arising from type erasure +class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit systemTag: ClassTag[T], harnessTag: ClassTag[S], portTag: ClassTag[U]) extends Config((site, here, up) => { + case HarnessBinders => up(HarnessBinders, site) + (systemTag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { val pts = ports.collect({case p: U => p}) - require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - val upfn = up(HarnessBinders, site)(tag.runtimeClass.toString) + require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${portTag}") + val upfn = up(HarnessBinders, site)(systemTag.runtimeClass.toString) th match { case th: S => t match { From dd358f45ab7e3e85aab41cbef04710a056a89b3e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 19 Oct 2020 11:29:25 -0700 Subject: [PATCH 280/457] UART Working... Bumped to newer fpga-shells --- fpga/Makefile | 2 +- fpga/fpga-shells | 2 +- .../main/scala/vcu118/bringup/Configs.scala | 24 ++++++++++++------- .../scala/vcu118/bringup/CustomOverlays.scala | 3 +-- .../scala/vcu118/bringup/TestHarness.scala | 3 +++ generators/sifive-blocks | 2 +- 6 files changed, 23 insertions(+), 13 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index e6bc426a..b984431c 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -29,7 +29,7 @@ TB := none # unused TOP := ChipTop # setup the board to use -BOARD ?= arty +BOARD ?= vcu118 .PHONY: default default: $(mcs) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index e8e7f8a3..89a5efec 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit e8e7f8a321ebde213ebc79db06422278d9aa477f +Subproject commit 89a5efec011ebc21b9455923501df70783161cb8 diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index f0dd91cc..8db731ed 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -1,6 +1,7 @@ package chipyard.fpga.vcu118.bringup import math.min +import sys.process._ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -54,6 +55,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { }) class SmallModifications extends Config((site, here, up) => { + case DebugModuleKey => None // disable debug module case SystemBusKey => up(SystemBusKey).copy( errorDevice = Some(DevNullParams( Seq(AddressSet(0x3000, 0xfff)), @@ -61,18 +63,24 @@ class SmallModifications extends Config((site, here, up) => { maxTransfer=128, region = RegionType.TRACKED))) case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = - Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt), + Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) + case ControlBusKey => up(ControlBusKey, site).copy( errorDevice = None) case DTSTimebase => BigInt(1000000) - case JtagDTMKey => new JtagDTMConfig( - idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai). - idcodePartNum = 0x000, // Decided to simplify. - idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses. - debugIdleCycles = 5) // Reasonable guess for synchronization }) +class WithBootROM extends Config((site, here, up) => { + case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => + // invoke makefile for sdboot + val freqMHz = site(DUTFrequencyKey).toInt * 1000000 + val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" + require (make.! == 0, "Failed to build bootrom") + p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") + } +}) class FakeBringupConfig extends Config( + new SmallModifications ++ new WithBringupUART ++ new WithBringupSPI ++ new WithBringupI2C ++ @@ -80,14 +88,14 @@ class FakeBringupConfig extends Config( new WithBringupDDR ++ new WithUARTIOPassthrough ++ new WithSPIIOPassthrough ++ - //new WithMMCSPIDTS ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithBringupPeripherals ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithBootROM ++ + new WithBootROM ++ // use local bootrom new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 2c438a34..fdbbb919 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -138,8 +138,7 @@ class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => { shell.xdc.addPackagePin(io, pin) shell.xdc.addIOStandard(io, iostd) - // TODO: no drive strength found - //if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } + if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } } } } } } diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 28e42e3c..28c3ae14 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -181,6 +181,9 @@ class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) exte val dutReset = harnessReset val success = false.B + childClock := harnessClock + childReset := harnessReset + // harness binders are non-lazy _outer.topDesign match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) diff --git a/generators/sifive-blocks b/generators/sifive-blocks index ed9f63f9..c160544e 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit ed9f63f9f5b9209c9e5ef2adfd063d6669691d79 +Subproject commit c160544e74db4f33d51f23c8a41c07a1ec16b7b7 From 7a55c55aa3e640e83b710c7bc9e73882af8959d2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 19 Oct 2020 16:17:46 -0700 Subject: [PATCH 281/457] Fix no-MBUS configs --- docs/Customization/IOBinders.rst | 4 ++-- generators/chipyard/src/main/scala/IOBinders.scala | 6 ++---- .../src/main/scala/config/SodorConfigs.scala | 12 ++++++------ 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index ff180bcd..1ae95512 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -4,7 +4,7 @@ IOBinders and HarnessBinders In Chipyard we use special ``Parameters`` keys, ``IOBinders`` and ``HarnessBinders`` to bridge the gap between digital system IOs and TestHarness collateral. IOBinders -========= +--------- The ``IOBinder`` functions are responsible for instantiating IO cells and IOPorts in the ``ChipTop`` layer. @@ -19,7 +19,7 @@ For example, the ``WithUARTIOCells`` IOBinder will, for any ``System`` that migh :end-before: DOC include end: WithUARTIOCells HarnessBinders -============== +-------------- The ``HarnessBinder`` functions determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. The ``HarnessBinder`` interface is designed to be reused across various simulation/implementation modes, enabling decoupling of the target design from simulation and testing concerns. diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 6bf8a6df..46bed169 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -267,8 +267,7 @@ class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveMasterAXI4MemPort) => { implicit val p: Parameters = GetSystemParameters(system) val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) - val mbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS) - clockSinkNode.map(_ := mbus.fixedClockNode) + clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { @@ -288,8 +287,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { implicit val p: Parameters = GetSystemParameters(system) val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) - val mbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS) - clockSinkNode.map(_ := mbus.fixedClockNode) + clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index ea245fbc..998ccff9 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -9,7 +9,7 @@ class Sodor1StageConfig extends Config( new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) @@ -18,7 +18,7 @@ class Sodor2StageConfig extends Config( new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) @@ -27,7 +27,7 @@ class Sodor3StageConfig extends Config( new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) @@ -36,7 +36,7 @@ class Sodor3StageSinglePortConfig extends Config( new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) @@ -45,7 +45,7 @@ class Sodor5StageConfig extends Config( new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) @@ -54,6 +54,6 @@ class SodorUCodeConfig extends Config( new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) From db73cab164b063da299bfcabba6c6d99f91277fb Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 20 Oct 2020 21:20:11 -0700 Subject: [PATCH 282/457] Add BootROM | Fix ResetWrangler for DDR | Add scripts --- fpga/.gitignore | 4 +- fpga/Makefile | 10 + fpga/scripts/run_impl_bitstream.tcl | 45 ++++ fpga/scripts/write_mmi.tcl | 75 ++++++ .../main/resources/vcu118/sdboot/.gitignore | 1 + .../src/main/resources/vcu118/sdboot/Makefile | 39 +++ .../src/main/resources/vcu118/sdboot/common.h | 9 + fpga/src/main/resources/vcu118/sdboot/head.S | 20 ++ .../resources/vcu118/sdboot/include/bits.h | 36 +++ .../resources/vcu118/sdboot/include/const.h | 18 ++ .../vcu118/sdboot/include/devices/clint.h | 14 ++ .../vcu118/sdboot/include/devices/gpio.h | 24 ++ .../vcu118/sdboot/include/devices/plic.h | 31 +++ .../vcu118/sdboot/include/devices/spi.h | 79 ++++++ .../vcu118/sdboot/include/devices/uart.h | 28 +++ .../vcu118/sdboot/include/platform.h | 108 ++++++++ .../sdboot/include/riscv_test_defaults.h | 81 ++++++ .../vcu118/sdboot/include/sections.h | 17 ++ .../resources/vcu118/sdboot/include/smp.h | 142 +++++++++++ .../main/resources/vcu118/sdboot/kprintf.c | 75 ++++++ .../main/resources/vcu118/sdboot/kprintf.h | 49 ++++ .../resources/vcu118/sdboot/linker/memory.lds | 5 + .../vcu118/sdboot/linker/sdboot.elf.lds | 79 ++++++ fpga/src/main/resources/vcu118/sdboot/sd.c | 236 ++++++++++++++++++ .../scala/vcu118/bringup/TestHarness.scala | 3 +- 25 files changed, 1223 insertions(+), 5 deletions(-) create mode 100644 fpga/scripts/run_impl_bitstream.tcl create mode 100644 fpga/scripts/write_mmi.tcl create mode 100644 fpga/src/main/resources/vcu118/sdboot/.gitignore create mode 100644 fpga/src/main/resources/vcu118/sdboot/Makefile create mode 100644 fpga/src/main/resources/vcu118/sdboot/common.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/head.S create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/bits.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/const.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/platform.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/sections.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/smp.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/kprintf.c create mode 100644 fpga/src/main/resources/vcu118/sdboot/kprintf.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/linker/memory.lds create mode 100644 fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds create mode 100644 fpga/src/main/resources/vcu118/sdboot/sd.c diff --git a/fpga/.gitignore b/fpga/.gitignore index a0991ff4..814384f3 100644 --- a/fpga/.gitignore +++ b/fpga/.gitignore @@ -1,3 +1 @@ -* -!.gitignore -!Makefile +generated-src diff --git a/fpga/Makefile b/fpga/Makefile index b984431c..748a5029 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -76,6 +76,16 @@ $(BIT_FILE): $(synth_list_f) .PHONY: bit bit: $(BIT_FILE) +.PHONY: debug-bitstream +debug-bitstream: $(build_dir)/obj/post_synth.dcp + cd $(build_dir); vivado \ + -nojournal -mode batch \ + -source $(sim_dir)/scripts/run_impl_bitstream.tcl \ + -tclargs \ + $(build_dir)/obj/post_synth.dcp \ + xcvu9p-flga2104-2l-e \ + $(build_dir)/obj/debug_output + # Build .mcs MCS_FILE := $(build_dir)/obj/$(MODEL).mcs $(MCS_FILE): $(BIT_FILE) diff --git a/fpga/scripts/run_impl_bitstream.tcl b/fpga/scripts/run_impl_bitstream.tcl new file mode 100644 index 00000000..ec3828e8 --- /dev/null +++ b/fpga/scripts/run_impl_bitstream.tcl @@ -0,0 +1,45 @@ +#### Command line arguments to this script +# argv[0] = absolute path to post_synth checkpoint file +# argv[1] = part +# argv[2] = output directory + +set synth_checkpoint_file [lindex $argv 0] +set part [lindex $argv 1] +set output_dir [lindex $argv 2] + +# Set the project part to the part passed into this script +set_part ${part} + +# Create output directory if it doesn't exist +file mkdir ${output_dir} +file mkdir ${output_dir}/reports +file mkdir ${output_dir}/outputs + +# Load synthesis checkpoint +open_checkpoint ${synth_checkpoint_file} + +# Run implementation and save reports as needed +opt_design +place_design +phys_opt_design +write_checkpoint -force ${output_dir}/outputs/post_place +report_timing_summary -file ${output_dir}/reports/post_place_timing_summary.rpt +report_drc -file ${output_dir}/reports/post_place_drc.rpt + +route_design +write_checkpoint -force ${output_dir}/outputs/post_route +report_timing_summary -file ${output_dir}/reports/post_route_timing_summary.rpt +report_timing -sort_by group -max_paths 100 -path_type summary -file ${output_dir}/reports/post_route_timing.rpt +report_clock_utilization -file ${output_dir}/reports/post_route_clock_utilization.rpt +report_utilization -file ${output_dir}/reports/post_route_utilization.rpt +report_drc -file ${output_dir}/reports/post_route_drc.rpt +report_cdc -details -file ${output_dir}/reports/post_route_cdc.rpt +report_clock_interaction -file ${output_dir}/reports/post_route_clock_interaction.rpt +report_bus_skew -file ${output_dir}/reports/post_route_bus_skew.rpt +report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file ${output_dir}/reports/post_route_timing_violations.rpt + +write_verilog -force ${output_dir}/outputs/post_route.v +write_xdc -no_fixed_only -force ${output_dir}/outputs/post_route.xdc + +write_bitstream -force ${output_dir}/outputs/top.bit +write_debug_probes -force ${output_dir}/outputs/debug_nets.ltx diff --git a/fpga/scripts/write_mmi.tcl b/fpga/scripts/write_mmi.tcl new file mode 100644 index 00000000..e577dd2b --- /dev/null +++ b/fpga/scripts/write_mmi.tcl @@ -0,0 +1,75 @@ +proc write_mmi {filepath inst} { + current_instance + current_instance $inst + set chn [open $filepath w] + puts $chn "" + puts $chn "" + puts $chn "\t" + set brams [dict create] + foreach cell [get_cells -hierarchical -filter { PRIMITIVE_GROUP =~ BLOCKRAM }] { + set name [get_property RTL_RAM_NAME $cell] + dict update brams $name name { + dict lappend name cells $cell + dict set name size [get_property RTL_RAM_BITS $cell] + } + } + proc compare {a b} { + set a_addr [get_property bram_addr_begin $a] + set b_addr [get_property bram_addr_begin $b] + if {$a_addr > $b_addr} { + return 1 + } elseif {$a_addr < $b_addr} { + return -1 + } + set a_slice [get_property bram_slice_begin $a] + set b_slice [get_property bram_slice_begin $b] + if {$a_slice > $b_slice} { + return 1 + } elseif {$a_slice < $b_slice} { + return -1 + } + return 0 + } + dict for {name desc} $brams { + dict with desc { + puts $chn "\t\t> 3]\">" + puts $chn "\t\t\t" + foreach cell [lsort -command compare $cells] { + set type [switch [get_property REF_NAME $cell] \ + RAMB36E2 {expr {"RAMB32"}} \ + RAMB36E1 {expr {"RAMB32"}}] + set loc [lindex [split [get_property LOC $cell] "_"] 1] + set lsb [get_property bram_slice_begin $cell] + set msb [get_property bram_slice_end $cell] + set addr_bgn [get_property bram_addr_begin $cell] + set addr_end [get_property bram_addr_end $cell] + puts $chn "\t\t\t\t" + puts $chn "\t\t\t\t\t" + puts $chn "\t\t\t\t\t" + puts $chn "\t\t\t\t\t" + puts $chn "\t\t\t\t" + } + puts $chn "\t\t\t" + puts $chn "\t\t" + } + } + puts $chn "\t" + puts $chn "\t" + puts $chn "\t\t" + puts $chn "" + close $chn + current_instance + +} + +if {$argc != 3} { + puts $argc + puts {Error: Invalid number of arguments} + puts {Usage: write_mmi.tcl checkpoint mmi_file instance} +} + +lassign $argv checkpoint mmi_file instance + +open_checkpoint $checkpoint +write_mmi $mmi_file $instance diff --git a/fpga/src/main/resources/vcu118/sdboot/.gitignore b/fpga/src/main/resources/vcu118/sdboot/.gitignore new file mode 100644 index 00000000..378eac25 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/.gitignore @@ -0,0 +1 @@ +build diff --git a/fpga/src/main/resources/vcu118/sdboot/Makefile b/fpga/src/main/resources/vcu118/sdboot/Makefile new file mode 100644 index 00000000..b9c21470 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/Makefile @@ -0,0 +1,39 @@ +# RISCV environment variable must be set +ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +BUILD_DIR := $(ROOT_DIR)/build + +CC=$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy +OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump +CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles +CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 +CFLAGS+= -I $(ROOT_DIR)/include -I. +LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds + +#PBUS_CLK passed in +elf := $(BUILD_DIR)/sdboot.elf +$(elf): head.S kprintf.c sd.c + mkdir -p $(BUILD_DIR) + $(CC) $(CFLAGS) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S sd.c kprintf.c + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/sdboot.bin +$(bin): $(elf) + mkdir -p $(BUILD_DIR) + $(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@ + +.PHONY: bin +bin: $(bin) + +dump := $(BUILD_DIR)/sdboot.dump +$(dump): $(elf) + $(OBJDUMP) -D -S $< > $@ + +.PHONY: dump +dump: $(dump) + +.PHONY: clean +clean:: + rm -rf $(BUILD_DIR) diff --git a/fpga/src/main/resources/vcu118/sdboot/common.h b/fpga/src/main/resources/vcu118/sdboot/common.h new file mode 100644 index 00000000..4f71e103 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/common.h @@ -0,0 +1,9 @@ +#ifndef _SDBOOT_COMMON_H +#define _SDBOOT_COMMON_H + +#ifndef PAYLOAD_DEST + #define PAYLOAD_DEST MEMORY_MEM_ADDR +#endif + + +#endif diff --git a/fpga/src/main/resources/vcu118/sdboot/head.S b/fpga/src/main/resources/vcu118/sdboot/head.S new file mode 100644 index 00000000..662a6fd2 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/head.S @@ -0,0 +1,20 @@ +// See LICENSE for license details. +#include +#include +#include "common.h" + + .section .text.init + .option norvc + .globl _prog_start +_prog_start: + smp_pause(s1, s2) + li sp, (PAYLOAD_DEST + 0xffff000) + call main + smp_resume(s1, s2) + csrr a0, mhartid // hartid for next level bootloader + la a1, dtb // dtb address for next level bootloader + li s1, PAYLOAD_DEST + jr s1 + + .section .rodata +dtb: diff --git a/fpga/src/main/resources/vcu118/sdboot/include/bits.h b/fpga/src/main/resources/vcu118/sdboot/include/bits.h new file mode 100644 index 00000000..bfe656fe --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/fpga/src/main/resources/vcu118/sdboot/include/const.h b/fpga/src/main/resources/vcu118/sdboot/include/const.h new file mode 100644 index 00000000..8dcffbb0 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h new file mode 100644 index 00000000..c2b05bae --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h new file mode 100644 index 00000000..f7f0acb4 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h new file mode 100644 index 00000000..4d5b2d8d --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h new file mode 100644 index 00000000..7118572a --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h @@ -0,0 +1,79 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#endif /* _SIFIVE_SPI_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h new file mode 100644 index 00000000..aecfd912 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h @@ -0,0 +1,28 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXNSTOP 0x2 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/platform.h b/fpga/src/main/resources/vcu118/sdboot/include/platform.h new file mode 100644 index 00000000..c240e0e5 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/platform.h @@ -0,0 +1,108 @@ +// See LICENSE for license details. + +#ifndef _EAGLE_PLATFORM_H +#define _EAGLE_PLATFORM_H + +#include "const.h" +#include "riscv_test_defaults.h" +#include "devices/clint.h" +#include "devices/gpio.h" +#include "devices/plic.h" +#include "devices/spi.h" +#include "devices/uart.h" + + // Some things missing from the official encoding.h +#if __riscv_xlen == 32 + #define MCAUSE_INT 0x80000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFUL +#else + #define MCAUSE_INT 0x8000000000000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL +#endif + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// CPU info +#define NUM_CORES 1 +#define GLOBAL_INT_SIZE 38 +#define GLOBAL_INT_MAX_PRIORITY 7 + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x2000000,UL) +#define CLINT_CTRL_SIZE _AC(0x10000,UL) +#define DEBUG_CTRL_ADDR _AC(0x0,UL) +#define DEBUG_CTRL_SIZE _AC(0x1000,UL) +#define ERROR_MEM_ADDR _AC(0x3000,UL) +#define ERROR_MEM_SIZE _AC(0x1000,UL) +#define GPIO_CTRL_ADDR _AC(0x64002000,UL) +#define GPIO_CTRL_SIZE _AC(0x1000,UL) +#define MASKROM_MEM_ADDR _AC(0x10000,UL) +#define MASKROM_MEM_SIZE _AC(0x10000,UL) +#define MEMORY_MEM_ADDR _AC(0x80000000,UL) +#define MEMORY_MEM_SIZE _AC(0x10000000,UL) +#define PLIC_CTRL_ADDR _AC(0xc000000,UL) +#define PLIC_CTRL_SIZE _AC(0x4000000,UL) +#define SPI_CTRL_ADDR _AC(0x64001000,UL) +#define SPI_CTRL_SIZE _AC(0x1000,UL) +#define SPI1_CTRL_ADDR _AC(0x64004000,UL) +#define SPI1_CTRL_SIZE _AC(0x1000,UL) +#define TEST_CTRL_ADDR _AC(0x4000,UL) +#define TEST_CTRL_SIZE _AC(0x1000,UL) +#define UART_CTRL_ADDR _AC(0x64000000,UL) +#define UART_CTRL_SIZE _AC(0x1000,UL) +#define UART1_CTRL_ADDR _AC(0x64003000,UL) +#define UART1_CTRL_SIZE _AC(0x1000,UL) +#define I2C_CTRL_ADDR _AC(0x64005000,UL) +#define I2C_CTRL_SIZE _AC(0x1000,UL) + +// IOF masks + + +// Interrupt numbers +#define UART_INT_BASE 1 +#define UART1_INT_BASE 2 +#define I2C_INT_BASE 3 +#define GPIO_INT_BASE 4 +#define SPI_INT_BASE 36 +#define SPI1_INT_BASE 37 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset) +#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset) +#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset) +#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset) +#define SPI1_REG64(offset) _REG64(SPI1_CTRL_ADDR, offset) +#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset) +#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset) +#define UART1_REG64(offset) _REG64(UART1_CTRL_ADDR, offset) +#define I2C_REG64(offset) _REG64(I2C_CTRL_ADDR, offset) + +// Misc + + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h new file mode 100644 index 00000000..a2dea3d4 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h @@ -0,0 +1,81 @@ +// See LICENSE for license details. +#ifndef _RISCV_TEST_DEFAULTS_H +#define _RISCV_TEST_DEFAULTS_H + +#define TESTNUM x28 +#define TESTBASE 0x4000 + +#define RVTEST_RV32U \ + .macro init; \ + .endm + +#define RVTEST_RV64U \ + .macro init; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + /* If FPU exists, initialize FCSR. */ \ + csrr t0, misa; \ + andi t0, t0, 1 << ('F' - 'A'); \ + beqz t0, 1f; \ + /* Enable FPU if it exists. */ \ + li t0, MSTATUS_FS; \ + csrs mstatus, t0; \ + fssr x0; \ +1: ; \ + .endm + +#define RVTEST_RV64UF \ + .macro init; \ + /* If FPU exists, initialize FCSR. */ \ + csrr t0, misa; \ + andi t0, t0, 1 << ('F' - 'A'); \ + beqz t0, 1f; \ + /* Enable FPU if it exists. */ \ + li t0, MSTATUS_FS; \ + csrs mstatus, t0; \ + fssr x0; \ +1: ; \ + .endm + +#define RVTEST_CODE_BEGIN \ + .section .text.init; \ + .globl _prog_start; \ +_prog_start: \ + init; + +#define RVTEST_CODE_END \ + unimp + +#define RVTEST_PASS \ + fence; \ + li t0, TESTBASE; \ + li t1, 0x5555; \ + sw t1, 0(t0); \ +1: \ + j 1b; + +#define RVTEST_FAIL \ + li t0, TESTBASE; \ + li t1, 0x3333; \ + slli a0, a0, 16; \ + add a0, a0, t1; \ + sw a0, 0(t0); \ +1: \ + j 1b; + +#define EXTRA_DATA + +#define RVTEST_DATA_BEGIN \ + EXTRA_DATA \ + .align 4; .global begin_signature; begin_signature: + +#define RVTEST_DATA_END \ + _msg_init: .asciz "RUN\r\n"; \ + _msg_pass: .asciz "PASS"; \ + _msg_fail: .asciz "FAIL "; \ + _msg_end: .asciz "\r\n"; \ + .align 4; .global end_signature; end_signature: + +#endif /* _RISCV_TEST_DEFAULTS_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/sections.h b/fpga/src/main/resources/vcu118/sdboot/include/sections.h new file mode 100644 index 00000000..6e1f0518 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/sections.h @@ -0,0 +1,17 @@ +// See LICENSE for license details. +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/smp.h b/fpga/src/main/resources/vcu118/sdboot/include/smp.h new file mode 100644 index 00000000..145ceb37 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/smp.h @@ -0,0 +1,142 @@ +#ifndef SIFIVE_SMP +#define SIFIVE_SMP +#include "platform.h" + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) +#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + li reg1, NONSMP_HART ;\ + csrr reg2, mhartid ;\ + bne reg1, reg2, 42f + +#ifdef CLINT1_CTRL_ADDR +// If a second CLINT exists, then make sure we: +// 1) Trigger a software interrupt on all harts of both CLINTs. +// 2) Locate your own hart's software interrupt pending register and clear it. +// 3) Wait for all harts on both CLINTs to clear their software interrupt +// pending register. +// WARNING: This code makes these assumptions, which are only true for Fadu as +// of now: +// 1) hart0 uses CLINT0 at offset 0 +// 2) hart2 uses CLINT1 at offset 0 +// 3) hart3 uses CLINT1 at offset 1 +// 4) There are no other harts or CLINTs in the system. +#define smp_resume(reg1, reg2) \ + /* Trigger software interrupt on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Trigger software interrupt on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Wait to receive software interrupt */ \ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + /* Clear own software interrupt bit */ \ + csrr reg2, mhartid ;\ + bnez reg2, 41f; \ + /* hart0 case: Use CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ + j 42f; \ +41: \ + /* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ + addi reg2, reg2, -2; \ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ; \ +42: \ + /* Wait for all software interrupt bits to be cleared on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* Wait for all software interrupt bits to be cleared on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* End smp_resume() */ + +#else + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif /* ifdef CLINT1_CTRL_ADDR */ + +#endif diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.c b/fpga/src/main/resources/vcu118/sdboot/kprintf.c new file mode 100644 index 00000000..57627011 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.c @@ -0,0 +1,75 @@ +// See LICENSE for license details. +#include +#include +#include + +#include "kprintf.h" + +static inline void _kputs(const char *s) +{ + char c; + for (; (c = *s) != '\0'; s++) + kputc(c); +} + +void kputs(const char *s) +{ + _kputs(s); + kputc('\r'); + kputc('\n'); +} + +void kprintf(const char *fmt, ...) +{ + va_list vl; + bool is_format, is_long, is_char; + char c; + + va_start(vl, fmt); + is_format = false; + is_long = false; + is_char = false; + while ((c = *fmt++) != '\0') { + if (is_format) { + switch (c) { + case 'l': + is_long = true; + continue; + case 'h': + is_char = true; + continue; + case 'x': { + unsigned long n; + long i; + if (is_long) { + n = va_arg(vl, unsigned long); + i = (sizeof(unsigned long) << 3) - 4; + } else { + n = va_arg(vl, unsigned int); + i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; + } + for (; i >= 0; i -= 4) { + long d; + d = (n >> i) & 0xF; + kputc(d < 10 ? '0' + d : 'a' + d - 10); + } + break; + } + case 's': + _kputs(va_arg(vl, const char *)); + break; + case 'c': + kputc(va_arg(vl, int)); + break; + } + is_format = false; + is_long = false; + is_char = false; + } else if (c == '%') { + is_format = true; + } else { + kputc(c); + } + } + va_end(vl); +} diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.h b/fpga/src/main/resources/vcu118/sdboot/kprintf.h new file mode 100644 index 00000000..26cc8055 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.h @@ -0,0 +1,49 @@ +// See LICENSE for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + +static inline void kputc(char c) +{ + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); +#ifdef __riscv_atomic + int32_t r; + do { + __asm__ __volatile__ ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (*tx) + : "r" (c)); + } while (r < 0); +#else + while ((int32_t)(*tx) < 0); + *tx = c; +#endif +} + +extern void kputs(const char *); +extern void kprintf(const char *, ...); + +#ifdef DEBUG +#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) +#define dputs(s) kputs((s)) +#else +#define dprintf(s, ...) do { } while (0) +#define dputs(s) do { } while (0) +#endif + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/memory.lds b/fpga/src/main/resources/vcu118/sdboot/linker/memory.lds new file mode 100644 index 00000000..997de4d3 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/linker/memory.lds @@ -0,0 +1,5 @@ +MEMORY +{ + bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000 + memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000 +} diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds new file mode 100644 index 00000000..34610c94 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds @@ -0,0 +1,79 @@ +OUTPUT_ARCH("riscv") +ENTRY(_prog_start) + +INCLUDE memory.lds + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + PROVIDE(_ram = ORIGIN(memory_mem)); + PROVIDE(_ram_end = _ram + LENGTH(memory_mem)); + + .text ALIGN((ORIGIN(bootrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(bootrom_mem) + 0x0), 8)) { + PROVIDE(_ftext = .); + *(.text.init) + *(.text.unlikely .text.unlikely.*) + *(.text .text.* .gnu.linkonce.t.*) + PROVIDE(_etext = .); + . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */ + } >bootrom_mem :text + + .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) { + *(.eh_frame) + } >bootrom_mem :text + + .srodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT { + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata.*) + } >bootrom_mem :data + + .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT { + *(.data .data.* .gnu.linkonce.d.*) + *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */ + } >bootrom_mem :data + + .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >bootrom_mem :data + + .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } >bootrom_mem :data + + PROVIDE(_data = ADDR(.rodata)); + PROVIDE(_data_lma = LOADADDR(.rodata)); + PROVIDE(_edata = .); + + .bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) { + PROVIDE(_fbss = .); + PROVIDE(__global_pointer$ = . + 0x7C0); + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(8); + PROVIDE(_ebss = .); + } >memory_mem :bss + + PROVIDE(_end = .); + + /* + * heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem)) + * heap_stack_min_size: 4096 + * heap_stack_max_size: 1048576 + */ + PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8)); + PROVIDE(_heap_end = _sp - 2048); + + /* This section is a noop and is only used for the ASSERT */ + .stack : { + ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack"); + } +} diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c new file mode 100644 index 00000000..bdd9d62a --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -0,0 +1,236 @@ +// See LICENSE for license details. +#include + +#include + +#include "common.h" + +#define DEBUG +#include "kprintf.h" + +#define MAX_CORES 8 + +// A sector is 512 bytes, so ((1 << 11) * 512) = 1 MiB +#define PAYLOAD_SIZE (16 << 11) + +// The sector at which the BBL partition starts +#define BBL_PARTITION_START_SECTOR 34 + +#ifndef TL_CLK +#error Must define TL_CLK +#endif + +#define F_CLK TL_CLK + +static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); + +static inline uint8_t spi_xfer(uint8_t d) +{ + int32_t r; + + REG32(spi, SPI_REG_TXFIFO) = d; + do { + r = REG32(spi, SPI_REG_RXFIFO); + } while (r < 0); + return r; +} + +static inline uint8_t sd_dummy(void) +{ + return spi_xfer(0xFF); +} + +static uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_HOLD; + sd_dummy(); + spi_xfer(cmd); + spi_xfer(arg >> 24); + spi_xfer(arg >> 16); + spi_xfer(arg >> 8); + spi_xfer(arg); + spi_xfer(crc); + + n = 1000; + do { + r = sd_dummy(); + if (!(r & 0x80)) { +// dprintf("sd:cmd: %hx\r\n", r); + goto done; + } + } while (--n > 0); + kputs("sd_cmd: timeout"); +done: + return r; +} + +static inline void sd_cmd_end(void) +{ + sd_dummy(); + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(void) +{ + long i; + REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; + for (i = 10; i > 0; i--) { + sd_dummy(); + } + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; +} + +static int sd_cmd0(void) +{ + int rc; + dputs("CMD0"); + rc = (sd_cmd(0x40, 0, 0x95) != 0x01); + sd_cmd_end(); + return rc; +} + +static int sd_cmd8(void) +{ + int rc; + dputs("CMD8"); + rc = (sd_cmd(0x48, 0x000001AA, 0x87) != 0x01); + sd_dummy(); /* command version; reserved */ + sd_dummy(); /* reserved */ + rc |= ((sd_dummy() & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy() != 0xAA); /* check pattern */ + sd_cmd_end(); + return rc; +} + +static void sd_cmd55(void) +{ + sd_cmd(0x77, 0, 0x65); + sd_cmd_end(); +} + +static int sd_acmd41(void) +{ + uint8_t r; + dputs("ACMD41"); + do { + sd_cmd55(); + r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */ + } while (r == 0x01); + return (r != 0x00); +} + +static int sd_cmd58(void) +{ + int rc; + dputs("CMD58"); + rc = (sd_cmd(0x7A, 0, 0xFD) != 0x00); + rc |= ((sd_dummy() & 0x80) != 0x80); /* Power up status */ + sd_dummy(); + sd_dummy(); + sd_dummy(); + sd_cmd_end(); + return rc; +} + +static int sd_cmd16(void) +{ + int rc; + dputs("CMD16"); + rc = (sd_cmd(0x50, 0x200, 0x15) != 0x00); + sd_cmd_end(); + return rc; +} + +static uint16_t crc16_round(uint16_t crc, uint8_t data) { + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + +#define SPIN_SHIFT 6 +#define SPIN_UPDATE(i) (!((i) & ((1 << SPIN_SHIFT)-1))) +#define SPIN_INDEX(i) (((i) >> SPIN_SHIFT) & 0x3) + +static const char spinner[] = { '-', '/', '|', '\\' }; + +static int copy(void) +{ + volatile uint8_t *p = (void *)(PAYLOAD_DEST); + long i = PAYLOAD_SIZE; + int rc = 0; + + dputs("CMD18"); + kprintf("LOADING "); + + // John: Let's go slow until we get this working + //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); + REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); + if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { + sd_cmd_end(); + return 1; + } + do { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy() != 0xFE); + do { + uint8_t x = sd_dummy(); + *p++ = x; + crc = crc16_round(crc, x); + } while (--n > 0); + + crc_exp = ((uint16_t)sd_dummy() << 8); + crc_exp |= sd_dummy(); + + if (crc != crc_exp) { + kputs("\b- CRC mismatch "); + rc = 1; + break; + } + + if (SPIN_UPDATE(i)) { + kputc('\b'); + kputc(spinner[SPIN_INDEX(i)]); + } + } while (--i > 0); + sd_cmd_end(); + + sd_cmd(0x4C, 0, 0x01); + sd_cmd_end(); + kputs("\b "); + return rc; +} + +int main(void) +{ + REG32(uart, UART_REG_TXCTRL) = UART_TXEN; + + kputs("INIT"); + sd_poweron(); + if (sd_cmd0() || + sd_cmd8() || + sd_acmd41() || + sd_cmd58() || + sd_cmd16() || + copy()) { + kputs("ERROR"); + return 1; + } + + kputs("BOOT"); + + __asm__ __volatile__ ("fence.i" : : : "memory"); + + return 0; +} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 28c3ae14..4eaea05b 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -134,8 +134,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends /*** DDR ***/ - val ddrWrangler = LazyModule(new ResetWrangler) - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) // connect 1 mem. channel to the FPGA DDR val inParams = topDesign match { case td: ChipTop => From ac19117ec5fc890b9c9b9540c3cb3f0c1ab65721 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 23 Oct 2020 15:41:49 -0700 Subject: [PATCH 283/457] Add MultiRoCCGemmini config fragment --- .../chipyard/src/main/scala/ConfigFragments.scala | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index e66dfb4a..68c41724 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -18,6 +18,7 @@ import testchipip._ import tracegen.{TraceGenSystem} import hwacha.{Hwacha} +import gemmini.{Gemmini, GemminiConfigs} import boom.common.{BoomTileAttachParams} import ariane.{ArianeTileAttachParams} @@ -105,6 +106,16 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config( }) ) +class WithMultiRoCCGemmini(harts: Int*) extends Config((site, here, up) => { + case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => + (i -> Seq((p: Parameters) => { + implicit val q = p + val gemmini = LazyModule(new Gemmini(OpcodeSet.custom3, GemminiConfigs.defaultConfig)) + gemmini + })) + } +}) + class WithTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( From 0c4dcffb0d40fe0146b25fc4d7ad2dff94a0bd2c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 23 Oct 2020 16:39:56 -0700 Subject: [PATCH 284/457] Fixed lowercase p bug --- generators/utilities/src/main/resources/csrc/emulator.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index f42f5bce..d3813bbd 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -223,7 +223,6 @@ int main(int argc, char** argv) verilog_plusargs_legal = 0; } else { c = 'P'; - verilated_argv[verilated_argc++] = optarg; } goto retry; } @@ -245,13 +244,14 @@ int main(int argc, char** argv) << arg << "\"\n"; c = '?'; } else { - c = 'p'; - verilated_argv[verilated_argc++] = optarg; + c = 'P'; } } goto retry; } - case 'P': break; // Nothing to do here, Verilog PlusArg + case 'P': + verilated_argv[verilated_argc++] = optarg; + break; // Nothing to do here, Verilog PlusArg // Realize that we've hit HTIF (HOST) arguments or error out default: if (c >= HTIF_LONG_OPTIONS_OPTIND) { From abbeb2af9e18417dfc6a363a7463373fa6920db3 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 23 Oct 2020 17:00:56 -0700 Subject: [PATCH 285/457] Fixed comments --- generators/utilities/src/main/resources/csrc/emulator.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index d3813bbd..40b5a2fa 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -249,9 +249,9 @@ int main(int argc, char** argv) } goto retry; } - case 'P': + case 'P': // Verilog PlusArg, add to the argument list for verilator environment verilated_argv[verilated_argc++] = optarg; - break; // Nothing to do here, Verilog PlusArg + break; // Realize that we've hit HTIF (HOST) arguments or error out default: if (c >= HTIF_LONG_OPTIONS_OPTIND) { @@ -270,7 +270,7 @@ done_processing: return 1; } - // Copy the binary file name into the verilator argument stack + // Copy remaining HTIF arguments (if any) and the binary file name into the verilator argument stack while (optind < argc) verilated_argv[verilated_argc++] = argv[optind++]; if (verbose) From 93e57ef23096528a6edd36c52e0ae69b6e629d06 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 26 Oct 2020 15:18:34 -0700 Subject: [PATCH 286/457] Make the ChipTop reset pin async always --- .../chipyard/src/main/scala/Clocks.scala | 52 +++---------------- .../chipyard/src/main/scala/IOBinders.scala | 18 +++---- .../chipyard/src/main/scala/TestHarness.scala | 3 +- 3 files changed, 15 insertions(+), 58 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 70fe38e7..3c9e70cd 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -15,40 +15,6 @@ import testchipip.{TLTileResetCtrl} import chipyard.clocking._ -/** - * Chipyard provides three baseline, top-level reset schemes, set using the - * [[GlobalResetSchemeKey]] in a Parameters instance. These are: - * - * 1) Synchronous: The input coming to the chip is synchronous to the provided - * clocks and will be used without modification as a synchronous reset. - * This is safe only for use in FireSim and SW simulation. - * - * 2) Asynchronous: The input reset is asynchronous to the input clock, but it - * is caught and synchronized to that clock before it is dissemenated. - * Thus, downsteam modules will be emitted with synchronously reset state - * elements. - * - * 3) Asynchronous Full: The input reset is asynchronous to the input clock, - * and is used globally as an async reset. Downstream modules will be emitted - * with asynchronously reset state elements. - * - */ -sealed trait GlobalResetScheme { - def pinIsAsync: Boolean -} -sealed trait HasAsyncInput { self: GlobalResetScheme => - def pinIsAsync = true -} - -sealed trait HasSyncInput { self: GlobalResetScheme => - def pinIsAsync = false -} - -case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput -case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput -case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput -case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous) - /** * A simple reset implementation that punches out reset ports * for standard Module classes. Three basic reset schemes @@ -58,18 +24,12 @@ object GenerateReset { def apply(chiptop: ChipTop, clock: Clock): Reset = { implicit val p = chiptop.p // this needs directionality so generateIOFromSignal works - val reset_wire = Wire(Input(Reset())) - val (reset_io, resetIOCell) = p(GlobalResetSchemeKey) match { - case GlobalResetSynchronous => - IOCell.generateIOFromSignal(reset_wire, "reset") - case GlobalResetAsynchronousFull => - IOCell.generateIOFromSignal(reset_wire, "reset", abstractResetAsAsync = true) - case GlobalResetAsynchronous => { - val async_reset_wire = Wire(Input(AsyncReset())) - reset_wire := ResetCatchAndSync(clock, async_reset_wire.asBool()) - IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true) - } - } + val async_reset_wire = Wire(Input(AsyncReset())) + val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", + abstractResetAsAsync = true) + + val reset_wire = ResetCatchAndSync(clock, async_reset_wire.asBool()) + chiptop.iocells ++= resetIOCell chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { reset_io := th.dutReset diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 87480bfc..246d9c3d 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -24,8 +24,6 @@ import barstools.iocell.chisel._ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} -import chipyard.GlobalResetSchemeKey - import scala.reflect.{ClassTag} // System for instantiating binders based @@ -157,7 +155,7 @@ class WithGPIOCells extends OverrideIOBinder({ class WithUARTIOCells extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) => - val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey)) + val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true) (port, ios) }).unzip (ports, cells2d.flatten) @@ -173,8 +171,8 @@ class WithSPIIOCells extends OverrideIOBinder({ val iocellBase = s"iocell_${name}" // SCK and CS are unidirectional outputs - val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey)) - val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey)) + val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset) + val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset) // DQ are bidirectional, so then need special treatment val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) => @@ -196,7 +194,7 @@ class WithSPIIOCells extends OverrideIOBinder({ class WithExtInterruptIOCells extends OverrideIOBinder({ (system: HasExtInterruptsModuleImp) => { if (system.outer.nExtInterrupts > 0) { - val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey)) + val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true) (Seq(port), cells) } else { (Nil, Nil) @@ -240,15 +238,15 @@ class WithDebugIOCells extends OverrideIOBinder({ // Add IOCells for the DMI/JTAG/APB ports val dmiTuple = debug.clockeddmi.map { d => - IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true) } val jtagTuple = debug.systemjtag.map { j => - IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = true) } val apbTuple = debug.apb.map { a => - IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = true) } val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq @@ -260,7 +258,7 @@ class WithDebugIOCells extends OverrideIOBinder({ class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey)) + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true) (Seq(port), cells) }).getOrElse((Nil, Nil)) }) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 2faff565..0b49d03c 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -39,8 +39,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign val harnessReset = WireInit(reset) val success = io.success - // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset - val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) + val dutReset = reset.asAsyncReset lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) From 3c42e2cae7a903d4d3e914d90405274e247cbbb1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 26 Oct 2020 18:15:58 -0700 Subject: [PATCH 287/457] Fixed BootROM | Updated HarnessBinders --- fpga/src/main/resources/vcu118/sdboot/head.S | 3 ++- .../vcu118/sdboot/linker/sdboot.elf.lds | 1 + .../main/scala/vcu118/bringup/Configs.scala | 19 +++++++------- .../scala/vcu118/bringup/HarnessBinders.scala | 13 +++++----- .../main/scala/vcu118/bringup/IOBinders.scala | 25 +++++++++++++------ .../scala/vcu118/bringup/TestHarness.scala | 5 +++- .../chipyard/src/main/scala/ChipTop.scala | 4 +-- generators/sifive-blocks | 2 +- 8 files changed, 43 insertions(+), 29 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/head.S b/fpga/src/main/resources/vcu118/sdboot/head.S index 662a6fd2..d871b824 100644 --- a/fpga/src/main/resources/vcu118/sdboot/head.S +++ b/fpga/src/main/resources/vcu118/sdboot/head.S @@ -16,5 +16,6 @@ _prog_start: li s1, PAYLOAD_DEST jr s1 - .section .rodata + .section .dtb + .align 3 dtb: diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds index 34610c94..7a0a42fe 100644 --- a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds +++ b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds @@ -47,6 +47,7 @@ SECTIONS .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.dtb) } >bootrom_mem :data PROVIDE(_data = ADDR(.rodata)); diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 8db731ed..79dbf6db 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -18,7 +18,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import chipyard.{BuildTop} @@ -29,12 +29,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L), - injectFunc = Some((spi: TLSPI) => { - ResourceBinding { - Resource(new MMCDevice(spi.device, 1), "reg").bind(ResourceAddress(0)) - } - })), + SPIParams(rAddress = BigInt(0x64001000L)), SPIParams(rAddress = BigInt(0x64004000L))) case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( @@ -56,6 +51,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { class SmallModifications extends Config((site, here, up) => { case DebugModuleKey => None // disable debug module + case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS case SystemBusKey => up(SystemBusKey).copy( errorDevice = Some(DevNullParams( Seq(AddressSet(0x3000, 0xfff)), @@ -79,6 +75,10 @@ class WithBootROM extends Config((site, here, up) => { } }) +class WithExtMemSetToDDR extends Config((site, here, up) => { + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) +}) + class FakeBringupConfig extends Config( new SmallModifications ++ new WithBringupUART ++ @@ -92,6 +92,7 @@ class FakeBringupConfig extends Config( new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithBringupPeripherals ++ + new WithExtMemSetToDDR ++ // set the external mem port size properly new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ @@ -100,8 +101,8 @@ class FakeBringupConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ + //new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new chipyard.WithMulticlockCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index efe805cd..79f602dc 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.fpga.vcu118.bringup import chisel3._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.{Analog, IO, BaseModule} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} @@ -19,13 +19,12 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} import chipyard.harness._ /*** UART ***/ class WithBringupUART extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) @@ -39,7 +38,7 @@ class WithBringupUART extends OverrideHarnessBinder({ /*** SPI ***/ class WithBringupSPI extends OverrideHarnessBinder({ - (system: HasPeripherySPIModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) @@ -53,7 +52,7 @@ class WithBringupSPI extends OverrideHarnessBinder({ /*** I2C ***/ class WithBringupI2C extends OverrideHarnessBinder({ - (system: HasPeripheryI2CModuleImp, th: HasHarnessSignalReferences, ports: Seq[I2CPort]) => { + (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) @@ -66,7 +65,7 @@ class WithBringupI2C extends OverrideHarnessBinder({ /*** GPIO ***/ class WithBringupGPIO extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => bb_io.bundle <> dut_io @@ -79,7 +78,7 @@ class WithBringupGPIO extends OverrideHarnessBinder({ /*** Experimental DDR ***/ class WithBringupDDR extends OverrideHarnessBinder({ - (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index ece212bb..558b074f 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -5,7 +5,7 @@ import chisel3.util.experimental.{BoringUtils} import chisel3.experimental.{Analog, IO, DataMirror} import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress, InModuleBody} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem._ @@ -27,7 +27,7 @@ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort} -import chipyard.iobinders.{OverrideIOBinder} +import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { @@ -49,13 +49,22 @@ class WithGPIOIOPassthrough extends OverrideIOBinder({ } }) -class WithSPIIOPassthrough extends OverrideIOBinder({ - (system: HasPeripherySPIModuleImp) => { - val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } - (io_spi_pins_temp zip system.spi).map { case (io, sysio) => - io <> sysio +class WithSPIIOPassthrough extends OverrideLazyIOBinder({ + (system: HasPeripherySPI) => { + // attach resource to 1st SPI + ResourceBinding { + Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) + } + + InModuleBody { + system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } } } - (io_spi_pins_temp, Nil) } }) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 4eaea05b..9f51d2aa 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -20,6 +20,7 @@ import sifive.blocks.devices.gpio._ import chipyard.harness._ import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} +import chipyard.iobinders.{HasIOBinders} case object DUTFrequencyKey extends Field[Double](100.0) @@ -186,6 +187,8 @@ class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) exte // harness binders are non-lazy _outer.topDesign match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } + _outer.topDesign match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) } } diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index bf07bcee..61a043b6 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -23,8 +23,8 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) * drive clock and reset generation */ -class ChipTop(implicit p: Parameters) extends LazyModule - with HasTestHarnessFunctions with HasIOBinders with BindingScope { +class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope + with HasTestHarnessFunctions with HasIOBinders { // The system module specified by BuildSystem lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c160544e..25eae85e 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c160544e74db4f33d51f23c8a41c07a1ec16b7b7 +Subproject commit 25eae85e711d650a305eb1cd923421a2872fcc56 From 0eca51ba4dce419b803945ad888b27ba7981a455 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 27 Oct 2020 12:57:34 -0700 Subject: [PATCH 288/457] Reorganize into bringup/simple | Bump sifive-blocks --- fpga/Makefile | 54 +++++-- fpga/src/main/scala/vcu118/Configs.scala | 85 +++++++++++ .../main/scala/vcu118/HarnessBinders.scala | 51 +++++++ fpga/src/main/scala/vcu118/IOBinders.scala | 52 +++++++ fpga/src/main/scala/vcu118/TestHarness.scala | 144 ++++++++++++++++++ .../main/scala/vcu118/bringup/Configs.scala | 92 +++-------- .../scala/vcu118/bringup/CustomOverlays.scala | 4 - .../scala/vcu118/bringup/HarnessBinders.scala | 53 ++----- .../main/scala/vcu118/bringup/IOBinders.scala | 66 +------- .../scala/vcu118/bringup/TestHarness.scala | 144 ++---------------- generators/sifive-blocks | 2 +- 11 files changed, 420 insertions(+), 327 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/Configs.scala create mode 100644 fpga/src/main/scala/vcu118/HarnessBinders.scala create mode 100644 fpga/src/main/scala/vcu118/IOBinders.scala create mode 100644 fpga/src/main/scala/vcu118/TestHarness.scala diff --git a/fpga/Makefile b/fpga/Makefile index 748a5029..74af21e9 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -14,22 +14,52 @@ sim_name := none ######################################################################################### # include shared variables ######################################################################################### +SUB_PROJECT ?= vcu118 + +ifeq ($(SUB_PROJECT),vcu118) + SBT_PROJECT ?= fpga_platforms + MODEL ?= VCU118FPGATestHarness + VLOG_MODEL ?= VCU118FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vcu118 + CONFIG ?= RocketVCU118Config + CONFIG_PACKAGE ?= chipyard.fpga.vcu118 + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= vcu118 +endif + +ifeq ($(SUB_PROJECT),bringup) + SBT_PROJECT ?= fpga_platforms + MODEL ?= BringupVCU118FPGATestHarness + VLOG_MODEL ?= BringupVCU118FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup + CONFIG ?= RocketBringupConfig + CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= vcu118 +endif + +ifeq ($(SUB_PROJECT),arty) + # TODO: Fix with Arty + SBT_PROJECT ?= fpga_platforms + MODEL ?= BringupVCU118FPGATestHarness + VLOG_MODEL ?= BringupVCU118FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup + CONFIG ?= RocketBringupConfig + CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= arty +endif + include $(base_dir)/variables.mk # default variables to build the arty example -SUB_PROJECT := fpga -SBT_PROJECT := fpga_platforms -MODEL := BringupVCU118FPGATestHarness -VLOG_MODEL := BringupVCU118FPGATestHarness -MODEL_PACKAGE := chipyard.fpga.vcu118.bringup -CONFIG := FakeBringupConfig -CONFIG_PACKAGE := chipyard.fpga.vcu118.bringup -GENERATOR_PACKAGE := chipyard -TB := none # unused -TOP := ChipTop - # setup the board to use -BOARD ?= vcu118 .PHONY: default default: $(mcs) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala new file mode 100644 index 00000000..f7b0df10 --- /dev/null +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -0,0 +1,85 @@ +package chipyard.fpga.vcu118 + +import sys.process._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} +import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} +import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.tile.{XLen} + +import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} + +import sifive.fpgashells.shell.{DesignKey} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} + +class WithDefaultPeripherals extends Config((site, here, up) => { + case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) + case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) + case VCU118ShellPMOD => "SDIO" +}) + +class WithSystemModifications extends Config((site, here, up) => { + case DebugModuleKey => None // disable debug module + case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS + case SystemBusKey => up(SystemBusKey).copy( + errorDevice = Some(DevNullParams( + Seq(AddressSet(0x3000, 0xfff)), + maxAtomic=site(XLen)/8, + maxTransfer=128, + region = RegionType.TRACKED))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = + Some(BigDecimal(site(FPGAFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) + case ControlBusKey => up(ControlBusKey, site).copy( + errorDevice = None) + case DTSTimebase => BigInt(1000000) + case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => + // invoke makefile for sdboot + val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 + val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" + require (make.! == 0, "Failed to build bootrom") + p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") + } + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) +}) + +class AbstractVCU118Config extends Config( + new WithUART ++ + new WithSPISDCard ++ + new WithDDRMem ++ + new WithUARTIOPassthrough ++ + new WithSPIIOPassthrough ++ + new WithTLIOPassthrough ++ + new WithDefaultPeripherals ++ + new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new chipyard.WithMulticlockCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class RocketVCU118Config extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new AbstractVCU118Config) + +class BoomVCU118Config extends Config( + new WithFPGAFrequency(75) ++ + new boom.common.WithNLargeBooms(1) ++ + new AbstractVCU118Config) + +class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { + case FPGAFrequencyKey => MHz +}) + +class WithFPGAFreq25MHz extends WithFPGAFrequency(25) +class WithFPGAFreq50MHz extends WithFPGAFrequency(50) +class WithFPGAFreq75MHz extends WithFPGAFrequency(75) +class WithFPGAFreq100MHz extends WithFPGAFrequency(100) diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala new file mode 100644 index 00000000..ae2462a2 --- /dev/null +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -0,0 +1,51 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{BaseModule} + +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} + +import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} +import chipyard.harness.{OverrideHarnessBinder} + +/*** UART ***/ +class WithUART extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + th match { case vcu118th: VCU118FPGATestHarnessImp => { + vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head + } } + + Nil + } +}) + +/*** SPI ***/ +class WithSPISDCard extends OverrideHarnessBinder({ + (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + th match { case vcu118th: VCU118FPGATestHarnessImp => { + vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head + } } + + Nil + } +}) + +/*** Experimental DDR ***/ +class WithDDRMem extends OverrideHarnessBinder({ + (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + th match { case vcu118th: VCU118FPGATestHarnessImp => { + require(ports.size == 1) + + val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> ports.head + } } + + Nil + } +}) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala new file mode 100644 index 00000000..a1f67bcd --- /dev/null +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -0,0 +1,52 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{IO, DataMirror} + +import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody} +import freechips.rocketchip.subsystem.{BaseSubsystem} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} +import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} + +import chipyard.{CanHaveMasterTLMemPort} +import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} + +class WithUARTIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } + (io_uart_pins_temp zip system.uart).map { case (io, sysio) => + io <> sysio + } + (io_uart_pins_temp, Nil) + } +}) + +class WithSPIIOPassthrough extends OverrideLazyIOBinder({ + (system: HasPeripherySPI) => { + // attach resource to 1st SPI + ResourceBinding { + Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) + } + + InModuleBody { + system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } } + } + } +}) + +class WithTLIOPassthrough extends OverrideIOBinder({ + (system: CanHaveMasterTLMemPort) => { + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> system.mem_tl + (Seq(io_tl_mem_pins_temp), Nil) + } +}) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala new file mode 100644 index 00000000..4748c528 --- /dev/null +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -0,0 +1,144 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{IO} + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ + +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} +import chipyard.iobinders.{HasIOBinders} +import chipyard.harness.{ApplyHarnessBinders} + +case object FPGAFrequencyKey extends Field[Double](100.0) + +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { + + def dp = designParameters + + val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO" + val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") + + // Order matters; ddr depends on sys_clock + val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput())) + val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None + val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) + val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput())) + val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) + val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) + val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) + + val topDesign = LazyModule(p(BuildTop)(dp)) + + // place all clocks in the shell + dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } + + /*** Connect/Generate clocks ***/ + + // connect to the PLL that will generate multiple clocks + val harnessSysPLL = dp(PLLFactoryKey)() + sys_clock.get() match { + case Some(x : SysClockVCU118PlacedOverlay) => { + harnessSysPLL := x.node + } + } + + // create and connect to the dutClock + val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val dutWrangler = LazyModule(new ResetWrangler) + val dutGroup = ClockGroup() + dutClock := dutWrangler.node := dutGroup := harnessSysPLL + + // connect ref clock to dummy sink node + ref_clock.get() match { + case Some(x : RefClockVCU118PlacedOverlay) => { + val sink = ClockSinkNode(Seq(ClockSinkParameters())) + sink := x.node + } + } + + /*** UART ***/ + + // 1st UART goes to the VCU118 dedicated UART + + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + + /*** SPI ***/ + + // 1st SPI goes to the VCU118 SDIO port + + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) + dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) + + /*** DDR ***/ + + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + ddrPlaced.overlayOutput.ddr := ddrClient + + // module implementation + override lazy val module = new VCU118FPGATestHarnessImp(this) +} + +class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { + + val vcu118Outer = _outer + + val reset = IO(Input(Bool())) + _outer.xdc.addPackagePin(reset, "L19") + _outer.xdc.addIOStandard(reset, "LVCMOS12") + + val reset_ibuf = Module(new IBUF) + reset_ibuf.io.I := reset + + val sysclk: Clock = _outer.sys_clock.get() match { + case Some(x: SysClockVCU118PlacedOverlay) => x.clock + } + + val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) + _outer.sdc.addAsyncPath(Seq(powerOnReset)) + + val ereset: Bool = _outer.chiplink.get() match { + case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n + case _ => false.B + } + + _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) + + // cy stuff + val harnessClock = _outer.dutClock.in.head._1.clock + val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) + val dutReset = harnessReset + val success = false.B + + childClock := harnessClock + childReset := harnessReset + + // harness binders are non-lazy + _outer.topDesign match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + } + _outer.topDesign match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } +} diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 79dbf6db..0e5602e5 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -1,39 +1,24 @@ package chipyard.fpga.vcu118.bringup import math.min -import sys.process._ -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.config.{Config} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} -import freechips.rocketchip.system._ -import freechips.rocketchip.tile._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} +import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} +import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} -import chipyard.{BuildTop} - -import chipyard.harness._ +import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} class WithBringupPeripherals extends Config((site, here, up) => { - case PeripheryUARTKey => List( - UARTParams(address = BigInt(0x64000000L)), - UARTParams(address = BigInt(0x64003000L))) - case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), - SPIParams(rAddress = BigInt(0x64004000L))) - case VCU118ShellPMOD => "SDIO" - case PeripheryI2CKey => List( - I2CParams(address = BigInt(0x64005000L))) + case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) + case PeripherySPIKey => up(PeripherySPIKey, site) ++ List(SPIParams(rAddress = BigInt(0x64004000L))) + case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) @@ -49,60 +34,19 @@ class WithBringupPeripherals extends Config((site, here, up) => { } }) -class SmallModifications extends Config((site, here, up) => { - case DebugModuleKey => None // disable debug module - case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS - case SystemBusKey => up(SystemBusKey).copy( - errorDevice = Some(DevNullParams( - Seq(AddressSet(0x3000, 0xfff)), - maxAtomic=site(XLen)/8, - maxTransfer=128, - region = RegionType.TRACKED))) - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = - Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) - case ControlBusKey => up(ControlBusKey, site).copy( - errorDevice = None) - case DTSTimebase => BigInt(1000000) -}) - -class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => - // invoke makefile for sdboot - val freqMHz = site(DUTFrequencyKey).toInt * 1000000 - val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" - require (make.! == 0, "Failed to build bootrom") - p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") - } -}) - -class WithExtMemSetToDDR extends Config((site, here, up) => { - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) -}) - -class FakeBringupConfig extends Config( - new SmallModifications ++ +class WithBringupAdditions extends Config( new WithBringupUART ++ new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ - new WithBringupDDR ++ - new WithUARTIOPassthrough ++ - new WithSPIIOPassthrough ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ - new WithTLIOPassthrough ++ + new WithBringupPeripherals) + +class RocketBringupConfig extends Config( new WithBringupPeripherals ++ - new WithExtMemSetToDDR ++ // set the external mem port size properly - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new WithBootROM ++ // use local bootrom - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - //new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new chipyard.WithMulticlockCoherentBusTopology ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new RocketVCU118Config) + +class BoomBringupConfig extends Config( + new WithBringupPeripherals ++ + new BoomVCU118Config) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index fdbbb919..c0a96d3c 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -4,15 +4,11 @@ import chisel3._ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ -import chipsalliance.rocketchip.config.{Parameters, Field} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ -import sifive.blocks.devices.gpio._ - - import chipyard.fpga.vcu118.{FMCPMap} /* Connect the I2C to certain FMC pins */ diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 79f602dc..b6693036 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -3,33 +3,21 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{Analog, IO, BaseModule} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} +import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks._ - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} -import chipyard.harness._ +import chipyard.{HasHarnessSignalReferences} +import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} /*** UART ***/ -class WithBringupUART extends OverrideHarnessBinder({ +class WithBringupUART extends ComposeHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) - vcu118th.outer.io_uart_bb.bundle <> ports.head - vcu118th.outer.io_uart_bb_2.bundle <> ports.last + vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last } } Nil @@ -37,13 +25,12 @@ class WithBringupUART extends OverrideHarnessBinder({ }) /*** SPI ***/ -class WithBringupSPI extends OverrideHarnessBinder({ +class WithBringupSPI extends ComposeHarnessBinder({ (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) - vcu118th.outer.io_spi_bb.bundle <> ports.head - vcu118th.outer.io_spi_bb_2.bundle <> ports.last + vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last } } Nil @@ -56,7 +43,7 @@ class WithBringupI2C extends OverrideHarnessBinder({ th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) - vcu118th.outer.io_i2c_bb.bundle <> ports.head + vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head } } Nil @@ -67,7 +54,7 @@ class WithBringupI2C extends OverrideHarnessBinder({ class WithBringupGPIO extends OverrideHarnessBinder({ (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => + (vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) => bb_io.bundle <> dut_io } } } @@ -75,19 +62,3 @@ class WithBringupGPIO extends OverrideHarnessBinder({ Nil } }) - -/*** Experimental DDR ***/ -class WithBringupDDR extends OverrideHarnessBinder({ - (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - require(ports.size == 1) - - val bundles = vcu118th.outer.ddrClient.out.map(_._1) - val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) - bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } - ddrClientBundle <> ports.head - } } - - Nil - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 558b074f..168933f7 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -1,43 +1,12 @@ package chipyard.fpga.vcu118.bringup import chisel3._ -import chisel3.util.experimental.{BoringUtils} -import chisel3.experimental.{Analog, IO, DataMirror} +import chisel3.experimental.{IO, DataMirror} -import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress, InModuleBody} -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.jtag.{JTAGIO} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system.{SimAXIMem} -import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} -import freechips.rocketchip.util._ -import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} -import freechips.rocketchip.tilelink.{TLBundle} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} +import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import tracegen.{TraceGenSystemModuleImp} - -import barstools.iocell.chisel._ - -import testchipip._ -import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} - -import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort} -import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} - -class WithUARTIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { - val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } - (io_uart_pins_temp zip system.uart).map { case (io, sysio) => - io <> sysio - } - (io_uart_pins_temp, Nil) - } -}) +import chipyard.iobinders.{OverrideIOBinder} class WithGPIOIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryGPIOModuleImp) => { @@ -49,25 +18,6 @@ class WithGPIOIOPassthrough extends OverrideIOBinder({ } }) -class WithSPIIOPassthrough extends OverrideLazyIOBinder({ - (system: HasPeripherySPI) => { - // attach resource to 1st SPI - ResourceBinding { - Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) - } - - InModuleBody { - system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { - val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } - (io_spi_pins_temp zip system.spi).map { case (io, sysio) => - io <> sysio - } - (io_spi_pins_temp, Nil) - } } - } - } -}) - class WithI2CIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryI2CModuleImp) => { val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } @@ -77,11 +27,3 @@ class WithI2CIOPassthrough extends OverrideIOBinder({ (io_i2c_pins_temp, Nil) } }) - -class WithTLIOPassthrough extends OverrideIOBinder({ - (system: CanHaveMasterTLMemPort) => { - val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") - io_tl_mem_pins_temp <> system.mem_tl - (Seq(io_tl_mem_pins_temp), Nil) - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 9f51d2aa..080f6189 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -1,11 +1,10 @@ package chipyard.fpga.vcu118.bringup import chisel3._ -import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import sifive.fpgashells.shell.xilinx._ @@ -18,100 +17,31 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.harness._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} -import chipyard.iobinders.{HasIOBinders} +import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp} -case object DUTFrequencyKey extends Field[Double](100.0) - -class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { - - def dp = designParameters - - val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO" - val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") - - // Order matters; ddr depends on sys_clock - val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput())) - val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None - val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) - val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput())) - val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) - val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) - val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) - - val topDesign = LazyModule(p(BuildTop)(dp)) - - // place all clocks in the shell - dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } - - /*** Connect/Generate clocks ***/ - - // connect to the PLL that will generate multiple clocks - val harnessSysPLL = dp(PLLFactoryKey)() - sys_clock.get() match { - case Some(x : SysClockVCU118PlacedOverlay) => { - harnessSysPLL := x.node - } - } - - // create and connect to the dutClock - val dutClock = ClockSinkNode(freqMHz = dp(DUTFrequencyKey)) - val dutWrangler = LazyModule(new ResetWrangler) - val dutGroup = ClockGroup() - dutClock := dutWrangler.node := dutGroup := harnessSysPLL - - //InModuleBody { - // topDesign.module match { case td: LazyModuleImp => { - // td.clock := dutClock.in.head._1.clock - // td.reset := dutClock.in.head._1.reset - // } - // } - //} - - // connect ref clock to dummy sink node - ref_clock.get() match { - case Some(x : RefClockVCU118PlacedOverlay) => { - val sink = ClockSinkNode(Seq(ClockSinkParameters())) - sink := x.node - } - } - - // extra overlays +class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness { /*** UART ***/ require(dp(PeripheryUARTKey).size == 2) - // 1st UART goes to the VCU118 dedicated UART - - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) - dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - // 2nd UART goes to the FMC UART val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) + dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb)) /*** SPI ***/ require(dp(PeripherySPIKey).size == 2) - // 1st SPI goes to the VCU118 SDIO port - - val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) - val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) - // 2nd SPI goes to the ADI port val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) - val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) + val io_adi_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) + dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_adi_spi_bb)) /*** I2C ***/ @@ -123,7 +53,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends /*** GPIO ***/ val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 + val maxGPIOSupport = 32 // max gpio per gpio chip val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) }) @@ -133,62 +63,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends placer.place(GPIODesignInput(params, io_gpio_bb(i))) } - /*** DDR ***/ - - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) - - // connect 1 mem. channel to the FPGA DDR - val inParams = topDesign match { case td: ChipTop => - td.lazySystem match { case lsys: CanHaveMasterTLMemPort => - lsys.memTLNode.edges.in(0) - } - } - val ddrClient = TLClientNode(Seq(inParams.master)) - ddrPlaced.overlayOutput.ddr := ddrClient - // module implementation override lazy val module = new BringupVCU118FPGATestHarnessImp(this) } -class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { - - val outer = _outer - - val reset = IO(Input(Bool())) - _outer.xdc.addPackagePin(reset, "L19") - _outer.xdc.addIOStandard(reset, "LVCMOS12") - - val reset_ibuf = Module(new IBUF) - reset_ibuf.io.I := reset - - val sysclk: Clock = _outer.sys_clock.get() match { - case Some(x: SysClockVCU118PlacedOverlay) => x.clock - } - - val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) - _outer.sdc.addAsyncPath(Seq(powerOnReset)) - - val ereset: Bool = _outer.chiplink.get() match { - case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n - case _ => false.B - } - - _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) - - // cy stuff - val harnessClock = _outer.dutClock.in.head._1.clock - val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) - val dutReset = harnessReset - val success = false.B - - childClock := harnessClock - childReset := harnessReset - - // harness binders are non-lazy - _outer.topDesign match { case d: HasTestHarnessFunctions => - d.harnessFunctions.foreach(_(this)) - } - _outer.topDesign match { case d: HasIOBinders => - ApplyHarnessBinders(this, d.lazySystem, d.portMap) - } +class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { + val bringupOuter = _outer } diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 25eae85e..7e2121ee 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 25eae85e711d650a305eb1cd923421a2872fcc56 +Subproject commit 7e2121ee26e614f2144a9e4c67c440773aa7544d From f4d70128c007807ba7617f5c4fd47ebaf59c49c4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 28 Oct 2020 15:34:14 -0700 Subject: [PATCH 289/457] Remove redundant ChipTop reset synchronizer --- generators/chipyard/src/main/scala/Clocks.scala | 4 +--- .../chipyard/src/main/scala/clocking/ResetSynchronizer.scala | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 3c9e70cd..e4d48b59 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -28,14 +28,12 @@ object GenerateReset { val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true) - val reset_wire = ResetCatchAndSync(clock, async_reset_wire.asBool()) - chiptop.iocells ++= resetIOCell chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { reset_io := th.dutReset Nil }) - reset_wire + async_reset_wire } } diff --git a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala index 13a593c5..2ba8e855 100644 --- a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala +++ b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync} * Instantiates a reset synchronizer on all clock-reset pairs in a clock group */ class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { - val node = ClockGroupIdentityNode() + val node = ClockGroupAdapterNode() lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) => From 7b83da054a4609202578168a8796df40a21ccc1d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 28 Oct 2020 16:18:22 -0700 Subject: [PATCH 290/457] Clean up HarnessBinders --- .../src/main/scala/HarnessBinders.scala | 72 ++++++++----------- 1 file changed, 31 insertions(+), 41 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 2ff8ad94..02ab3732 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -27,19 +27,22 @@ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvon import scala.reflect.{ClassTag} -case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]]]( - Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]]().withDefaultValue((t: Any, th: HasHarnessSignalReferences, d: Seq[Data]) => Nil) +case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Unit]]( + Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Unit]().withDefaultValue((t: Any, th: HasHarnessSignalReferences, d: Seq[Data]) => ()) ) object ApplyHarnessBinders { - def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters) = { + def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters): Unit = { val pm = portMap.withDefaultValue(Nil) - p(HarnessBinders).map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + p(HarnessBinders).foreach { case (s, f) => + f(sys, th, pm(s)) + f(sys.module, th, pm(s)) + } } } // The ClassTags here are necessary to overcome issues arising from type erasure -class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit systemTag: ClassTag[T], harnessTag: ClassTag[S], portTag: ClassTag[U]) extends Config((site, here, up) => { +class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Unit) => (T, S, Seq[U]) => Unit)(implicit systemTag: ClassTag[T], harnessTag: ClassTag[S], portTag: ClassTag[U]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (systemTag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { val pts = ports.collect({case p: U => p}) @@ -49,71 +52,68 @@ class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T case th: S => t match { case system: T => composer(upfn)(system, th, pts) - case _ => Nil + case _ => } - case _ => Nil + case _ => } }) ) }) -class OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) +class OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Unit) (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) - extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => fn) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Unit) => fn) -class ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) +class ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Unit) (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) - extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => (t, th, p) => upfn(t, th, p) ++ fn(t, th, p)) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Unit) => (t, th, p) => { + upfn(t, th, p) + fn(t, th, p) + }) class WithGPIOTiedOff extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Analog]) => { + (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => { ports.foreach { _ <> AnalogConst(0) } - Nil } }) // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { UARTAdapter.connect(ports)(system.p) - Nil } }) // DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ - (system: HasPeripherySPIFlashModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { + (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p) - Nil } }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } - Nil } }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } - Nil } }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => withClockAndReset(n.clock, th.harnessReset) { NicLoopback.connect(Some(n.bits), p(NICKey)) } } - Nil } }) @@ -121,7 +121,6 @@ class WithSimNetwork extends OverrideHarnessBinder({ (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } - Nil } }) @@ -135,7 +134,6 @@ class WithSimAXIMem extends OverrideHarnessBinder({ } mem.io_axi4.head <> port.bits } - Nil } }) @@ -150,7 +148,6 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ mem.io.clock := port.clock mem.io.reset := port.reset } - Nil } }) @@ -164,26 +161,23 @@ class WithSimAXIMMIO extends OverrideHarnessBinder({ } mmio_mem.io_axi4.head <> port.bits } - Nil } }) class WithTieOffInterrupts extends OverrideHarnessBinder({ - (system: HasExtInterruptsModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UInt]) => { + (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => { ports.foreach { _ := 0.U } - Nil } }) class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ - (system: CanHaveSlaveAXI4Port, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { ports.foreach({ p => p := DontCare; p.bits.tieoff() }) - Nil } }) class WithSimDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebug, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebug, th: HasHarnessSignalReferences, ports: Seq[Data]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { case d: ClockedDMIIO => @@ -195,12 +189,11 @@ class WithSimDebug extends OverrideHarnessBinder({ when (dtm_success) { th.success := true.B } val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) } - Nil } }) class WithTiedOffDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebug, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebug, th: HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case j: JTAGIO => j.TCK := true.B.asClock @@ -220,13 +213,12 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ a.psel := false.B a.penable := false.B } - Nil } }) class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -236,7 +228,7 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ }) class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -247,15 +239,13 @@ class WithSimSerial extends OverrideHarnessBinder({ }) class WithTraceGenSuccess extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Bool]) => { + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } - Nil } }) class WithSimDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } - Nil } }) From 3e4fddbc6984fa2dbbae3940dc82dea2de944bad Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Mon, 2 Nov 2020 22:30:06 +0000 Subject: [PATCH 291/457] make hammer work according to docs --- vlsi/Makefile | 2 +- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 0e1989dd..7a38f881 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -32,7 +32,7 @@ ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ example-nangate45.yml,\ example-asap7.yml) -HAMMER_EXEC ?= example-vlsi +HAMMER_EXEC ?= ./example-vlsi VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= chiptop VLSI_OBJ_DIR ?= $(vlsi_dir)/build diff --git a/vlsi/hammer b/vlsi/hammer index bed4d340..8fd14864 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit bed4d34094fa4c72db37a0066050c475eb5e37b2 +Subproject commit 8fd1486499b875d56f09b060f03a62775f0a6aa7 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index d905828d..3e5b046b 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit d905828d68aeb4ff5619418807a8aa6d7376d796 +Subproject commit 3e5b046be13fb3fd4e00402acfbfd295a5da0a68 From 0f3f283893253af195444509292d1da7a00c6794 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Mon, 2 Nov 2020 22:31:24 +0000 Subject: [PATCH 292/457] example ymls --- vlsi/example-design.yml | 14 ++++++++++++++ vlsi/example-tech.yml | 10 ++++++++++ vlsi/example-tools.yml | 24 ++++++++++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 vlsi/example-design.yml create mode 100644 vlsi/example-tech.yml create mode 100644 vlsi/example-tools.yml diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml new file mode 100644 index 00000000..c277c916 --- /dev/null +++ b/vlsi/example-design.yml @@ -0,0 +1,14 @@ +# General Hammer Inputs Related to the Design and Build System + +# Generate Make include to aid in flow +vlsi.core.build_system: make +vlsi.core.max_threads: 12 + +# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info +vlsi.inputs.power_spec_mode: "auto" +vlsi.inputs.power_spec_type: "cpf" + +# Specify clock signals +vlsi.inputs.clocks: [ + {name: "clock", period: "1ns", uncertainty: "0.1ns"} +] diff --git a/vlsi/example-tech.yml b/vlsi/example-tech.yml new file mode 100644 index 00000000..a5de62f9 --- /dev/null +++ b/vlsi/example-tech.yml @@ -0,0 +1,10 @@ +# Technology Setup +vlsi.core.technology: +vlsi.core.technology_path: ["hammer--plugin"] +vlsi.core.technology_path_meta: append + +# tech node measured in nm (required because of licensing) +vlsi.core.node: + +# technology files installation directory +technology..install_dir: "" diff --git a/vlsi/example-tools.yml b/vlsi/example-tools.yml new file mode 100644 index 00000000..52f5e373 --- /dev/null +++ b/vlsi/example-tools.yml @@ -0,0 +1,24 @@ +# SRAM Compiler compiler options +vlsi.core.sram_generator_tool: "sram_compiler" +# You should specify a location for the SRAM generator in the tech plugin +vlsi.core.sram_generator_tool_path: [] +vlsi.core.sram_generator_tool_path_meta: "append" + +# Tool options. Replace with your tool plugin of choice. +# Genus options +vlsi.core.synthesis_tool: "genus" +vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"] +vlsi.core.synthesis_tool_path_meta: "append" +synthesis.genus.version: "1813" +# Innovus options +vlsi.core.par_tool: "innovus" +vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] +vlsi.core.par_tool_path_meta: "append" +par.innovus.version: "181" +par.innovus.design_flow_effort: "standard" +par.inputs.gds_merge: true +# Calibre options +vlsi.core.drc_tool: "calibre" +vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] +vlsi.core.lvs_tool: "calibre" +vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] From 8bf23177d34cb6f0f140a3d664029997499fd88b Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 2 Nov 2020 14:32:39 -0800 Subject: [PATCH 293/457] VLSI docs revamp midpoint --- docs/Tools/Barstools.rst | 2 + docs/VLSI/Basic-Flow.rst | 127 +++++++++++++++++++++++++++++++++++++++ docs/VLSI/Tutorial.rst | 2 +- 3 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 docs/VLSI/Basic-Flow.rst diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 9089c947..e2fbac70 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -1,3 +1,5 @@ +.. _barstools: + Barstools =============================== diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst new file mode 100644 index 00000000..96504097 --- /dev/null +++ b/docs/VLSI/Basic-Flow.rst @@ -0,0 +1,127 @@ +.. _hammer_basic_flow: + +Using Hammer To Place and Route a Custom Block +================================================= + +.. IMPORTANT:: In order to use the Hammer VLSI flow, you need access to Hammer tools and technology plugins. You can obtain these by emailing hammer-plugins-access@lists.berkeley.edu with a request for which plugin(s) you would like access to. + +Initialize the Hammer Plug-ins +---------------------------------- +In the Chipyard root, run: + +.. code-block:: shell + + ./scripts/init-vlsi.sh + +This will pull the Hammer & CAD tool plugin submodules, assuming the technology plugins are available on github. +Currently only the asap7 technology plugin is available on github. +If you have additional private technology plugins (this is a typical use-case for proprietry process technologies with require NDAs and secure servers), you can clone them directly +into VLSI directory with the name ``hammer--plugin``. +For example, for an imaginary process technology called tsmintel3: + +.. code-block:: shell + + cd vlsi + git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git + + +Next, we define the Hammer environment into the shell: + +.. code-block:: shell + + cd vlsi # (if you haven't done so yet) + export HAMMER_HOME=$PWD/hammer + source $HAMMER_HOME/sourceme.sh + + +Setting up the Hammer Configuration Files +-------------------------------------------- + +The first configuration files that needs to be set up is the Hammer environment configuration files ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you need to fill the paths only for the tools that you will be using. +If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`Advanced Environment Setup` segment of this documentation page. + +Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``nangate45`` +OpenRoad example), the generally applicable way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design. +The ``vlsi`` directory includes three such example configuration files matching the three concerns: ``example-tools.yml``, ``example-tech.yml``, and ``example-design.yml``. + +The ``example-tools.yml`` file configures which EDA tools hammer will use. This example files uses Cadence Innovus, Genus and Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). + +The ``example-design.yml`` file contrain basic build system information (how many cores/threads to use, etc.), as well as configuration that are specific to the design we are working on such as clock signal, power modes, and additional contraints that we will add later on. + +Finally, the ``example-tech`` file is a template file for a process technology plugin configuration. We will copy this file, and replace its fields with the appropriate process technology details for the tech plugin that we have access to. For example, for the ``asap7`` tech plugin we will replace the field with "asap7", the Node size "N" with "7", and the path to the process technology files installation directory. + +We recommend copying these example configuration files and customizing them with a different name, so you can have different configuration files for different process technologies and designs. + + +Building the Design +--------------------- +After we have set the configuration files, we will now elaborate our Chipyard Chisel design into Verilog, while also performing the required transformations in order to make the Verilog VLSI-friendly. +Additionally, we will automatically generate another set of Hammer configuration files matching to this design, which will be used in order to configure the physical design tools. +We will do so by calling ``make buildfile`` with appropriate Chipyard configuration variables and Hammer configuration files. +As in the rest of the Chipyard flows, we specify our SoC configuration using the ``CONFIG`` make variable. +However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module. +Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on. +The makefile will automatically call tools such as Barstools and the MacroCopmiler (:ref:`barstools`) in order to make the generated Verilog more VLSI friendly. +By default, the MacroCopmiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are wokring with a new process technology are prefer to work with flipflop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, the ASAP7 process technology does not have associated SRAMs, and therefore the ASAP7 Hammer tutorial (:ref:`tutorial`) uses the ``MACROCOMPILER_MODE='--mode synflops'`` option. + +We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. + +Hence, if we want to monolitically place and route the entire SoC, the relevant command would be +.. code-block:: shell + + make buildfile CONFIG= tech_name= INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + +In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, the relevant command would be +.. code-block:: shell + + make buildfile CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + +Running the VLSI Flow +--------------------- + +Running a basic VLSI flow using the Hammer default configurations is fairly simple, and consists of simpele ``Make`` command with the previously mentioned Make variables. + +Synthesis +^^^^^^^^^ + +In order to run synthesis, we run ``make syn`` with the matching Make variables. +Post-synthesis logs and collateral will be saved in ``build/syn-rundir``. The raw QoR data wil be found in ``build/syn-rundir/reports``. + +Hence, if we want to monolitically synthesize the entire SoC, the relevant command would be +.. code-block:: shell + + make syn CONFIG= tech_name= INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + +In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, the relevant command would be +.. code-block:: shell + + make syn CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + + + +Customizing Your VLSI Flow in Hammer +---------------------------------------- + +Advanced Environment Setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +If you have access to a shared LSF cluster and you would like Hammer to submit it's compute-intensive jobs to the LSF cluster rather than your login machine, you can add the following code segment to your ``env.yml`` file (completing the relevant values for the bsub binary path, the number of CPUs requested, and the requested LSF queue): + +.. code-block:: shell + + #submit command (use LSF) + vlsi.submit: + command: "lsf" + settings: [{"lsf": { + "bsub_binary": "", + "num_cpus": , + "queue": "", + "extra_args": ["-R", "span[hosts=1]"] + } + }] + settings_meta: "append" + + +example-vlsi +^^^^^^^^^^^^ +This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 406cee46..7e44ebb7 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -30,7 +30,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * Verilog wrapper around the accelerator and dummy hard macro. -* example.yml +* example-asap7.yml * Hammer IR for this tutorial. From 57a0bc5dfcbca2e76cbbb14caa1590ab283a2bfe Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 3 Nov 2020 12:14:02 -0500 Subject: [PATCH 294/457] Fix zsh compatibility in init-submodules-no-rv-tools (#705) --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index cede5e47..c861658d 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -77,6 +77,6 @@ if [ ! -f ./software/firemarshal/marshal-config.yaml ]; then fi echo "# line auto-generated by init-submodules-no-riscv-tools.sh" >> env.sh -echo '__DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"' >> env.sh +echo '__DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]:-${(%):-%x}}")")"' >> env.sh echo "PATH=\$__DIR/bin:\$PATH" >> env.sh echo "PATH=\$__DIR/software/firemarshal:\$PATH" >> env.sh From 946a191221cdca685074ffe28df1a2cf0218aaa3 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 3 Nov 2020 12:14:18 -0500 Subject: [PATCH 295/457] [clocking] Provide a default div for ClockDividerN sv implementation (#706) --- generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv index 4d940d06..1e09a078 100644 --- a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv +++ b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv @@ -5,7 +5,7 @@ * Duty cycle is 100 * (ceil(DIV / 2)) / DIV. */ -module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in); +module ClockDividerN #(parameter DIV = 1)(output logic clk_out = 1'b0, input clk_in); localparam CWIDTH = $clog2(DIV); localparam LOW_CYCLES = DIV / 2; From f387634a4128762c698fe79dde6e723ca2d3f817 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 2 Nov 2020 10:38:37 -0800 Subject: [PATCH 296/457] [clocking] Bound SimplePllConfiguration by maximum reference freq --- .../src/main/scala/clocking/DividerOnlyClockGenerator.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index fb816c35..bbf05f38 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -16,12 +16,13 @@ import scala.collection.immutable.ListMap object FrequencyUtils { def computeReferenceFrequencyMHz( requestedOutputs: Seq[ClockParameters], - maximumAllowableDivisor: Int = 0xFFFF): ClockParameters = { + maximumAllowableFreqMHz: Double = 8000.0): ClockParameters = { require(requestedOutputs.nonEmpty) require(!requestedOutputs.contains(0.0)) val freqs = requestedOutputs.map(f => BigInt(Math.round(f.freqMHz * 1000 * 1000))) val refFreq = freqs.reduce((a, b) => a * b / a.gcd(b)).toDouble / (1000 * 1000) - assert((refFreq / freqs.min.toDouble) < maximumAllowableDivisor.toDouble) + assert(refFreq < maximumAllowableFreqMHz, + s"Reference frequency ${refFreq} exceeds maximum allowable value of ${maximumAllowableFreqMHz} MHz") ClockParameters(refFreq) } } From aa4a44925e2bdf95296f26b6bd9a474529785f77 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 2 Nov 2020 10:40:39 -0800 Subject: [PATCH 297/457] [clocking] Add ScalaTests for the divider-only PLL configurator --- .../clocking/SimplePllConfigurationSpec.scala | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala diff --git a/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala new file mode 100644 index 00000000..897ab0f4 --- /dev/null +++ b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala @@ -0,0 +1,21 @@ +//See LICENSE for license details. +package chipyard.clocking + +import freechips.rocketchip.prci._ + +class SimplePllConfigurationSpec extends org.scalatest.FlatSpec { + + def conf(freqMHz: Iterable[Double]): SimplePllConfiguration = new SimplePllConfiguration("test", + freqMHz.map({ f => ClockSinkParameters( + name = Some(s"desiredFreq_$f"), + take = Some(ClockParameters(f))) }).toSeq) + + def tryConf(freqMHz: Double*): Unit = { + val freqStr = freqMHz.mkString(", ") + it should s"configure for ${freqStr} MHz" in { conf(freqMHz) } + } + + tryConf(3200.0, 1600.0, 1000.0, 100.0) + tryConf(3200.0, 1600.0) + tryConf(3200.0, 1066.7) +} From f504b7a0f50d04eafaad400dc977c95b5398e2a5 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 3 Nov 2020 09:13:18 -0800 Subject: [PATCH 298/457] [clocking] Improve reference clock selection using a multiple-of-fastest strategy --- .../clocking/DividerOnlyClockGenerator.scala | 71 +++++++++++++++---- .../clocking/SimplePllConfigurationSpec.scala | 24 ++++--- .../firechip/src/main/scala/FireSim.scala | 1 + 3 files changed, 76 insertions(+), 20 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index bbf05f38..2b666196 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -14,21 +14,65 @@ import scala.collection.immutable.ListMap * TODO: figure out how much division is acceptable in our simulators and redefine this. */ object FrequencyUtils { - def computeReferenceFrequencyMHz( + /** + * Adds up the squared error between the generated clocks (refClock / [integer] divider) + * and the requested frequencies. + * + * @param refMHz The candidate reference clock + * @param desiredFreqMHz A list of the requested output frequencies + */ + def squaredError(refMHz: Double, desiredFreqMHz: List[Double], sum: Double = 0.0): Double = desiredFreqMHz match { + case Nil => sum + case desired :: xs => + val divider = Math.round(refMHz / desired) + val termError = ((refMHz / divider) - desired) / desired + squaredError(refMHz, xs, sum + termError * termError) + } + + /** + * Picks a candidate reference frequency by doing a brute-force search over + * multiples of the fastest requested clock. Choose the smallest multiple that + * has an RMS error (across all output frequencies) that is: + * 1) zero or failing that, + * 2) is within the relativeThreshold of the best or is less than the absoluteThreshold + * + * @param requestedOutputs The desired output frequencies in MHz + * @param maximumAllowableFreqMHz The maximum allowable reference in MHz + * @param relativeThreshold See above + * @param absoluteThreshold See above + */ + def computeReferenceAsMultipleOfFastestClock( requestedOutputs: Seq[ClockParameters], - maximumAllowableFreqMHz: Double = 8000.0): ClockParameters = { + maximumAllowableFreqMHz: Double, + relativeThreshold: Double = 1.10, + absoluteThreshold: Double = 0.01): ClockParameters = { + require(requestedOutputs.nonEmpty) require(!requestedOutputs.contains(0.0)) - val freqs = requestedOutputs.map(f => BigInt(Math.round(f.freqMHz * 1000 * 1000))) - val refFreq = freqs.reduce((a, b) => a * b / a.gcd(b)).toDouble / (1000 * 1000) - assert(refFreq < maximumAllowableFreqMHz, - s"Reference frequency ${refFreq} exceeds maximum allowable value of ${maximumAllowableFreqMHz} MHz") - ClockParameters(refFreq) + val requestedFreqs = requestedOutputs.map(_.freqMHz) + val fastestFreq = requestedFreqs.max + require(fastestFreq < maximumAllowableFreqMHz) + + val candidateFreqs = + Seq.tabulate(Math.ceil(maximumAllowableFreqMHz / fastestFreq).toInt)(i => (i + 1) * fastestFreq) + val errorTuples = candidateFreqs.map { f => + f -> Math.sqrt(squaredError(f, requestedFreqs.toList) / requestedFreqs.size) + } + val minError = errorTuples.map(_._2).min + val viableFreqs = errorTuples.collect { + case (f, error) if (error <= minError * relativeThreshold) || (minError > 0 && error < absoluteThreshold) => f + } + ClockParameters(viableFreqs.min) } } -class SimplePllConfiguration(name: String, val sinks: Seq[ClockSinkParameters]) { - val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz +class SimplePllConfiguration( + name: String, + val sinks: Seq[ClockSinkParameters], + maximumAllowableFreqMHz: Double = 16000.0 ) { + val referenceFreqMHz = FrequencyUtils.computeReferenceAsMultipleOfFastestClock( + sinks.flatMap(_.take), + maximumAllowableFreqMHz).freqMHz val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*) private val preamble = s""" @@ -41,8 +85,10 @@ class SimplePllConfiguration(name: String, val sinks: Seq[ClockSinkParameters]) } val summaryString = preamble + outputSummaries.mkString("\n") - ElaborationArtefacts.add(s"${name}.freq-summary", summaryString) - println(summaryString) + def emitSummaries(): Unit = { + ElaborationArtefacts.add(s"${name}.freq-summary", summaryString) + println(summaryString) + } } case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName) @@ -54,7 +100,7 @@ case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValN "All output clocks in group must set their take parameters. Use a ClockGroupDealiaser") ClockSinkParameters( name = Some(s"${pllName}_reference_input"), - take = Some(FrequencyUtils.computeReferenceFrequencyMHz(u.head.members.flatMap(_.take)))) } + take = Some(ClockParameters(new SimplePllConfiguration(pllName, u.head.members).referenceFreqMHz))) } ) /** @@ -79,6 +125,7 @@ class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName val referenceFreq = refSinkParam.take.get.freqMHz val pllConfig = new SimplePllConfiguration(pllName, outSinkParams.members) + pllConfig.emitSummaries() val dividedClocks = mutable.HashMap[Int, Clock]() def instantiateDivider(div: Int): Clock = { diff --git a/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala index 897ab0f4..0abe7c50 100644 --- a/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala +++ b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala @@ -5,17 +5,25 @@ import freechips.rocketchip.prci._ class SimplePllConfigurationSpec extends org.scalatest.FlatSpec { - def conf(freqMHz: Iterable[Double]): SimplePllConfiguration = new SimplePllConfiguration("test", + def genConf(freqMHz: Iterable[Double]): SimplePllConfiguration = new SimplePllConfiguration( + "testPLL", freqMHz.map({ f => ClockSinkParameters( name = Some(s"desiredFreq_$f"), - take = Some(ClockParameters(f))) }).toSeq) + take = Some(ClockParameters(f))) }).toSeq, + maximumAllowableFreqMHz = 16000.0) - def tryConf(freqMHz: Double*): Unit = { - val freqStr = freqMHz.mkString(", ") - it should s"configure for ${freqStr} MHz" in { conf(freqMHz) } + def trySuccessfulConf(requestedFreqs: Seq[Double], expected: Double): Unit = { + val freqStr = requestedFreqs.mkString(", ") + it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in { + val conf = genConf(requestedFreqs) + conf.emitSummaries + assert(expected == conf.referenceFreqMHz) + } } - tryConf(3200.0, 1600.0, 1000.0, 100.0) - tryConf(3200.0, 1600.0) - tryConf(3200.0, 1066.7) + trySuccessfulConf(Seq(3200.0, 1600.0, 1000.0, 100.0), 16000.0) + trySuccessfulConf(Seq(3200.0, 1600.0), 3200.0) + trySuccessfulConf(Seq(3200.0, 1066.7), 3200.0) + trySuccessfulConf(Seq(100, 50, 6.67), 100) + trySuccessfulConf(Seq(1, 2, 3, 5, 7, 11, 13).map(_ * 10.0), 1560.0) } diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index acbdbc6b..ff765970 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -118,6 +118,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { } val pllConfig = new SimplePllConfiguration("FireSim RationalClockBridge", clockGroupEdge.sink.members) + pllConfig.emitSummaries val rationalClockSpecs = for ((sinkP, division) <- pllConfig.sinkDividerMap) yield { RationalClock(sinkP.name.get, 1, division) } From 16c34e2cf3044152e231d4dbe2f8ba69b4fee740 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 11:46:02 -0800 Subject: [PATCH 299/457] Bump Dromajo for old glibc --- tools/dromajo/dromajo-src | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dromajo/dromajo-src b/tools/dromajo/dromajo-src index 56e2ff46..09fbef45 160000 --- a/tools/dromajo/dromajo-src +++ b/tools/dromajo/dromajo-src @@ -1 +1 @@ -Subproject commit 56e2ff46b70521916c362799517f4ed8e67e9e88 +Subproject commit 09fbef4565429f641a7eb93f190ad0e45e11d7f8 From 5e3d1a605d787b7bd02a2361ababd4954c7a7656 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 11:57:23 -0800 Subject: [PATCH 300/457] Add --ignore-qemu flag to toolchains | Prepare QEMU when it builds --- scripts/build-toolchains.sh | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 2685872e..9ceb8808 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -20,6 +20,7 @@ usage() { echo "Options" echo " --prefix PREFIX : Install destination. If unset, defaults to $(pwd)/riscv-tools-install" echo " or $(pwd)/esp-tools-install" + echo " --ignore-qemu : Ignore installing QEMU" echo " --help -h : Display this message" exit "$1" } @@ -34,6 +35,7 @@ die() { TOOLCHAIN="riscv-tools" EC2FASTINSTALL="false" +IGNOREQEMU="false" RISCV="" # getopts does not support long options, and is inflexible @@ -45,6 +47,9 @@ do -p | --prefix ) shift RISCV=$(realpath $1) ;; + --ignore-qemu ) + shift + IGNOREQEMU="true" ;; riscv-tools | esp-tools) TOOLCHAIN=$1 ;; ec2fast ) @@ -109,7 +114,7 @@ else *) false ;; esac; ) || die 'obsolete make version; need GNU make 4.x or later' - module_prepare riscv-gnu-toolchain qemu + module_prepare riscv-gnu-toolchain module_build riscv-gnu-toolchain --prefix="${RISCV}" --with-cmodel=medany echo '==> Building GNU/Linux toolchain' module_make riscv-gnu-toolchain linux @@ -128,7 +133,9 @@ module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf +if [ "${IGNOREQEMU}" = false ] ; then SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu +fi # make Dromajo git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src From a2ebbee2ac21d2703995b67daea8a18cc6713271 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 15:05:11 -0800 Subject: [PATCH 301/457] Rename Ariane to CVA6 --- .circleci/check-commit.sh | 2 +- .circleci/config.yml | 6 +- .circleci/defaults.sh | 4 +- .circleci/run-tests.sh | 2 +- .gitmodules | 6 +- README.md | 6 +- build.sbt | 4 +- common.mk | 4 +- docs/Chipyard-Basics/Chipyard-Components.rst | 4 +- docs/Customization/Custom-Core.rst | 70 +++++++++---------- docs/Generators/{Ariane.rst => CVA6.rst} | 10 +-- docs/Generators/index.rst | 2 +- generators/ariane | 1 - .../src/main/scala/ConfigFragments.scala | 4 +- .../chipyard/src/main/scala/TestSuites.scala | 3 - .../src/main/scala/config/ArianeConfigs.scala | 19 ----- .../src/main/scala/config/CVA6Configs.scala | 19 +++++ .../src/main/scala/example/TutorialTile.scala | 14 ++-- generators/cva6 | 1 + .../src/main/scala/BridgeBinders.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 8 +-- .../src/test/scala/ScalaTestSuite.scala | 2 +- scripts/tutorial-patches/build.sbt.patch | 10 +-- sims/firesim | 2 +- sims/verilator/Makefile | 8 +-- 25 files changed, 105 insertions(+), 108 deletions(-) rename docs/Generators/{Ariane.rst => CVA6.rst} (59%) delete mode 160000 generators/ariane delete mode 100644 generators/chipyard/src/main/scala/config/ArianeConfigs.scala create mode 100644 generators/chipyard/src/main/scala/config/CVA6Configs.scala create mode 160000 generators/cva6 diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 68cc975c..2660fa49 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") +submodules=("cva6" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then diff --git a/.circleci/config.yml b/.circleci/config.yml index 4ee84ced..6e74b9d5 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -234,12 +234,12 @@ jobs: - run-tests: group-key: "group-cores" project-key: "chipyard-boom" - chipyard-ariane-run-tests: + chipyard-cva6-run-tests: executor: main-env steps: - run-tests: group-key: "group-cores" - project-key: "chipyard-ariane" + project-key: "chipyard-cva6" timeout: "30m" chipyard-sodor-run-tests: executor: main-env @@ -431,7 +431,7 @@ workflows: - chipyard-boom-run-tests: requires: - prepare-chipyard-cores - - chipyard-ariane-run-tests: + - chipyard-cva6-run-tests: requires: - prepare-chipyard-cores - chipyard-sodor-run-tests: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e628de7b..c0bce62d 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop" +grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -67,7 +67,7 @@ mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" -mapping["chipyard-ariane"]=" CONFIG=ArianeConfig" +mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig" mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index da5029b5..5ea53c78 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -91,7 +91,7 @@ case $1 in tracegen-boom) run_tracegen ${mapping[$1]} ;; - chipyard-ariane) + chipyard-cva6) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv ;; chipyard-sodor) diff --git a/.gitmodules b/.gitmodules index f374fa1f..d9dbe85f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -113,9 +113,9 @@ [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git -[submodule "generators/ariane"] - path = generators/ariane - url = https://github.com/ucb-bar/ariane-wrapper.git +[submodule "generators/cva6"] + path = generators/cva6 + url = git@github.com:ucb-bar/cva6-wrapper.git [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git diff --git a/README.md b/README.md index ab542cf3..11f1b8d5 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. @@ -35,7 +35,7 @@ If used for research, please cite Chipyard by the following publication: ``` @article{chipyard, - author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje}, + author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje}, journal={IEEE Micro}, title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, year={2020}, @@ -80,6 +80,6 @@ These additional publications cover many of the internal components used in Chip [rocket-chip]: https://github.com/freechipsproject/rocket-chip [boom]: https://github.com/riscv-boom/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ -[ariane]: https://github.com/pulp-platform/ariane/ +[cva6]: https://github.com/openhwgroup/cva6/ [gemmini]: https://github.com/ucb-bar/gemmini [nvdla]: http://nvdla.org/ diff --git a/build.sbt b/build.sbt index 750878ab..bbf7964f 100644 --- a/build.sbt +++ b/build.sbt @@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla, sodor) + gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -154,7 +154,7 @@ lazy val boom = conditionalDependsOn(project in file("generators/boom")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val ariane = (project in file("generators/ariane")) +lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/common.mk b/common.mk index 8ebc262c..ca34ffce 100644 --- a/common.mk +++ b/common.mk @@ -47,7 +47,7 @@ HELP_COMMANDS += \ # include additional subproject make fragments # see HELP_COMPILATION_VARIABLES ######################################################################################### -include $(base_dir)/generators/ariane/ariane.mk +include $(base_dir)/generators/cva6/cva6.mk include $(base_dir)/generators/tracegen/tracegen.mk include $(base_dir)/generators/nvdla/nvdla.mk include $(base_dir)/tools/dromajo/dromajo.mk @@ -103,7 +103,7 @@ $(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala $(FIRRTL_FILE) $(ANNO_FILE): generator_temp @echo "" > /dev/null -# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile +# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\ diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index c24f81ed..4ad39d51 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -20,9 +20,9 @@ Processor Cores An out-of-order RISC-V core. See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. -**Ariane Core** +**CVA6 Core** An in-order RISC-V core written in System Verilog. - See :ref:`Ariane Core` for more information. + See :ref:`CVA6 Core` for more information. Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index a76741ec..6da84cb7 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -6,14 +6,14 @@ Adding a custom core You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides step-by-step instructions on how to achieve this. -.. note:: +.. note:: RoCC is currently not supported by cores other than Rocket and BOOM. Please use Rocket or BOOM as the RoCC base core if you need to use RoCC. .. note:: - This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately - from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through + This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately + from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through GitHub issues! Wrap Verilog Module with Blackbox (Optional) @@ -30,15 +30,15 @@ This object is derived from``TileParams``, a trait containing the information ne their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``. ``TileParams`` holds the parameters for the tile, which include parameters for all components in the tile (e.g. -core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile. -They must be implemented as case classes with fields that can be overridden by -other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of -variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. +core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile. +They must be implemented as case classes with fields that can be overridden by +other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of +variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. -``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``, +``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``, where ``TileType`` is the tile class (see the next section). All custom cores will also need to implement ``instantiate()`` in their tile parameter class to return a new instance -of the tile class ``TileType``. +of the tile class ``TileType``. ``TileParams`` (in the file `BaseTile.scala `_) , ``InstantiableTileParams`` (in the file `BaseTile.scala `_), @@ -88,7 +88,7 @@ contains the following fields: val nBreakpoints: Int // # of hardware breakpoints supported (in RISC-V debug specs) val useBPWatch: Boolean // Support hardware breakpoints val nPerfCounters: Int // # of supported performance counters - val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension + val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension val haveFSDirty: Boolean // If true, the core will set FS field in mstatus CSR to dirty when appropriate val misaWritable: Boolean // Support writable misa CSR (like variable instruction bits) val haveCFlush: Boolean // Rocket specific: enables Rocket's custom instruction extension to flush the cache @@ -96,7 +96,7 @@ contains the following fields: val mtvecInit: Option[BigInt] // mtvec CSR (of V extension) initial value val mtvecWritable: Boolean // If mtvec CSR is writable - // Normally, you don't need to change these values (except lrscCycles) + // Normally, you don't need to change these values (except lrscCycles) def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs def hasSupervisorMode: Boolean = useSupervisor || useVM @@ -113,19 +113,19 @@ contains the following fields: def eLen(xLen: Int, fLen: Int): Int = xLen max fLen def vMemDataBits: Int = 0 } - + case class FPUParams( - minFLen: Int = 32, // Minimum floating point length (no need to change) + minFLen: Int = 32, // Minimum floating point length (no need to change) fLen: Int = 64, // Maximum floating point length, use 32 if only single precision is supported divSqrt: Boolean = true, // Div/Sqrt operation supported sfmaLatency: Int = 3, // Rocket specific: Fused multiply-add pipeline latency (single precision) dfmaLatency: Int = 4 // Rocket specific: Fused multiply-add pipeline latency (double precision) ) -Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some -implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore +Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some +implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore any fields marked "Rocket specific" and use their default values; however, if you need to store additional information -with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of +with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of creating your own custom fields. You will also need a ``CanAttachTile`` class to add the tile config into the config system, with the following format: @@ -144,14 +144,14 @@ from the parameters in this class for every such class it found. value may break Chipyard components that rely on them (e.g. an inaccurate indication of supported ISA extension will result in an incorrect test suite being generated) as well as any custom modules that use them. ALWAYS document any fields you ignore or with altered usage in your core implementation, and if you are implementing other devices that - would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but + would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but you should document them if you use them. Create Tile Class ----------------- In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System -interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. +interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core, which specifies the constraints on the core's parameters and the connections with other diplomatic nodes. This class usually contains Diplomacy/TileLink code only, and Chisel RTL code should not go here. @@ -167,10 +167,10 @@ which allow the tile to accept external interrupt. A typical tile has the follow Connect TileLink Buses ---------------------- -Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters +Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters between the core's memory protocol and TileLink within the Tile module. in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by -Rocket chip: +Rocket chip: .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala :language: scala @@ -179,11 +179,11 @@ Rocket chip: Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also -provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the -source files in ``generators/rocket-chip/src/main/scala/amba`` for more info. +provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the +source files in ``generators/rocket-chip/src/main/scala/amba`` for more info. If you are using some other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba`` -as the template, but it is not recommended unless you are familiar with TileLink. +as the template, but it is not recommended unless you are familiar with TileLink. ``memAXI4Node`` is an AXI4 master node and is defined as following in our example: @@ -215,7 +215,7 @@ The implementation class contains the parameterized, actual hardware that depend framework according to the info provided in the Tile class. This class will normally contains Chisel RTL code. If your core is in Verilog, you will need to instantiate the black box class that wraps your Verilog implementation and connect it with the buses and other components. No Diplomacy/TileLink code should be in this class; you should only connect the IO signals in TileLink -interfaces or other diplomatically defined components, which are located in the tile class. +interfaces or other diplomatically defined components, which are located in the tile class. The implementation class for your core is of the following form: @@ -234,12 +234,12 @@ If you create an AXI4 node (or equivalents), you will need to connect them to yo Connect Interrupt ----------------- -Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. -In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and +Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. +In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and call ``decodeCoreInterrupts()`` with the object as the argument. Note that you should call this function in the implementation class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the ``TileInterrupts`` bundle -we create above. The definition of ``TileInterrupts`` -(in the file `Interrupts.scala `_) is +we create above. The definition of ``TileInterrupts`` +(in the file `Interrupts.scala `_) is .. code-block:: scala @@ -247,7 +247,7 @@ we create above. The definition of ``TileInterrupts`` val debug = Bool() // debug interrupt val mtip = Bool() // Machine level timer interrupt val msip = Bool() // Machine level software interrupt - val meip = Bool() // Machine level external interrupt + val meip = Bool() // Machine level external interrupt val seip = usingSupervisor.option(Bool()) // Valid only if supervisor mode is supported val lip = Vec(coreParams.nLocalInterrupts, Bool()) // Local interrupts } @@ -261,7 +261,7 @@ Here is an example on how to connect these signals in the implementation class: Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications`` from the implementation class: -(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file +(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file `Interrupts.scala `_) .. code-block:: scala @@ -290,12 +290,12 @@ the current config. An example of such config will be like this: :end-before: DOC include end: Config fragment Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``. -This config fragment simply appends new tile parameters to the end of this list. +This config fragment simply appends new tile parameters to the end of this list. Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`. -You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports). +You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports). -If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala`` -provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI -interface with the memory coherency system. +If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/CVA6Tile.scala`` +provides a concrete example of the CVA6 core. Note that this particular example includes additional nuances with respect to the interaction of the AXI +interface with the memory coherency system. diff --git a/docs/Generators/Ariane.rst b/docs/Generators/CVA6.rst similarity index 59% rename from docs/Generators/Ariane.rst rename to docs/Generators/CVA6.rst index e58f9dfc..6250c614 100644 --- a/docs/Generators/Ariane.rst +++ b/docs/Generators/CVA6.rst @@ -1,14 +1,14 @@ -Ariane Core +CVA6 Core ==================================== -`Ariane `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. -The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`. +`CVA6 `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. +The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`. The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface). -While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters). +While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters). .. Warning:: This target does not support Verilator simulation at this time. Please use VCS. -For more information, please refer to the `GitHub repository `__. +For more information, please refer to the `GitHub repository `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index cebb17e5..cfc7d601 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -27,7 +27,7 @@ so changes to the generators themselves will automatically be used when building TestChipIP SiFive-Generators SHA3 - Ariane + CVA6 NVDLA Sodor diff --git a/generators/ariane b/generators/ariane deleted file mode 160000 index 3a2eed60..00000000 --- a/generators/ariane +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 3a2eed602faac24e58a530db429f23f11810aae9 diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 68c41724..0db4ed4c 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import gemmini.{Gemmini, GemminiConfigs} import boom.common.{BoomTileAttachParams} -import ariane.{ArianeTileAttachParams} +import cva6.{CVA6TileAttachParams} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ @@ -120,7 +120,7 @@ class WithTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( trace = true)) - case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( trace = true)) case other => other } diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 8cdfd3c9..596337c0 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -7,9 +7,6 @@ import freechips.rocketchip.tile.{XLen, TileParams} import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} -import boom.common.{BoomTileAttachParams} -import ariane.{ArianeTileAttachParams} - /** * A set of pre-chosen regression tests */ diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala deleted file mode 100644 index 6e75ac54..00000000 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ /dev/null @@ -1,19 +0,0 @@ -package chipyard - -import chisel3._ - -import freechips.rocketchip.config.{Config} - -// --------------------- -// Ariane Configs -// --------------------- - -class ArianeConfig extends Config( - new ariane.WithNArianeCores(1) ++ // single Ariane core - new chipyard.config.AbstractConfig) - -class dmiArianeConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial - new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port - new ariane.WithNArianeCores(1) ++ // single Ariane core - new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala new file mode 100644 index 00000000..132a3009 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/CVA6Configs.scala @@ -0,0 +1,19 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} + +// --------------------- +// CVA6 Configs +// --------------------- + +class CVA6Config extends Config( + new cva6.WithNCVA6Cores(1) ++ // single CVA6 core + new chipyard.config.AbstractConfig) + +class dmiCVA6Config extends Config( + new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new cva6.WithNCVA6Cores(1) ++ // single CVA6 core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 1f58e5e4..9af2cb54 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -16,7 +16,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ -// Example parameter class copied from Ariane, not included in documentation but for compile check only +// Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure // out what parameters you need before you write the parameter class case class MyCoreParams( @@ -127,9 +127,9 @@ class MyTile( // TODO: Create TileLink nodes and connections here. // DOC include end: Tile class - + // DOC include start: AXI4 node - // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. + // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. val idBits = 4 val memAXI4Node = AXI4MasterNode( Seq(AXI4MasterPortParameters( @@ -160,17 +160,17 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ // TODO: Create the top module of the core and connect it with the ports in "outer" - // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like - // val core = Module(new MyCoreBlackbox(params...)) + // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like + // val core = Module(new MyCoreBlackbox(params...)) // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial // (link on the top of the page) for more info. - // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala + // You can look at https://github.com/ucb-bar/cva6-wrapper/blob/master/src/main/scala/CVA6Tile.scala // for a Verilog example. // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module // and connect appropriate signal. You can even implement this class as your top module. // See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and - // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for + // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for // Chisel example. // DOC include end: Implementation class diff --git a/generators/cva6 b/generators/cva6 new file mode 160000 index 00000000..27157f7b --- /dev/null +++ b/generators/cva6 @@ -0,0 +1 @@ +Subproject commit 27157f7bbdd1ebc395fc8e22e46b3118290fa188 diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index e4f691e2..0572fabd 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -22,7 +22,7 @@ import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotatio import firesim.bridges._ import firesim.configs.MemModelKey import tracegen.{TraceGenSystemModuleImp} -import ariane.ArianeTile +import cva6.CVA6Tile import boom.common.{BoomTile} import barstools.iocell.chisel._ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 719599f4..89ac8073 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -128,7 +128,7 @@ class FireSimQuadRocketConfig extends Config( new chipyard.QuadRocketConfig) // A stripped down configuration that should fit on all supported hosts. -// Flat to avoid having to reorganize the config class hierarchy to remove certain features +// Flat to avoid having to reorganize the config class hierarchy to remove certain features class FireSimSmallSystemConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ @@ -188,13 +188,13 @@ class SupernodeFireSimRocketConfig extends Config( new FireSimRocketConfig) //********************************************************************************** -//* Ariane Configurations +//* CVA6 Configurations //*********************************************************************************/ -class FireSimArianeConfig extends Config( +class FireSimCVA6Config extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ - new chipyard.ArianeConfig) + new chipyard.CVA6Config) //********************************************************************************** //* Multiclock Configurations diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index ea1627b7..64b9b4ba 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -110,7 +110,7 @@ class RocketMulticlockF1Tests extends FireSimTestSuite( "FireSimMulticlockRocketConfig", "WithSynthAsserts_BaseF1Config") -class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") +class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config") // This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call. class CITests extends Suites( diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index aa7f0bd4..cb289b6f 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -3,24 +3,24 @@ index 5d642c1..56f6fda 100644 --- a/build.sbt +++ b/build.sbt @@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) - + lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla, sodor) + gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(commonSettings) -@@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane")) +@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) .settings(commonSettings) - + -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) - .settings(commonSettings) +//lazy val sha3 = (project in file("generators/sha3")) +// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +// .settings(commonSettings) - + lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) diff --git a/sims/firesim b/sims/firesim index 1c76c446..57efb2ec 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1c76c446dab42b782f8128c3e7e56b4e9ab104d7 +Subproject commit 57efb2ec032a8c7afa2f458761cc79b2614180b5 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 211b5676..65e64179 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -91,7 +91,7 @@ VERILATOR_OPT_FLAGS := \ --output-split 10000 \ --output-split-cfuncs 100 -# default flags added for external IP (ariane/NVDLA) +# default flags added for external IP (cva6/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ -Wno-PINCONNECTEMPTY \ @@ -103,14 +103,14 @@ VERILOG_IP_VERILATOR_FLAGS := \ -Wno-style \ -Wall -# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA) +# normal flags used for chipyard builds (that are incompatible with vlog ip aka cva6/NVDLA) CHIPYARD_VERILATOR_FLAGS := \ --assert -# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used +# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ - if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \ + if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \ then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) From 94eceeb6249f477e2e257eebb8da757d4f5a345b Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 15:54:09 -0800 Subject: [PATCH 302/457] Use empty variable instead of t/f --- scripts/build-toolchains.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 9ceb8808..84fdbd45 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -35,7 +35,7 @@ die() { TOOLCHAIN="riscv-tools" EC2FASTINSTALL="false" -IGNOREQEMU="false" +IGNOREQEMU="" RISCV="" # getopts does not support long options, and is inflexible @@ -133,7 +133,7 @@ module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf -if [ "${IGNOREQEMU}" = false ] ; then +if [ -z "$IGNOREQEMU" ] ; then SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu fi From fc8c5e4b3019d65fc0ec0040ffdb7477c55daf6a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 18:02:49 -0800 Subject: [PATCH 303/457] Use HTTPS for submodules --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index d9dbe85f..7054c14f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -115,7 +115,7 @@ url = https://github.com/firesim/FireMarshal.git [submodule "generators/cva6"] path = generators/cva6 - url = git@github.com:ucb-bar/cva6-wrapper.git + url = https://github.com/ucb-bar/cva6-wrapper.git [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git From 59c9163bd5ca201b37ff7ed6633755e3811fbb23 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 18:37:26 -0800 Subject: [PATCH 304/457] Bump CVA6 for submodule fixes --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index 27157f7b..3f0513a9 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 27157f7bbdd1ebc395fc8e22e46b3118290fa188 +Subproject commit 3f0513a9bd9394047c7cc1fbd50ea5077bb2e36c From 9052b41328bcc76da1d6e9718edce4b4e044face Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 20:59:14 -0800 Subject: [PATCH 305/457] Re-ignore QEMU from gnu-toolchain | Avoid piping make version in toolchain build --- scripts/build-toolchains.sh | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 84fdbd45..1897d157 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -107,14 +107,18 @@ if [ "${EC2FASTINSTALL}" = true ] ; then git submodule deinit "${module}" || : else - "${MAKE}" --version | ( - read -r makever - case ${makever} in - 'GNU Make '[4-9]\.*|'GNU Make '[1-9][0-9]) ;; - *) false ;; - esac; ) || die 'obsolete make version; need GNU make 4.x or later' + MAKE_VER=$("${MAKE}" --version) || true + case ${MAKE_VER} in + 'GNU Make '[4-9]\.*) + ;; + 'GNU Make '[1-9][0-9]) + ;; + *) + die 'obsolete make version; need GNU make 4.x or later' + ;; + esac - module_prepare riscv-gnu-toolchain + module_prepare riscv-gnu-toolchain qemu module_build riscv-gnu-toolchain --prefix="${RISCV}" --with-cmodel=medany echo '==> Building GNU/Linux toolchain' module_make riscv-gnu-toolchain linux From 60cd99900264f57a3d075c6fc8ba214136e41c5c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 21:09:24 -0800 Subject: [PATCH 306/457] Bump CVA6 for Make fix --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index 3f0513a9..e3576371 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 3f0513a9bd9394047c7cc1fbd50ea5077bb2e36c +Subproject commit e35763717b25c08df215b10334fd2d40845e1912 From 0685812c342c31d735472ad13573ce8f21ed3687 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 10:30:00 -0800 Subject: [PATCH 307/457] Bump CVA6 --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index e3576371..8a11e2c9 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit e35763717b25c08df215b10334fd2d40845e1912 +Subproject commit 8a11e2c97627459d0449853447bfc7ca64608b82 From 356fa70c3c9a334f8ead280c61afd4d619f7a01d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 11:16:17 -0800 Subject: [PATCH 308/457] Update fpga-shells submodule | Fix Arty Makefile lines --- fpga/Makefile | 10 +++++----- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 -- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index 74af21e9..fa1f8e08 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -45,11 +45,11 @@ endif ifeq ($(SUB_PROJECT),arty) # TODO: Fix with Arty SBT_PROJECT ?= fpga_platforms - MODEL ?= BringupVCU118FPGATestHarness - VLOG_MODEL ?= BringupVCU118FPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup - CONFIG ?= RocketBringupConfig - CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup + MODEL ?= ArtyFPGATestHarness + VLOG_MODEL ?= ArtyFPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.arty + CONFIG ?= E300ArtyDevKitConfig + CONFIG_PACKAGE ?= chipyard.fpga.arty GENERATOR_PACKAGE ?= chipyard TB ?= none # unused TOP ?= ChipTop diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index db16d125..c861658d 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -39,8 +39,6 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.software/firemarshal.update none -# Disable updates to the local FPGA tools -git config submodule.fpga/fpga-shells.update none git submodule update --init --recursive #--jobs 8 # Un-ignore toolchain submodules From a7ab0dab593771678498dcff2ac108f7c13f1caf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 13:59:10 -0800 Subject: [PATCH 309/457] Updated VCU118 | Bumped naming on Arty --- fpga/src/main/scala/arty/HarnessBinders.scala | 2 - fpga/src/main/scala/arty/TestHarness.scala | 14 +++-- fpga/src/main/scala/vcu118/Configs.scala | 5 +- fpga/src/main/scala/vcu118/DigitalTop.scala | 62 +++++++++++++++++++ .../main/scala/vcu118/HarnessBinders.scala | 8 +-- fpga/src/main/scala/vcu118/IOBinders.scala | 1 - fpga/src/main/scala/vcu118/TestHarness.scala | 12 ++-- .../main/scala/vcu118/bringup/Configs.scala | 11 +++- .../scala/vcu118/bringup/DigitalTop.scala | 25 ++++++++ .../scala/vcu118/bringup/HarnessBinders.scala | 8 --- .../chipyard/src/main/scala/DigitalTop.scala | 40 ------------ 11 files changed, 117 insertions(+), 71 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/DigitalTop.scala create mode 100644 fpga/src/main/scala/vcu118/bringup/DigitalTop.scala diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 89105d78..a7ce4465 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -58,7 +58,6 @@ class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ // IOBUF(th.jd_1, j.TRSTn) // PULLUP(th.jd_1) // } - Nil } }) @@ -68,6 +67,5 @@ class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ // UARTAdapter.connect(ports)(system.p) // IOBUF(th.ck_io(2), ports.txd) // IOBUF(th.ck_io(3), ports.rxd) - Nil } }) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 856f903f..ff16327e 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -7,11 +7,12 @@ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} +import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { - val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") + val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") // turn IO clock into Reset type val hReset = Wire(Reset()) @@ -19,17 +20,20 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell // default to 32MHz clock withClockAndReset(clock_32MHz, hReset) { - val dut = Module(ldut.module) + val dut = Module(lazyDut.module) } val harnessClock = clock_32MHz val harnessReset = hReset val success = false.B + val dutReset = reset_core - // must be after HasHarnessSignalReferences assignments - ldut match { case d: HasTestHarnessFunctions => + lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) } + lazyDut match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } + } diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f7b0df10..f55c9520 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118 import sys.process._ -import freechips.rocketchip.config.{Config} +import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} @@ -15,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import chipyard.{BuildSystem} + class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) @@ -22,6 +24,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS case SystemBusKey => up(SystemBusKey).copy( diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala new file mode 100644 index 00000000..4a176fca --- /dev/null +++ b/fpga/src/main/scala/vcu118/DigitalTop.scala @@ -0,0 +1,62 @@ +package chipyard.fpga.vcu118 + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +import chipyard.{DigitalTop, DigitalTopModule} + +// ------------------------------------ +// VCU118 DigitalTop +// ------------------------------------ + +class VCU118DigitalTop(implicit p: Parameters) extends DigitalTop + with sifive.blocks.devices.spi.HasPeripherySPI + with CanHaveMasterTLMemPort +{ + override lazy val module = new VCU118DigitalTopModule(this) +} + +class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends DigitalTopModule(l) + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + +/** Adds a TileLink port to the system intended to master an MMIO device bus */ +trait CanHaveMasterTLMemPort { this: BaseSubsystem => + private val memPortParamsOpt = p(ExtMem) + private val portName = "tl_mem" + private val device = new MemoryDevice + private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsGet = TransferSizes(1, mbus.blockBytes), + supportsPutFull = TransferSizes(1, mbus.blockBytes), + supportsPutPartial = TransferSizes(1, mbus.blockBytes))), + beatBytes = memPortParams.beatBytes) + } + }).toList.flatten) + + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) + } + + val mem_tl = InModuleBody { memTLNode.makeIOs() } +} diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index ae2462a2..6ba53642 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} +import chipyard.{HasHarnessSignalReferences} import chipyard.harness.{OverrideHarnessBinder} /*** UART ***/ @@ -18,8 +18,6 @@ class WithUART extends OverrideHarnessBinder({ th match { case vcu118th: VCU118FPGATestHarnessImp => { vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head } } - - Nil } }) @@ -29,8 +27,6 @@ class WithSPISDCard extends OverrideHarnessBinder({ th match { case vcu118th: VCU118FPGATestHarnessImp => { vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head } } - - Nil } }) @@ -45,7 +41,5 @@ class WithDDRMem extends OverrideHarnessBinder({ bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } ddrClientBundle <> ports.head } } - - Nil } }) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala index a1f67bcd..4c5bb357 100644 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -11,7 +11,6 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} -import chipyard.{CanHaveMasterTLMemPort} import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 4748c528..d5a5481e 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -15,10 +15,9 @@ import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -125,10 +124,13 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) - // cy stuff + // reset setup + val hReset = Wire(Reset()) + hReset := _outer.dutClock.in.head._1.reset + val harnessClock = _outer.dutClock.in.head._1.clock - val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) - val dutReset = harnessReset + val harnessReset = WireInit(hReset) + val dutReset = hReset.asAsyncReset val success = false.B childClock := harnessClock diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 0e5602e5..fc5df5a1 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup import math.min -import freechips.rocketchip.config.{Config} +import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} @@ -13,6 +13,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import chipyard.{BuildSystem} + import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} class WithBringupPeripherals extends Config((site, here, up) => { @@ -34,6 +36,10 @@ class WithBringupPeripherals extends Config((site, here, up) => { } }) +class WithBringupVCU118System extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top +}) + class WithBringupAdditions extends Config( new WithBringupUART ++ new WithBringupSPI ++ @@ -41,7 +47,8 @@ class WithBringupAdditions extends Config( new WithBringupGPIO ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ - new WithBringupPeripherals) + new WithBringupPeripherals ++ + new WithBringupVCU118System) class RocketBringupConfig extends Config( new WithBringupPeripherals ++ diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala new file mode 100644 index 00000000..ddcfe163 --- /dev/null +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -0,0 +1,25 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} + +// ------------------------------------ +// BringupVCU118 DigitalTop +// ------------------------------------ + +class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop + with sifive.blocks.devices.i2c.HasPeripheryI2C +{ + override lazy val module = new BringupVCU118DigitalTopModule(this) +} + +class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index b6693036..531b3c8d 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -19,8 +19,6 @@ class WithBringupUART extends ComposeHarnessBinder({ vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last } } - - Nil } }) @@ -32,8 +30,6 @@ class WithBringupSPI extends ComposeHarnessBinder({ vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last } } - - Nil } }) @@ -45,8 +41,6 @@ class WithBringupI2C extends OverrideHarnessBinder({ vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head } } - - Nil } }) @@ -58,7 +52,5 @@ class WithBringupGPIO extends OverrideHarnessBinder({ bb_io.bundle <> dut_io } } } - - Nil } }) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 46904a37..c0ac1ff7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -26,7 +26,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA - with CanHaveMasterTLMemPort { override lazy val module = new DigitalTopModule(this) } @@ -39,42 +38,3 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -/** Adds a TileLink port to the system intended to master an MMIO device bus */ -trait CanHaveMasterTLMemPort { this: BaseSubsystem => - private val memPortParamsOpt = p(ExtMem) - private val portName = "tl_mem" - private val device = new MemoryDevice - private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) - - val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => - Seq.tabulate(nMemoryChannels) { channel => - val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - - TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = base.flatMap(_.intersect(filter)), - resources = device.reg, - regionType = RegionType.UNCACHED, // cacheable - executable = true, - supportsGet = TransferSizes(1, mbus.blockBytes), - supportsPutFull = TransferSizes(1, mbus.blockBytes), - supportsPutPartial = TransferSizes(1, mbus.blockBytes))), - beatBytes = memPortParams.beatBytes) - } - }).toList.flatten) - - mbus.coupleTo(s"memory_controller_port_named_$portName") { - (memTLNode - :*= TLBuffer() - :*= TLSourceShrinker(1 << idBits) - :*= TLWidthWidget(mbus.beatBytes) - :*= _) - } - - val mem_tl = InModuleBody { memTLNode.makeIOs() } -} From a281869041fbe7c38d91268756626d5d1d891f51 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:04:44 -0800 Subject: [PATCH 310/457] Fix Arty merge and errors from CY bump --- fpga/Makefile | 2 +- fpga/src/main/scala/arty/Configs.scala | 39 ++------ fpga/src/main/scala/arty/DigitalTop.scala | 21 ----- fpga/src/main/scala/arty/HarnessBinders.scala | 90 +++++++++---------- fpga/src/main/scala/arty/IOBinders.scala | 24 +++++ fpga/src/main/scala/arty/TestHarness.scala | 19 ++-- 6 files changed, 89 insertions(+), 106 deletions(-) delete mode 100644 fpga/src/main/scala/arty/DigitalTop.scala create mode 100644 fpga/src/main/scala/arty/IOBinders.scala diff --git a/fpga/Makefile b/fpga/Makefile index fa1f8e08..fa6847ef 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),arty) MODEL ?= ArtyFPGATestHarness VLOG_MODEL ?= ArtyFPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.arty - CONFIG ?= E300ArtyDevKitConfig + CONFIG ?= TinyRocketArtyConfig CONFIG_PACKAGE ?= chipyard.fpga.arty GENERATOR_PACKAGE ?= chipyard TB ?= none # unused diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index e96bcd9c..11cf0260 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -9,35 +9,13 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ import chipyard.{BuildSystem} -import chipyard.iobinders -class E300DevKitExtra extends Config((site, here, up) => { - case PeripheryGPIOKey => List( - GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) - case PeripheryPWMKey => List( - PWMParams(address = 0x10015000, cmpWidth = 8), - PWMParams(address = 0x10025000, cmpWidth = 16), - PWMParams(address = 0x10035000, cmpWidth = 16)) - case PeripherySPIKey => List( - SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), - SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) - case PeripherySPIFlashKey => List( - SPIFlashParams( - fAddress = 0x20000000, - rAddress = 0x10014000, - defaultSampleDel = 3)) +class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( - UARTParams(address = 0x10013000), - UARTParams(address = 0x10023000)) - case PeripheryI2CKey => List( - I2CParams(address = 0x10016000)) + UARTParams(address = 0x10013000)) case DTSTimebase => BigInt(32768) case JtagDTMKey => new JtagDTMConfig ( idcodeVersion = 2, @@ -46,17 +24,16 @@ class E300DevKitExtra extends Config((site, here, up) => { debugIdleCycles = 5) }) -class WithE300System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) -}) - -class E300ArtyDevKitConfig extends Config( - new WithE300System ++ +class TinyRocketArtyConfig extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ + new WithArtyResetHarnessBinder ++ new chipyard.iobinders.WithDebugIOCells ++ new chipyard.iobinders.WithUARTIOCells ++ - new E300DevKitExtra ++ + new WithResetPassthrough ++ + new WithDefaultPeripherals ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.With1TinyCore ++ diff --git a/fpga/src/main/scala/arty/DigitalTop.scala b/fpga/src/main/scala/arty/DigitalTop.scala deleted file mode 100644 index 858b6215..00000000 --- a/fpga/src/main/scala/arty/DigitalTop.scala +++ /dev/null @@ -1,21 +0,0 @@ -package chipyard.fpga.arty - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// E300 DigitalTop -// ------------------------------------ - -class E300DigitalTop(implicit p: Parameters) extends DigitalTop -{ - override lazy val module = new E300DigitalTopModule(this) -} - -class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index a7ce4465..408d2b7d 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -1,71 +1,69 @@ package chipyard.fpga.arty import chisel3._ -import chisel3.experimental.{Analog} -import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} -import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} -import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.subsystem._ -import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ - -import barstools.iocell.chisel._ - -import testchipip._ - -import chipyard.harness.OverrideHarnessBinder -import chipyard.HasHarnessSignalReferences -import chipyard.iobinders.GetSystemParameters - -import tracegen.{TraceGenSystemModuleImp} -import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} - -import scala.reflect.{ClassTag} +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pinctrl._ import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} -class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { - // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { - // ports.map { - // case d: ClockedDMIIO => - // // Want to error here. - // case j: JTAGIO => - // //val dtm_success = WireInit(false.B) - // //when (dtm_success) { th.success := true.B } - // //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) +import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} - // j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt +class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { + withClockAndReset(th.clock_32MHz, th.ck_rst) { + // Debug module reset + th.dut_ndreset := ports(0) - // IOBUF(th.jd_5, j.TMS) - // PULLUP(th.jd_5) + // JTAG reset + ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz) + } + } +}) - // IOBUF(th.jd_4, j.TDI) - // PULLUP(th.jd_4) +class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + ports.map { + case j: JTAGIO => + withClockAndReset(th.harnessClock, th.hReset) { + val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag") - // IOBUF(th.jd_0, j.TDO) + JTAGPinsFromPort(io_jtag, j) - // // mimic putting a pullup on this line (part of reset vote) - // th.SRST_n := IOBUF(th.jd_6) - // PULLUP(th.jd_6) + io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool - // IOBUF(th.jd_1, j.TRSTn) - // PULLUP(th.jd_1) - // } + IOBUF(th.jd_5, io_jtag.TMS) + PULLUP(th.jd_5) + + IOBUF(th.jd_4, io_jtag.TDI) + PULLUP(th.jd_4) + + IOBUF(th.jd_0, io_jtag.TDO) + + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) + + // ignore the po input + io_jtag.TCK.i.po.map(_ := DontCare) + io_jtag.TDI.i.po.map(_ := DontCare) + io_jtag.TMS.i.po.map(_ := DontCare) + io_jtag.TDO.i.po.map(_ := DontCare) + } + } } }) class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { - // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { - // UARTAdapter.connect(ports)(system.p) - // IOBUF(th.ck_io(2), ports.txd) - // IOBUF(th.ck_io(3), ports.rxd) + withClockAndReset(th.clock_32MHz, th.ck_rst) { + IOBUF(th.uart_txd_in, ports.head.txd) + ports.head.rxd := IOBUF(th.uart_rxd_out) + } } }) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala new file mode 100644 index 00000000..205f8fcc --- /dev/null +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -0,0 +1,24 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{IO} + +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug._ + +import chipyard.iobinders.{ComposeIOBinder} + +class WithResetPassthrough extends ComposeIOBinder({ + (system: HasPeripheryDebugModuleImp) => { + // Debug module reset + val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset") + io_ndreset := system.debug.get.ndreset + + // JTAG reset + val sjtag = system.debug.get.systemjtag.get + val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset") + sjtag.reset := io_sjtag_reset + + (Seq(io_ndreset, io_sjtag_reset), Nil) + } +}) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index ff16327e..503d2de6 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -1,23 +1,27 @@ package chipyard.fpga.arty import chisel3._ -import chisel3.experimental.{Analog} -import scala.collection.mutable.{ArrayBuffer} + import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.config.{Parameters} + import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} + import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} +import chipyard.harness.{ApplyHarnessBinders} import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") - // turn IO clock into Reset type + // Convert harness resets from Bool to Reset type. val hReset = Wire(Reset()) hReset := ck_rst + val dReset = Wire(AsyncReset()) + dReset := reset_core.asAsyncReset + // default to 32MHz clock withClockAndReset(clock_32MHz, hReset) { val dut = Module(lazyDut.module) @@ -27,13 +31,14 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val harnessReset = hReset val success = false.B - val dutReset = reset_core + val dutReset = dReset + // must be after HasHarnessSignalReferences assignments lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) } lazyDut match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } - } + From 43e64ded93ce22fa2c578cd1e283c8336f5a497d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:13:09 -0800 Subject: [PATCH 311/457] Readd ignore fpga-shells in main submodule setup --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c861658d..e3272f86 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -39,6 +39,8 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.software/firemarshal.update none +# Disable update to fpga-shells +git config submodule.fpga/fpga-shells.update none git submodule update --init --recursive #--jobs 8 # Un-ignore toolchain submodules From 083f34ab23f91a910edfbbc70d35e56fe4331448 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:44:54 -0800 Subject: [PATCH 312/457] Revert Chipyard system | Create new VCU118 Chipyard system --- fpga/src/main/scala/vcu118/DigitalTop.scala | 54 +++++++++++++++++-- .../chipyard/src/main/scala/System.scala | 1 + 2 files changed, 50 insertions(+), 5 deletions(-) diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala index 4a176fca..9fe42bc8 100644 --- a/fpga/src/main/scala/vcu118/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/DigitalTop.scala @@ -8,22 +8,66 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.{DontTouch} -import chipyard.{DigitalTop, DigitalTopModule} +import chipyard.{DigitalTop, DigitalTopModule, ChipyardSubsystem, ChipyardSubsystemModuleImp} // ------------------------------------ // VCU118 DigitalTop // ------------------------------------ -class VCU118DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.spi.HasPeripherySPI - with CanHaveMasterTLMemPort +class VCU118DigitalTop(implicit p: Parameters) extends VCU118ChipyardSystem + with testchipip.CanHaveTraceIO // Enables optionally adding trace IO + with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device + with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter + with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART + with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs + with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port + with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim + with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget + with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget + with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget + with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget + with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new VCU118DigitalTopModule(this) } -class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends DigitalTopModule(l) +class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends VCU118ChipyardSystemModule(l) + with testchipip.CanHaveTraceIOModuleImp + with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + with chipyard.example.CanHavePeripheryGCDModuleImp + with freechips.rocketchip.util.DontTouch + +// ------------------------------------ +// VCU118 Chipyard System +// ------------------------------------ + +class VCU118ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem + with HasAsyncExtInterrupts + with CanHaveMasterTLMemPort // expose a TL port for outer memory (replaces AXI outer port) + with CanHaveMasterAXI4MMIOPort + with CanHaveSlaveAXI4Port +{ + + val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } + val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } + override lazy val module = new VCU118ChipyardSystemModule(this) +} + +class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasExtInterruptsModuleImp + with DontTouch + +// ------------------------------------ +// VCU118 Mem Port Mixin +// ------------------------------------ /** Adds a TileLink port to the system intended to master an MMIO device bus */ trait CanHaveMasterTLMemPort { this: BaseSubsystem => diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index f8906e04..bd20ddc7 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -23,6 +23,7 @@ import freechips.rocketchip.util.{DontTouch} */ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts + with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port { From 2de5f7dd7e245ad3f47cbfa69a68b925c38df3af Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:48:50 -0800 Subject: [PATCH 313/457] [ci skip] Note that CVA6 was called Ariane in the past --- README.md | 2 +- docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- docs/Generators/CVA6.rst | 2 +- sims/firesim | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 11f1b8d5..0283da58 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 4ad39d51..398b537d 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -21,7 +21,7 @@ Processor Cores See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. **CVA6 Core** - An in-order RISC-V core written in System Verilog. + An in-order RISC-V core written in System Verilog. Previously called Ariane. See :ref:`CVA6 Core` for more information. Accelerators diff --git a/docs/Generators/CVA6.rst b/docs/Generators/CVA6.rst index 6250c614..bfca746a 100644 --- a/docs/Generators/CVA6.rst +++ b/docs/Generators/CVA6.rst @@ -1,7 +1,7 @@ CVA6 Core ==================================== -`CVA6 `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. +`CVA6 `__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`. The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. diff --git a/sims/firesim b/sims/firesim index 57efb2ec..37fe89a6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 57efb2ec032a8c7afa2f458761cc79b2614180b5 +Subproject commit 37fe89a65f1c1ccd8d2cc0d1efd0c06308d0224d From 255e88fe8f8a0ee5e2b648403d0d6b872d75e1d1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 17:06:34 -0800 Subject: [PATCH 314/457] Initial outline of FPGA prototyping docs --- docs/Chipyard-Basics/Chipyard-Components.rst | 11 ++- docs/Simulation/FPGA-Prototyping.rst | 87 ++++++++++++++++++++ docs/Simulation/index.rst | 11 ++- fpga/src/main/scala/vcu118/Configs.scala | 2 + fpga/src/main/scala/vcu118/TestHarness.scala | 2 + 5 files changed, 107 insertions(+), 6 deletions(-) create mode 100644 docs/Simulation/FPGA-Prototyping.rst diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index c24f81ed..1d19a65f 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -106,12 +106,12 @@ Software Sims ------------------------------------------- -**verilator (Verilator wrapper)** +**Verilator** Verilator is an open source Verilog simulator. The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). See :ref:`Verilator (Open-Source)` for more information. -**vcs (VCS wrapper)** +**VCS** VCS is a proprietary Verilog simulator. Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). See :ref:`Synopsys VCS (License Required)` for more information. @@ -124,6 +124,13 @@ Sims In order to use FireSim, the repository must be cloned and executed on AWS instances. See :ref:`FireSim` for more information. +**FPGA Prototyping** + FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. + Some examples of FPGA's supported are Arty and VCU118. + For more accurate and deterministic simulation results, please consider using the :ref:`FireSim` platform. + See :ref:`FPGA Prototyping` for more information. + + VLSI ------------------------------------------- diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst new file mode 100644 index 00000000..eab33d35 --- /dev/null +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -0,0 +1,87 @@ +FPGA Prototyping +============================== + +FPGA Prototyping +----------------------- + +Chipyard supports FPGA prototyping for local FPGAs supported under ``fpga-shells`` . +This include popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. + +Setup +----- + +All FPGA related collateral is located in the ``fpga`` top-level Chipyard folder. +To initialize the ``fpga-shells`` repository, run the included submodule script: + +.. code-block:: shell + + # in the chipyard top level folder + ./scripts/init-fpga.sh + +Making a Bitstream +------------------ + +Making a bitstream for any FPGA is similar to building RTL for a software RTL simulation. +Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software RTL Simulation` section you can run the following command in the ``fpga`` directory. + +.. code-block:: shell + + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... bit + + # or + + make SUB_PROJECT= bit + +By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. +These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. +In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. +For example, building the BOOM configuration on the VCU118: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config + +Running a Design on Arty +------------------------ + +Running a Design on VCU118 +-------------------------- + +Basic Design +~~~~~~~~~~~~ + +The default VCU118 design is setup to run RISC-V Linux from an SDCard while piping the terminal over UART. +To change the design, you can create your own configuration and add the ``AbstractVCU118Config`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory. +Notice that the majority of config. fragments in ``AbstractVCU118Config`` are shared with a normal Chipyard config. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala + :language: scala + :start-after: DOC include start: AbstractVCU118 and Rocket + :end-before: DOC include end: AbstractVCU118 and Rocket + +fpga-shells / Overlays / HarnessBinders +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To make meaningful VCU118 changes (adding new IOs, connecting to different VCU118 ports, etc), the ``VCU118TestHarness`` must change. +The ``VCU118TestHarness`` uses ``fpga-shells`` to add ``Overlays`` that connect to the VCU118 external IOs. +``fpga/src/main/scala/vcu118/TestHarness.scala`` shows an example of using these ``Overlays``. +First ``Overlays`` must be "placed" which adds them to the design. +For example, the following shows a UART overlay being placed into the design. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: UartOverlay + :end-before: DOC include end: UartOverlay + +Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. +The ``UARTDesignInput`` is used to pass in the UART signals used to connect to the external UART IO. +This is similar to all the other ``Overlays``. +They must be "placed" and given a set of inputs (IOs, parameters). + +Once you add the wanted ``Overlays`` and place them into a new ``TestHarness``, you can add a new set of harness/io binders to connect to them. +This is shown in ``fpga/src/main/scala/vcu118/HarnessBinders.scala``. +For more information on harness and IO binders, refer to :ref:`IOBinders and HarnessBinders`. + +An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index c15283d3..24099bfb 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,16 +1,18 @@ Simulation ======================= -Chipyard supports two classes of simulation: +Chipyard supports three classes of simulation: -#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators +#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators #. FPGA-accelerated full-system simulation using FireSim +#. FPGA prototyping on ``fpga-shells`` platforms Software RTL simulators of Chipyard designs run at O(1 KHz), but compile -quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run +quickly and provide full waveforms. Conversely, FPGA-accelerated simulators and FPGA prototyping run at O(100 MHz), making them appropriate for booting an operating system and running a complete workload, but have multi-hour compile times and poorer debug -visability. +visibility. However, FPGA-accelerated simulators differ from FPGA prototyping by providing deterministic +cycle-accurate results. Click next to see how to run a simulation. @@ -20,4 +22,5 @@ Click next to see how to run a simulation. Software-RTL-Simulation FPGA-Accelerated-Simulation + FPGA-Prototyping diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f55c9520..6822b251 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -48,6 +48,7 @@ class WithSystemModifications extends Config((site, here, up) => { case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) }) +// DOC include start: AbstractVCU118 and Rocket class AbstractVCU118Config extends Config( new WithUART ++ new WithSPISDCard ++ @@ -72,6 +73,7 @@ class AbstractVCU118Config extends Config( class RocketVCU118Config extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new AbstractVCU118Config) +// DOC include end: AbstractVCU118 and Rocket class BoomVCU118Config extends Config( new WithFPGAFrequency(75) ++ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d5a5481e..05e1e59d 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -70,10 +70,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** UART ***/ +// DOC include start: UartOverlay // 1st UART goes to the VCU118 dedicated UART val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) +// DOC include end: UartOverlay /*** SPI ***/ From 9a5b67bf8c3a65e67cacd24616730f3c406c2ba1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 20:30:49 -0800 Subject: [PATCH 315/457] Use Chipyard configs as a base (VCU118) --- fpga/src/main/scala/vcu118/Configs.scala | 28 ++++++++----------- .../main/scala/vcu118/bringup/Configs.scala | 13 +++++---- .../scala/vcu118/bringup/TestHarness.scala | 2 +- .../main/scala/config/AbstractConfig.scala | 2 +- 4 files changed, 21 insertions(+), 24 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f55c9520..aee3c489 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -15,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import testchipip.{SerialTLKey} + import chipyard.{BuildSystem} class WithDefaultPeripherals extends Config((site, here, up) => { @@ -45,10 +47,11 @@ class WithSystemModifications extends Config((site, here, up) => { require (make.! == 0, "Failed to build bootrom") p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") } - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size + case SerialTLKey => None // remove serialized tl port }) -class AbstractVCU118Config extends Config( +class WithVCU118Tweaks extends Config( new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ @@ -56,27 +59,18 @@ class AbstractVCU118Config extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size + new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new chipyard.WithMulticlockCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) class RocketVCU118Config extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new AbstractVCU118Config) + new WithVCU118Tweaks ++ + new chipyard.RocketConfig) class BoomVCU118Config extends Config( new WithFPGAFrequency(75) ++ - new boom.common.WithNLargeBooms(1) ++ - new AbstractVCU118Config) + new WithVCU118Tweaks ++ + new chipyard.MegaBoomConfig) class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { case FPGAFrequencyKey => MHz diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index fc5df5a1..133d2ae2 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -15,7 +15,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import chipyard.{BuildSystem} -import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} +import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) @@ -51,9 +51,12 @@ class WithBringupAdditions extends Config( new WithBringupVCU118System) class RocketBringupConfig extends Config( - new WithBringupPeripherals ++ - new RocketVCU118Config) + new WithBringupAdditions ++ + new WithVCU118Tweaks ++ + new chipyard.RocketConfig) class BoomBringupConfig extends Config( - new WithBringupPeripherals ++ - new BoomVCU118Config) + new WithFPGAFrequency(75) ++ + new WithBringupAdditions ++ + new WithVCU118Tweaks ++ + new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 080f6189..8a4ae8fc 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -68,5 +68,5 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends } class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { - val bringupOuter = _outer + lazy val bringupOuter = _outer } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 301c03d7..b1e873d1 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -49,6 +49,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system From b0fc0457aa63073b10b86d4cccb21e45d428fc8c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 20:44:48 -0800 Subject: [PATCH 316/457] Use Chipyard configs as base (Arty) --- fpga/src/main/scala/arty/Configs.scala | 29 +++++++------------ fpga/src/main/scala/arty/HarnessBinders.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 4 +++ 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 11cf0260..bc62bcf9 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -11,6 +11,8 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ +import testchipip.{SerialTLKey} + import chipyard.{BuildSystem} class WithDefaultPeripherals extends Config((site, here, up) => { @@ -22,29 +24,20 @@ class WithDefaultPeripherals extends Config((site, here, up) => { idcodePartNum = 0x000, idcodeManufId = 0x489, debugIdleCycles = 5) + case SerialTLKey => None // remove serialized tl port }) -class TinyRocketArtyConfig extends Config( +class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithArtyResetHarnessBinder ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ new WithResetPassthrough ++ new WithDefaultPeripherals ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithIncoherentBusTopology) + +class TinyRocketArtyConfig extends Config( + new WithArtyTweaks ++ + new chipyard.TinyRocketConfig) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 408d2b7d..464d054a 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -59,7 +59,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ } }) -class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ +class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { withClockAndReset(th.clock_32MHz, th.ck_rst) { IOBUF(th.uart_txd_in, ports.head.txd) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index d413cc12..626700a5 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -10,6 +10,10 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) +class TinyRocketConfig extends Config( + new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core + new chipyard.config.AbstractConfig) + class HwachaRocketConfig extends Config( new chipyard.config.WithHwachaTest ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator From 84508bee6e075db9181ed4ad2b3bc76a43852e91 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 21:51:25 -0800 Subject: [PATCH 317/457] More FPGA prototyping docs --- docs/Simulation/FPGA-Prototyping.rst | 74 +++++++++++++------- fpga/src/main/scala/vcu118/TestHarness.scala | 2 + 2 files changed, 51 insertions(+), 25 deletions(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index eab33d35..0594b132 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -2,16 +2,21 @@ FPGA Prototyping ============================== FPGA Prototyping ------------------------ +---------------- -Chipyard supports FPGA prototyping for local FPGAs supported under ``fpga-shells`` . -This include popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. +This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. -Setup ------ +.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. + However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. -All FPGA related collateral is located in the ``fpga`` top-level Chipyard folder. +Sources and Submodule Setup +--------------------------- + +All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard folder. +This includes ``fpga-shells`` and the ``src`` folders that hold both Scala, TCL and other collateral. +However, the ``fpga-shells`` repository is not initialized by default. To initialize the ``fpga-shells`` repository, run the included submodule script: .. code-block:: shell @@ -22,8 +27,8 @@ To initialize the ``fpga-shells`` repository, run the included submodule script: Making a Bitstream ------------------ -Making a bitstream for any FPGA is similar to building RTL for a software RTL simulation. -Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software RTL Simulation` section you can run the following command in the ``fpga`` directory. +Making a bitstream for any FPGA target is similar to building RTL for a software RTL simulation. +Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream: .. code-block:: shell @@ -35,12 +40,16 @@ Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. +Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (i.e. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override). In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. For example, building the BOOM configuration on the VCU118: .. code-block:: shell - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit + +That command will build the RTL and generate a bitstream using Vivado. +However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. Running a Design on Arty ------------------------ @@ -51,24 +60,24 @@ Running a Design on VCU118 Basic Design ~~~~~~~~~~~~ -The default VCU118 design is setup to run RISC-V Linux from an SDCard while piping the terminal over UART. -To change the design, you can create your own configuration and add the ``AbstractVCU118Config`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. -Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory. -Notice that the majority of config. fragments in ``AbstractVCU118Config`` are shared with a normal Chipyard config. +The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. +This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). +To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. .. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala :language: scala :start-after: DOC include start: AbstractVCU118 and Rocket :end-before: DOC include end: AbstractVCU118 and Rocket -fpga-shells / Overlays / HarnessBinders -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Brief Implementation Description + More Complicated Designs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -To make meaningful VCU118 changes (adding new IOs, connecting to different VCU118 ports, etc), the ``VCU118TestHarness`` must change. -The ``VCU118TestHarness`` uses ``fpga-shells`` to add ``Overlays`` that connect to the VCU118 external IOs. -``fpga/src/main/scala/vcu118/TestHarness.scala`` shows an example of using these ``Overlays``. -First ``Overlays`` must be "placed" which adds them to the design. -For example, the following shows a UART overlay being placed into the design. +The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design. +This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target. +The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs. +Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral. +For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``. .. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala :language: scala @@ -76,12 +85,27 @@ For example, the following shows a UART overlay being placed into the design. :end-before: DOC include end: UartOverlay Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. -The ``UARTDesignInput`` is used to pass in the UART signals used to connect to the external UART IO. -This is similar to all the other ``Overlays``. +The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``. +Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope). +This pattern is similar for all other ``Overlays`` in the test harness. They must be "placed" and given a set of inputs (IOs, parameters). +The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA. -Once you add the wanted ``Overlays`` and place them into a new ``TestHarness``, you can add a new set of harness/io binders to connect to them. -This is shown in ``fpga/src/main/scala/vcu118/HarnessBinders.scala``. -For more information on harness and IO binders, refer to :ref:`IOBinders and HarnessBinders`. +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: ClockOverlay + :end-before: DOC include end: ClockOverlay + +Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``. +For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design. + +After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. +This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). +For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. +This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. + +.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. + For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. + See :ref:`Making a Bitstream` for information on the various make variables. diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 05e1e59d..ed4ba221 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -41,6 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val topDesign = LazyModule(p(BuildTop)(dp)) +// DOC include start: ClockOverlay // place all clocks in the shell dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } @@ -59,6 +60,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val dutWrangler = LazyModule(new ResetWrangler) val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL +// DOC include end: ClockOverlay // connect ref clock to dummy sink node ref_clock.get() match { From c721d897f3397506d120efa6c00fa530e34aa584 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 10:18:10 -0800 Subject: [PATCH 318/457] Point to SiFive license | Add require on Arty --- LICENSE.SiFive | 202 ++++++++++++++++++ .../src/main/resources/vcu118/sdboot/common.h | 1 + fpga/src/main/resources/vcu118/sdboot/head.S | 2 +- .../resources/vcu118/sdboot/include/bits.h | 2 +- .../resources/vcu118/sdboot/include/const.h | 2 +- .../vcu118/sdboot/include/devices/clint.h | 4 +- .../vcu118/sdboot/include/devices/gpio.h | 2 +- .../vcu118/sdboot/include/devices/plic.h | 2 +- .../vcu118/sdboot/include/devices/spi.h | 2 +- .../vcu118/sdboot/include/devices/uart.h | 2 +- .../sdboot/include/riscv_test_defaults.h | 2 +- .../vcu118/sdboot/include/sections.h | 2 +- .../resources/vcu118/sdboot/include/smp.h | 3 +- .../main/resources/vcu118/sdboot/kprintf.c | 2 +- .../main/resources/vcu118/sdboot/kprintf.h | 2 +- fpga/src/main/resources/vcu118/sdboot/sd.c | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 2 + 17 files changed, 221 insertions(+), 15 deletions(-) create mode 100644 LICENSE.SiFive diff --git a/LICENSE.SiFive b/LICENSE.SiFive new file mode 100644 index 00000000..7e709337 --- /dev/null +++ b/LICENSE.SiFive @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2016-2017 SiFive, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/fpga/src/main/resources/vcu118/sdboot/common.h b/fpga/src/main/resources/vcu118/sdboot/common.h index 4f71e103..ccb9cd3b 100644 --- a/fpga/src/main/resources/vcu118/sdboot/common.h +++ b/fpga/src/main/resources/vcu118/sdboot/common.h @@ -1,3 +1,4 @@ +// See LICENSE.Sifive for license details. #ifndef _SDBOOT_COMMON_H #define _SDBOOT_COMMON_H diff --git a/fpga/src/main/resources/vcu118/sdboot/head.S b/fpga/src/main/resources/vcu118/sdboot/head.S index d871b824..c6653f7c 100644 --- a/fpga/src/main/resources/vcu118/sdboot/head.S +++ b/fpga/src/main/resources/vcu118/sdboot/head.S @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #include #include #include "common.h" diff --git a/fpga/src/main/resources/vcu118/sdboot/include/bits.h b/fpga/src/main/resources/vcu118/sdboot/include/bits.h index bfe656fe..216b698c 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/bits.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/bits.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _RISCV_BITS_H #define _RISCV_BITS_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/const.h b/fpga/src/main/resources/vcu118/sdboot/include/const.h index 8dcffbb0..8507e168 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/const.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/const.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. /* Derived from */ #ifndef _SIFIVE_CONST_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h index c2b05bae..08092cd4 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_CLINT_H #define _SIFIVE_CLINT_H @@ -11,4 +11,4 @@ #define CLINT_MTIME 0xBFF8 #define CLINT_MTIME_size 0x8 -#endif /* _SIFIVE_CLINT_H */ +#endif /* _SIFIVE_CLINT_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h index f7f0acb4..76dcb9f0 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_GPIO_H #define _SIFIVE_GPIO_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h index 4d5b2d8d..eddcae98 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef PLIC_H #define PLIC_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h index 7118572a..85c10994 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_SPI_H #define _SIFIVE_SPI_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h index aecfd912..c3f6a532 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_UART_H #define _SIFIVE_UART_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h index a2dea3d4..c9212737 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _RISCV_TEST_DEFAULTS_H #define _RISCV_TEST_DEFAULTS_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/sections.h b/fpga/src/main/resources/vcu118/sdboot/include/sections.h index 6e1f0518..4ec1ef7e 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/sections.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/sections.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SECTIONS_H #define _SECTIONS_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/smp.h b/fpga/src/main/resources/vcu118/sdboot/include/smp.h index 145ceb37..d93e64b2 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/smp.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/smp.h @@ -1,3 +1,4 @@ +// See LICENSE.Sifive for license details. #ifndef SIFIVE_SMP #define SIFIVE_SMP #include "platform.h" @@ -14,7 +15,7 @@ #define NONSMP_HART 0 #endif -/* If your test cannot handle multiple-threads, use this: +/* If your test cannot handle multiple-threads, use this: * smp_disable(reg1) */ #define smp_disable(reg1, reg2) \ diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.c b/fpga/src/main/resources/vcu118/sdboot/kprintf.c index 57627011..3e3f2185 100644 --- a/fpga/src/main/resources/vcu118/sdboot/kprintf.c +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.c @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #include #include #include diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.h b/fpga/src/main/resources/vcu118/sdboot/kprintf.h index 26cc8055..a7a94866 100644 --- a/fpga/src/main/resources/vcu118/sdboot/kprintf.h +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SDBOOT_KPRINTF_H #define _SDBOOT_KPRINTF_H diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index bdd9d62a..47c87d5f 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #include #include diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 464d054a..ef7b1805 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -16,6 +16,8 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { + require(ports.size == 2) + withClockAndReset(th.clock_32MHz, th.ck_rst) { // Debug module reset th.dut_ndreset := ports(0) From b0eed5075f804990deb8346e33db6ab87aebed55 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 6 Nov 2020 10:57:55 -0800 Subject: [PATCH 319/457] [temp] start integrating tsi host widget --- .../main/scala/vcu118/bringup/Configs.scala | 29 ++++++++++ .../scala/vcu118/bringup/CustomOverlays.scala | 56 ++++++++++++++++++- .../scala/vcu118/bringup/DigitalTop.scala | 2 + .../main/scala/vcu118/bringup/IOBinders.scala | 14 +++++ generators/testchipip | 2 +- 5 files changed, 101 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 133d2ae2..4c6cd5ad 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -4,6 +4,8 @@ import math.min import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.diplomacy._ import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} @@ -13,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} + import chipyard.{BuildSystem} import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} @@ -34,6 +38,30 @@ class WithBringupPeripherals extends Config((site, here, up) => { List.empty[GPIOParams] } } + case PeripheryTSIHostKey => List( + TSIHostParams( + serialIfWidth = 4, + mmioBaseAddress = BigInt(0x64006000), + mmioSourceId = 1 << 13, // manager source + serdesParams = TSIHostSerdesParams( + clientPortParams = TLMasterPortParameters.v1( + clients = Seq(TLMasterParameters.v1( + name = "tl-tsi-host-serdes", + sourceId = IdRange(0, (1 << 13))))), + managerPortParams = TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), + regionType = RegionType.UNCACHED, + executable = true, + supportsGet = TransferSizes(1, 64), + supportsPutFull = TransferSizes(1, 64), + supportsPutPartial = TransferSizes(1, 64), + supportsAcquireT = TransferSizes(1, 64), + supportsAcquireB = TransferSizes(1, 64), + supportsArithmetic = TransferSizes(1, 64), + supportsLogical = TransferSizes(1, 64))), + endSinkId = 1 << 6, // manager sink + beatBytes = 8)))) }) class WithBringupVCU118System extends Config((site, here, up) => { @@ -45,6 +73,7 @@ class WithBringupAdditions extends Config( new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ + new WithTSITLIOPassthrough ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ new WithBringupPeripherals ++ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index c0a96d3c..30a25afe 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -144,4 +144,58 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } - +//case class TSIShellInput() +//case class TSIDesignInput( +// +// )( +// implicit val p: Parameters)extends DDRDesignInput +// +//abstract class TSIOverlay(val params: TSIOverlayParams) +// extends IOOverlay[TLTSIWithDDRIO, TLTSIHostWidget] +//{ +// implicit val p = params.p +// +// // instantiate the tsi host widget and setup necessary connections +// val (tlTsiHost, tlTsiMemNode) = TLTSIHostWidget.attach(TSIHostWidgetAttachParams(params.tsiHostParams, params.controlBus)) +// val tlTsiHostIONodeSink = tlTsiHost.ioNode.makeSink +// +// // instantiate the DDR +// val size = p(TSIMigDDRSize) +// val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(params.tsiHostParams.targetBaseAddress, size)) +// val mig = LazyModule(new XilinxVCU118MIG(migParams)) +// val tsiIONode = BundleBridgeSource(() => new TSIHostWidgetIO(params.tsiHostParams.serialIfWidth)) +// val topTSIIONode = shell { tsiIONode.makeSink() } +// val ddrIONode = BundleBridgeSource(() => mig.module.io.cloneType) +// val topDDRIONode = shell { ddrIONode.makeSink() } +// val ddrUI = shell { ClockSourceNode(freqMHz = 200) } +// val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } +// areset := params.ddrParams.wrangler := ddrUI +// val asyncSink = LazyModule(new TLAsyncCrossingSink) +// val migClockReset = BundleBridgeSource(() => new Bundle { +// val clock = Output(Clock()) +// val reset = Output(Bool()) +// }) +// val migClockResetTop = shell { migClockReset.makeSink() } +// +// // connect them +// (mig.node := TLFragmenter(32,64,holdFirstDeny=true) := TLCacheCork() := TLSinkSetter(1 << 1) := TLSourceShrinker(1 << 4) := tlTsiMemNode) +// +// def designOutput = tlTsiHost +// def ioFactory = new TLTSIWithDDRIO(params.tsiHostParams.serialIfWidth, size) // top level io of the shell +// +// InModuleBody { +// val (t, _) = tsiIONode.out(0) +// val tsi = tlTsiHostIONodeSink.bundle +// tsi.serial_clock := t.serial_clock +// tsi.serial.in.bits := t.serial.in.bits +// tsi.serial.in.valid := t.serial.in.valid +// tsi.serial.out.ready := t.serial.out.ready +// t.serial.out.bits := tsi.serial.out.bits +// t.serial.out.valid := tsi.serial.out.valid +// t.serial.in.ready := tsi.serial.in.ready +// ddrIONode.bundle <> mig.module.io +// asyncSink.module.clock := migClockReset.bundle.clock +// asyncSink.module.reset := migClockReset.bundle.reset +// } +//} +// diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index ddcfe163..a9105e26 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -17,9 +17,11 @@ import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C + with testchipip.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp + with testchipip.HasPeripheryTSIHostWidgetModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 168933f7..32badd2a 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -3,9 +3,14 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{IO, DataMirror} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} +import testchipip.{HasPeripheryTSIHostWidget} + import chipyard.iobinders.{OverrideIOBinder} class WithGPIOIOPassthrough extends OverrideIOBinder({ @@ -27,3 +32,12 @@ class WithI2CIOPassthrough extends OverrideIOBinder({ (io_i2c_pins_temp, Nil) } }) + +class WithTSITLIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryTSIHostWidget) => { + require(system.tsiMem.size == 1) + val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiMem.head)).suggestName("tsi_tl_slave") + io_tsi_tl_mem_pins_temp <> system.tsiMem.head + (Seq(io_tsi_tl_mem_pins_temp), Nil) + } +}) diff --git a/generators/testchipip b/generators/testchipip index 03af7aa5..5dae68ef 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 03af7aa53988dd96dffd613d1d50a5c6661e0a82 +Subproject commit 5dae68efbc925d09c6a8758064e88f6a3661baa2 From b7ef84860583bca6948f14d1518235077454de71 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 11:13:27 -0800 Subject: [PATCH 320/457] Add some docs on debugging --- docs/Simulation/FPGA-Prototyping.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index 0594b132..ba53a0b7 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -109,3 +109,19 @@ This example extends the default test harness and creates new ``Overlays`` to co .. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. See :ref:`Making a Bitstream` for information on the various make variables. + +Debugging with ILAs +~~~~~~~~~~~~~~~~~~~ + +Adding an ILA can be added to the design for debugging relevant signals. +First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). +Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). +After the changes are made, save the checkpoint and run the make invocation with the ``debug-bitstream`` target: +be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. +For example, running the bitstream build for an added ILA for a BOOM config.: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream + +For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. From 6aae66c54fe3653a3aeb294fa4bdd8843becd673 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 15:50:28 -0800 Subject: [PATCH 321/457] Add TSI Host Widget --- .../main/scala/vcu118/bringup/Configs.scala | 1 + .../scala/vcu118/bringup/CustomOverlays.scala | 208 +++++++++++++----- .../scala/vcu118/bringup/DigitalTop.scala | 2 - .../scala/vcu118/bringup/HarnessBinders.scala | 27 +++ .../main/scala/vcu118/bringup/IOBinders.scala | 14 +- .../scala/vcu118/bringup/TestHarness.scala | 26 +++ generators/testchipip | 2 +- 7 files changed, 217 insertions(+), 63 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 4c6cd5ad..f6e4880c 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -73,6 +73,7 @@ class WithBringupAdditions extends Config( new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ + new WithBringupTSIHost ++ new WithTSITLIOPassthrough ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 30a25afe..b138038d 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -4,10 +4,16 @@ import chisel3._ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.tilelink.{TLInwardNode} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.clocks._ +import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} + +import testchipip.{TSIHostParams, TSIHostWidgetIO} import chipyard.fpga.vcu118.{FMCPMap} @@ -144,58 +150,150 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } -//case class TSIShellInput() -//case class TSIDesignInput( -// -// )( -// implicit val p: Parameters)extends DDRDesignInput -// -//abstract class TSIOverlay(val params: TSIOverlayParams) -// extends IOOverlay[TLTSIWithDDRIO, TLTSIHostWidget] -//{ -// implicit val p = params.p -// -// // instantiate the tsi host widget and setup necessary connections -// val (tlTsiHost, tlTsiMemNode) = TLTSIHostWidget.attach(TSIHostWidgetAttachParams(params.tsiHostParams, params.controlBus)) -// val tlTsiHostIONodeSink = tlTsiHost.ioNode.makeSink -// -// // instantiate the DDR -// val size = p(TSIMigDDRSize) -// val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(params.tsiHostParams.targetBaseAddress, size)) -// val mig = LazyModule(new XilinxVCU118MIG(migParams)) -// val tsiIONode = BundleBridgeSource(() => new TSIHostWidgetIO(params.tsiHostParams.serialIfWidth)) -// val topTSIIONode = shell { tsiIONode.makeSink() } -// val ddrIONode = BundleBridgeSource(() => mig.module.io.cloneType) -// val topDDRIONode = shell { ddrIONode.makeSink() } -// val ddrUI = shell { ClockSourceNode(freqMHz = 200) } -// val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } -// areset := params.ddrParams.wrangler := ddrUI -// val asyncSink = LazyModule(new TLAsyncCrossingSink) -// val migClockReset = BundleBridgeSource(() => new Bundle { -// val clock = Output(Clock()) -// val reset = Output(Bool()) -// }) -// val migClockResetTop = shell { migClockReset.makeSink() } -// -// // connect them -// (mig.node := TLFragmenter(32,64,holdFirstDeny=true) := TLCacheCork() := TLSinkSetter(1 << 1) := TLSourceShrinker(1 << 4) := tlTsiMemNode) -// -// def designOutput = tlTsiHost -// def ioFactory = new TLTSIWithDDRIO(params.tsiHostParams.serialIfWidth, size) // top level io of the shell -// -// InModuleBody { -// val (t, _) = tsiIONode.out(0) -// val tsi = tlTsiHostIONodeSink.bundle -// tsi.serial_clock := t.serial_clock -// tsi.serial.in.bits := t.serial.in.bits -// tsi.serial.in.valid := t.serial.in.valid -// tsi.serial.out.ready := t.serial.out.ready -// t.serial.out.bits := tsi.serial.out.bits -// t.serial.out.valid := tsi.serial.out.valid -// t.serial.in.ready := tsi.serial.in.ready -// ddrIONode.bundle <> mig.module.io -// asyncSink.module.clock := migClockReset.bundle.clock -// asyncSink.module.reset := migClockReset.bundle.reset -// } -//} -// +case class TSIHostShellInput() +case class TSIHostDesignInput( + wrangler: ClockAdapterNode, + corePLL: PLLNode, + tsiHostParams: TSIHostParams, + node: BundleBridgeSource[TSIHostWidgetIO], + vc7074gbdimm: Boolean = false + )( + implicit val p: Parameters) +case class TSIHostOverlayOutput(ddr: TLInwardNode) +trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] + +class TSIHostWithDDRIO(val w: Int, val size: BigInt) extends Bundle { + val tsi = new TSIHostWidgetIO(w) + val ddr = new XilinxVCU118MIGPads(size) +} + +case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil) + +abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput) + extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] +{ + implicit val p = di.p +} + +case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB +class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) + extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput) +{ + val size = p(TSIHostVCU118DDRSize) + + // connect the DDR + val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.tsiHostParams.targetBaseAddress, size)) + val mig = LazyModule(new XilinxVCU118MIG(migParams)) + val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val ddrUI = shell { ClockSourceNode(freqMHz = 200) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := ddrUI + + // connect the TSI serial + val tlTsiSerialSink = di.node.makeSink() + val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth)) + val topTSIIONode = shell { tsiIoNode.makeSink() } + + def overlayOutput = TSIHostOverlayOutput(ddr = mig.node) + def ioFactory = new TSIHostWithDDRIO(di.tsiHostParams.serialIfWidth, size) + + InModuleBody { + // connect MIG + ioNode.bundle <> mig.module.io + + // connect TSI serial + val tsiSourcePort = tsiIoNode.bundle + val tsiSinkPort = tlTsiSerialSink.bundle + tsiSinkPort.serial_clock := tsiSourcePort.serial_clock + tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits + tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid + tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready + tsiSinkPort.serial.in.bits := tsiSourcePort.serial.in.bits + tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid + tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready + } + + // connect the DDR port + shell { InModuleBody { + require (shell.sys_clock.get.isDefined, "Use of DDRVCU118Overlay depends on SysClockVCU118Overlay") + val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + val ddrPort = topIONode.bundle.port + io.ddr <> ddrPort + ui.clock := ddrPort.c0_ddr4_ui_clk + ui.reset := /*!ddrPort.mmcm_locked ||*/ ddrPort.c0_ddr4_ui_clk_sync_rst + ddrPort.c0_sys_clk_i := sys.clock.asUInt + ddrPort.sys_rst := sys.reset // pllReset + ddrPort.c0_ddr4_aresetn := !ar.reset + + // This was just copied from the SiFive example, but it's hard to follow. + // The pins are emitted in the following order: + // adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7] + val allddrpins = Seq( + "AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13] + "AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg + "AR25", "AU28", // ba[0->1] + "BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt + "BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15] + "AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31] + "BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47] + "BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63] + "BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7] + "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] + "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] + + (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + } } + + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) +} + +class BringupTSIHostVCU118PlacedOverlay(override val shell: VCU118ShellBasicOverlays, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) + extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) +{ + // connect the TSI port + shell { InModuleBody { + // connect TSI signals + val tsiPort = topTSIIONode.bundle + io.tsi <> tsiPort + + require(di.tsiHostParams.serialIfWidth == 4) + + val clkIo = IOPin(io.tsi.serial_clock) + val packagePinsWithPackageIOs = Seq( + (FMCPMap("D8"), clkIo), + (FMCPMap("D17"), IOPin(io.tsi.serial.out.ready)), + (FMCPMap("D18"), IOPin(io.tsi.serial.out.valid)), + (FMCPMap("D11"), IOPin(io.tsi.serial.out.bits, 0)), + (FMCPMap("D12"), IOPin(io.tsi.serial.out.bits, 1)), + (FMCPMap("D14"), IOPin(io.tsi.serial.out.bits, 2)), + (FMCPMap("D15"), IOPin(io.tsi.serial.out.bits, 3)), + (FMCPMap("D26"), IOPin(io.tsi.serial.in.ready)), + (FMCPMap("D27"), IOPin(io.tsi.serial.in.valid)), + (FMCPMap("D20"), IOPin(io.tsi.serial.in.bits, 0)), + (FMCPMap("D21"), IOPin(io.tsi.serial.in.bits, 1)), + (FMCPMap("D23"), IOPin(io.tsi.serial.in.bits, 2)), + (FMCPMap("D24"), IOPin(io.tsi.serial.in.bits, 3))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + } } + + // Don't add an IOB to the clock + (packagePinsWithPackageIOs take 1) foreach { case (pin, io) => { + shell.xdc.addIOB(io) + } } + + shell.sdc.addClock("TSI_CLK", clkIo, 50) + shell.sdc.addGroup(pins = Seq(clkIo)) + shell.xdc.clockDedicatedRouteFalse(clkIo) + } } +} + +class BringupTSIHostVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: TSIHostShellInput)(implicit val valName: ValName) + extends TSIHostShellPlacer[VCU118ShellBasicOverlays] { + def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index a9105e26..42ea7af2 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -10,7 +10,6 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} - // ------------------------------------ // BringupVCU118 DigitalTop // ------------------------------------ @@ -24,4 +23,3 @@ class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp - with testchipip.HasPeripheryTSIHostWidgetModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 531b3c8d..02b821b4 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -3,11 +3,16 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{Analog, IO, BaseModule} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} +import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} + import chipyard.{HasHarnessSignalReferences} import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} @@ -54,3 +59,25 @@ class WithBringupGPIO extends OverrideHarnessBinder({ } } } }) + +/*** TSI Host Widget ***/ +class WithBringupTSIHost extends OverrideHarnessBinder({ + (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link + + ports.head match { case tlPort: HeterogeneousBag[TLBundle] => + val tsiBundles = vcu118th.bringupOuter.tsiDdrClient.out.map(_._1) + val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType))) + tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io } + tsiDdrClientBundle <> tlPort + } + + ports.last match { case serialPort: TSIHostWidgetIO => + vcu118th.bringupOuter.io_tsi_serial_bb.bundle <> serialPort + } + } } + } +}) + + diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 32badd2a..87763cde 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} -import testchipip.{HasPeripheryTSIHostWidget} +import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} import chipyard.iobinders.{OverrideIOBinder} @@ -35,9 +35,13 @@ class WithI2CIOPassthrough extends OverrideIOBinder({ class WithTSITLIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryTSIHostWidget) => { - require(system.tsiMem.size == 1) - val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiMem.head)).suggestName("tsi_tl_slave") - io_tsi_tl_mem_pins_temp <> system.tsiMem.head - (Seq(io_tsi_tl_mem_pins_temp), Nil) + require(system.tsiTLMem.size == 1) + val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave") + io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head + + require(system.tsiSerial.size == 1) + val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial") + io_tsi_serial_pins_temp <> system.tsiSerial.head + (Seq(io_tsi_tl_mem_pins_temp, io_tsi_serial_pins_temp), Nil) } }) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 8a4ae8fc..e3b4c137 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -17,8 +17,12 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ +import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter} + import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp} +import chipyard.{ChipTop} + class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness { /*** UART ***/ @@ -63,6 +67,28 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends placer.place(GPIODesignInput(params, io_gpio_bb(i))) } + /*** TSI Host Widget ***/ + require(dp(PeripheryTSIHostKey).size == 1) + + val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) + + val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) + val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dutWrangler.node, harnessSysPLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) + + // connect 1 mem. channel to the FPGA DDR + val inTsiParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: HasPeripheryTSIHostWidget => + lsys.tsiMemTLNodes.head.edges.in(0) + } + } + val tsiDdrClient = TLClientNode(Seq(inTsiParams.master)) + (tsiDdrPlaced.overlayOutput.ddr + := TLFragmenter(8,64,holdFirstDeny=true) + := TLCacheCork() + := TLAtomicAutomata(passthrough=false) + := TLSinkSetter(64) + := tsiDdrClient) + // module implementation override lazy val module = new BringupVCU118FPGATestHarnessImp(this) } diff --git a/generators/testchipip b/generators/testchipip index 5dae68ef..e956a60c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5dae68efbc925d09c6a8758064e88f6a3661baa2 +Subproject commit e956a60cbfd848c31bd849ffe0140eb0f9af2524 From 7baa1341ee221f8d3aa7feb1638508e9eed46575 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 16:34:45 -0800 Subject: [PATCH 322/457] Use 2nd system clock for TSI DDR | Small cleanups --- fpga/src/main/scala/vcu118/TestHarness.scala | 21 ++------ .../scala/vcu118/bringup/CustomOverlays.scala | 49 ++++++++++++++++--- .../scala/vcu118/bringup/TestHarness.scala | 14 +++++- 3 files changed, 59 insertions(+), 25 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d5a5481e..39f389f8 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -42,17 +42,14 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val topDesign = LazyModule(p(BuildTop)(dp)) // place all clocks in the shell - dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } + require(dp(ClockInputOverlayKey).size >= 1) + val sys_clk_placed = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()) /*** Connect/Generate clocks ***/ // connect to the PLL that will generate multiple clocks val harnessSysPLL = dp(PLLFactoryKey)() - sys_clock.get() match { - case Some(x : SysClockVCU118PlacedOverlay) => { - harnessSysPLL := x.node - } - } + harnessSysPLL := sys_clk_placed.overlayOutput.node // create and connect to the dutClock val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) @@ -60,14 +57,6 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL - // connect ref clock to dummy sink node - ref_clock.get() match { - case Some(x : RefClockVCU118PlacedOverlay) => { - val sink = ClockSinkNode(Seq(ClockSinkParameters())) - sink := x.node - } - } - /*** UART ***/ // 1st UART goes to the VCU118 dedicated UART @@ -110,9 +99,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod val reset_ibuf = Module(new IBUF) reset_ibuf.io.I := reset - val sysclk: Clock = _outer.sys_clock.get() match { - case Some(x: SysClockVCU118PlacedOverlay) => x.clock - } + val sysclk: Clock = _outer.sys_clk_placed.overlayOutput.node.out.head._1.clock val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) _outer.sdc.addAsyncPath(Seq(powerOnReset)) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index b138038d..23ed9f11 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -5,7 +5,7 @@ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.tilelink.{TLInwardNode} +import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ @@ -176,7 +176,7 @@ abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHos } case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB -class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) +class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput) { val size = p(TSIHostVCU118DDRSize) @@ -190,6 +190,14 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := ddrUI + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + // connect the TSI serial val tlTsiSerialSink = di.node.makeSink() val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth)) @@ -202,6 +210,10 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri // connect MIG ioNode.bundle <> mig.module.io + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + // connect TSI serial val tsiSourcePort = tsiIoNode.bundle val tsiSinkPort = tlTsiSerialSink.bundle @@ -216,10 +228,15 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri // connect the DDR port shell { InModuleBody { - require (shell.sys_clock.get.isDefined, "Use of DDRVCU118Overlay depends on SysClockVCU118Overlay") - val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + require (shell.sys_clock2.get.isDefined, "Use of TSIHostVCU118Overlay depends on SysClock2VCU118Overlay") + val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0) val (ui, _) = ddrUI.out(0) val (ar, _) = areset.in(0) + + // connect the async fifo sink to sys_clock2 + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + val ddrPort = topIONode.bundle.port io.ddr <> ddrPort ui.clock := ddrPort.c0_ddr4_ui_clk @@ -250,7 +267,7 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) } -class BringupTSIHostVCU118PlacedOverlay(override val shell: VCU118ShellBasicOverlays, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) +class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) { // connect the TSI port @@ -293,7 +310,25 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: VCU118ShellBasicOver } } } -class BringupTSIHostVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: TSIHostShellInput)(implicit val valName: ValName) - extends TSIHostShellPlacer[VCU118ShellBasicOverlays] { +class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val shellInput: TSIHostShellInput)(implicit val valName: ValName) + extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] { def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } + +class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) + extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) +{ + val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) } + + shell { InModuleBody { + shell.xdc.addPackagePin(io.p, "AW26") + shell.xdc.addPackagePin(io.n, "AW27") + shell.xdc.addIOStandard(io.p, "DIFF_SSTL12") + shell.xdc.addIOStandard(io.n, "DIFF_SSTL12") + } } +} +class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) + extends ClockInputShellPlacer[VCU118ShellBasicOverlays] +{ + def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index e3b4c137..0fd51108 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -70,10 +70,22 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends /*** TSI Host Widget ***/ require(dp(PeripheryTSIHostKey).size == 1) + // use the 2nd system clock for the 2nd DDR + val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) + val sys_clk2_placed = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()) + + val ddr2PLL = dp(PLLFactoryKey)() + ddr2PLL := sys_clk2_placed.overlayOutput.node + + val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val ddrWrangler = LazyModule(new ResetWrangler) + val ddrGroup = ClockGroup() + ddrClock := ddrWrangler.node := ddrGroup := ddr2PLL + val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dutWrangler.node, harnessSysPLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) + val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => From 98fcea7b572e2c0456a9f74096cea3b2482997c9 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 17:25:05 -0800 Subject: [PATCH 323/457] Adding initial Arty documentation; will be expanded further. --- docs/Simulation/FPGA-Prototyping.rst | 15 +++++++++++++++ fpga/src/main/scala/arty/Configs.scala | 3 ++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index ba53a0b7..ed07a7f4 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -54,6 +54,21 @@ However, like a software RTL simulation, you can also run the intermediate make Running a Design on Arty ------------------------ +Basic Design +~~~~~~~~~~~~ + +The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. +The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. +To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. +Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. + +.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala + :language: scala + :start-after: DOC include start: AbstractArty and Rocket + :end-before: DOC include end: AbstractArty and Rocket + +Future peripherals to be supported include the Arty's SPI Flash EEPROM. + Running a Design on VCU118 -------------------------- diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index bc62bcf9..61a6234c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -26,7 +26,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { debugIdleCycles = 5) case SerialTLKey => None // remove serialized tl port }) - +// DOC include start: AbstractArty and Rocket class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ @@ -41,3 +41,4 @@ class WithArtyTweaks extends Config( class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ new chipyard.TinyRocketConfig) +// DOC include start: AbstractArty and Rocket From e20311da84d85178ad0a2b16fd0a642feb2bc4a5 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 19:58:52 -0800 Subject: [PATCH 324/457] Adding implementation details for the Arty. --- docs/Simulation/FPGA-Prototyping.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index ed07a7f4..eacf3982 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -69,6 +69,12 @@ Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2 Future peripherals to be supported include the Arty's SPI Flash EEPROM. +Brief Implementation Description for Less Complicated Designs (Such as Arty), and Guidance for Adding/Changing Xilinx Collateral +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlay``s, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlay``s, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinder``s and ssIOBinder``s. + Running a Design on VCU118 -------------------------- From 8fb76dda7babad128f76d121bfd77c5155fbfa24 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 20:00:29 -0800 Subject: [PATCH 325/457] Fixed syntax. --- docs/Simulation/FPGA-Prototyping.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index eacf3982..6f82446e 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -73,7 +73,7 @@ Brief Implementation Description for Less Complicated Designs (Such as Arty), an ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. -This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlay``s, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlay``s, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinder``s and ssIOBinder``s. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``. Running a Design on VCU118 -------------------------- From 9144e3c70640b6be54759a76768bbe3469d01c22 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 6 Nov 2020 20:51:11 -0800 Subject: [PATCH 326/457] Fix pin mappings for TSI DDR --- fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 23ed9f11..1881d821 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -261,7 +261,7 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] - (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + (IOPin.of(io.ddr) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } } } shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) From c5e8fecb5c88f762969ef8755cb3e8c708b360e5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 21:00:18 -0800 Subject: [PATCH 327/457] Small renaming and cleanup --- fpga/src/main/scala/vcu118/TestHarness.scala | 16 ++++++++-------- .../main/scala/vcu118/bringup/TestHarness.scala | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 39f389f8..8b91c3ea 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -43,13 +43,13 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S // place all clocks in the shell require(dp(ClockInputOverlayKey).size >= 1) - val sys_clk_placed = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()) + val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node /*** Connect/Generate clocks ***/ // connect to the PLL that will generate multiple clocks val harnessSysPLL = dp(PLLFactoryKey)() - harnessSysPLL := sys_clk_placed.overlayOutput.node + harnessSysPLL := sysClkNode // create and connect to the dutClock val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) @@ -73,7 +73,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** DDR ***/ - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr // connect 1 mem. channel to the FPGA DDR val inParams = topDesign match { case td: ChipTop => @@ -82,7 +82,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } } val ddrClient = TLClientNode(Seq(inParams.master)) - ddrPlaced.overlayOutput.ddr := ddrClient + ddrNode := ddrClient // module implementation override lazy val module = new VCU118FPGATestHarnessImp(this) @@ -96,10 +96,10 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod _outer.xdc.addPackagePin(reset, "L19") _outer.xdc.addIOStandard(reset, "LVCMOS12") - val reset_ibuf = Module(new IBUF) - reset_ibuf.io.I := reset + val resetIBUF = Module(new IBUF) + resetIBUF.io.I := reset - val sysclk: Clock = _outer.sys_clk_placed.overlayOutput.node.out.head._1.clock + val sysclk: Clock = _outer.sysClkNode.out.head._1.clock val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) _outer.sdc.addAsyncPath(Seq(powerOnReset)) @@ -109,7 +109,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod case _ => false.B } - _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) + _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset) // reset setup val hReset = Wire(Reset()) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 0fd51108..95025dc7 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -72,10 +72,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends // use the 2nd system clock for the 2nd DDR val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) - val sys_clk2_placed = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()) + val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node val ddr2PLL = dp(PLLFactoryKey)() - ddr2PLL := sys_clk2_placed.overlayOutput.node + ddr2PLL := sysClk2Node val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) val ddrWrangler = LazyModule(new ResetWrangler) @@ -85,7 +85,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) + val tsiDdrNode = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)).overlayOutput.ddr // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => @@ -94,7 +94,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends } } val tsiDdrClient = TLClientNode(Seq(inTsiParams.master)) - (tsiDdrPlaced.overlayOutput.ddr + (tsiDdrNode := TLFragmenter(8,64,holdFirstDeny=true) := TLCacheCork() := TLAtomicAutomata(passthrough=false) From 9c12ce08b7f309fa19d8196d688d5dd70f82c71b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 7 Nov 2020 17:05:39 -0800 Subject: [PATCH 328/457] Create new prototyping section | Address some comments | Small clarifications --- docs/Chipyard-Basics/Chipyard-Components.rst | 10 +- docs/Prototyping/Arty.rst | 28 ++++ docs/Prototyping/General.rst | 68 +++++++++ docs/Prototyping/VCU118.rst | 55 +++++++ docs/Prototyping/index.rst | 17 +++ docs/Simulation/FPGA-Prototyping.rst | 148 ------------------- docs/Simulation/index.rst | 10 +- docs/index.rst | 2 + 8 files changed, 179 insertions(+), 159 deletions(-) create mode 100644 docs/Prototyping/Arty.rst create mode 100644 docs/Prototyping/General.rst create mode 100644 docs/Prototyping/VCU118.rst create mode 100644 docs/Prototyping/index.rst delete mode 100644 docs/Simulation/FPGA-Prototyping.rst diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 1d19a65f..3e45f99f 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -124,12 +124,14 @@ Sims In order to use FireSim, the repository must be cloned and executed on AWS instances. See :ref:`FireSim` for more information. +Prototyping +------------------------------------------- + **FPGA Prototyping** FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. - Some examples of FPGA's supported are Arty and VCU118. - For more accurate and deterministic simulation results, please consider using the :ref:`FireSim` platform. - See :ref:`FPGA Prototyping` for more information. - + Some examples of FPGAs supported are the Arty and VCU118 boards. + To instead do an fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. + See :ref:`Prototyping Flow` for more information on FPGA prototypes. VLSI ------------------------------------------- diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst new file mode 100644 index 00000000..fe36a4ef --- /dev/null +++ b/docs/Prototyping/Arty.rst @@ -0,0 +1,28 @@ +Running a Design on Arty +======================== + +Basic Design +------------ + +The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. +The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. +The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. +To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. +Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. + +.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala + :language: scala + :start-after: DOC include start: AbstractArty and Rocket + :end-before: DOC include end: AbstractArty and Rocket + +Future peripherals to be supported include the Arty's SPI Flash EEPROM. + +Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral +----------------------------------------------------------------------------------- + +The basis for the Arty design is the creation of a special test harness that connects the external FPGA IO (which exist as Xilinx IP blackboxes) to the Chipyard design. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. +However, unlike the more complicated ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects ``ChipTop`` IO to the ports of the external FPGA IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. +Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. +If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. +The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the ``ChipTop`` using ``HarnessBinders`` and ``IOBinders``. diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst new file mode 100644 index 00000000..d27cd66a --- /dev/null +++ b/docs/Prototyping/General.rst @@ -0,0 +1,68 @@ +General Setup and Usage +============================== + +Sources and Submodule Setup +--------------------------- + +All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard directory. +This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral. +However, the ``fpga-shells`` submodule repository is not initialized by default. +To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory: + +.. code-block:: shell + + # in the chipyard top level folder + ./scripts/init-fpga.sh + +Generating a Bitstream +------------------ + +Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation. +Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: + +.. code-block:: shell + + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bit + + # or + + make SUB_PROJECT= bit + +The ``SUB_PROJECT`` make variable is a way to meta make variable that sets all of the other make variables to a specific default. +For example: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 bit + + # converts to + + make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bit + +Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. +These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. +Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (ex. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override). +In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. +For example, building the BOOM configuration on the VCU118: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit + +That command will build the RTL and generate a bitstream using Vivado. +However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. + +Debugging with ILAs on Supported FPGAs +-------------------------------------- + +Adding an ILA (integrated logic analyzer) can be added to certain designs for debugging relevant signals. +First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). +Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). +This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. +For example, running the bitstream build for an added ILA for a BOOM config.: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream + +For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst new file mode 100644 index 00000000..a23b487e --- /dev/null +++ b/docs/Prototyping/VCU118.rst @@ -0,0 +1,55 @@ +Running a Design on VCU118 +========================== + +Basic Design +------------ + +The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. +This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). +To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala + :language: scala + :start-after: DOC include start: AbstractVCU118 and Rocket + :end-before: DOC include end: AbstractVCU118 and Rocket + +Brief Implementation Description + More Complicated Designs +----------------------------------------------------------- + +The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design. +This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target. +The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs. +Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral. +For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: UartOverlay + :end-before: DOC include end: UartOverlay + +Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. +The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``. +Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope). +This pattern is similar for all other ``Overlays`` in the test harness. +They must be "placed" and given a set of inputs (IOs, parameters). +The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: ClockOverlay + :end-before: DOC include end: ClockOverlay + +Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``. +For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design. + +After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. +This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). +For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. + +An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. +This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. + +.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. + For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. + See :ref:`Making a Bitstream` for information on the various make variables. diff --git a/docs/Prototyping/index.rst b/docs/Prototyping/index.rst new file mode 100644 index 00000000..695c588f --- /dev/null +++ b/docs/Prototyping/index.rst @@ -0,0 +1,17 @@ +Prototyping Flow +================ + +Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. +This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +FPGA prototyping allows for orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times and less design introspection. + +.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. + However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. + +.. toctree:: + :maxdepth: 2 + :caption: Prototyping Flow: + + General + VCU118 + Arty diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst deleted file mode 100644 index 6f82446e..00000000 --- a/docs/Simulation/FPGA-Prototyping.rst +++ /dev/null @@ -1,148 +0,0 @@ -FPGA Prototyping -============================== - -FPGA Prototyping ----------------- - -Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. -This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. -FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. - -.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. - However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. - -Sources and Submodule Setup ---------------------------- - -All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard folder. -This includes ``fpga-shells`` and the ``src`` folders that hold both Scala, TCL and other collateral. -However, the ``fpga-shells`` repository is not initialized by default. -To initialize the ``fpga-shells`` repository, run the included submodule script: - -.. code-block:: shell - - # in the chipyard top level folder - ./scripts/init-fpga.sh - -Making a Bitstream ------------------- - -Making a bitstream for any FPGA target is similar to building RTL for a software RTL simulation. -Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream: - -.. code-block:: shell - - make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... bit - - # or - - make SUB_PROJECT= bit - -By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. -These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. -Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (i.e. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override). -In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. -For example, building the BOOM configuration on the VCU118: - -.. code-block:: shell - - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit - -That command will build the RTL and generate a bitstream using Vivado. -However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. - -Running a Design on Arty ------------------------- - -Basic Design -~~~~~~~~~~~~ - -The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. -The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. -To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. -Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. - -.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala - :language: scala - :start-after: DOC include start: AbstractArty and Rocket - :end-before: DOC include end: AbstractArty and Rocket - -Future peripherals to be supported include the Arty's SPI Flash EEPROM. - -Brief Implementation Description for Less Complicated Designs (Such as Arty), and Guidance for Adding/Changing Xilinx Collateral -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. -This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``. - -Running a Design on VCU118 --------------------------- - -Basic Design -~~~~~~~~~~~~ - -The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. -This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). -To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. -Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. - -.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala - :language: scala - :start-after: DOC include start: AbstractVCU118 and Rocket - :end-before: DOC include end: AbstractVCU118 and Rocket - -Brief Implementation Description + More Complicated Designs -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design. -This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target. -The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs. -Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral. -For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``. - -.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala - :language: scala - :start-after: DOC include start: UartOverlay - :end-before: DOC include end: UartOverlay - -Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. -The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``. -Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope). -This pattern is similar for all other ``Overlays`` in the test harness. -They must be "placed" and given a set of inputs (IOs, parameters). -The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA. - -.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala - :language: scala - :start-after: DOC include start: ClockOverlay - :end-before: DOC include end: ClockOverlay - -Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``. -For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design. - -After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. -This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). -For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. - -An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. -This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. - -.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. - For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. - See :ref:`Making a Bitstream` for information on the various make variables. - -Debugging with ILAs -~~~~~~~~~~~~~~~~~~~ - -Adding an ILA can be added to the design for debugging relevant signals. -First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). -Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). -After the changes are made, save the checkpoint and run the make invocation with the ``debug-bitstream`` target: -be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. -For example, running the bitstream build for an added ILA for a BOOM config.: - -.. code-block:: shell - - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream - -For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index 24099bfb..9be1b2c9 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,18 +1,16 @@ Simulation ======================= -Chipyard supports three classes of simulation: +Chipyard supports two classes of simulation: #. Software RTL simulation using commercial or open-source (Verilator) RTL simulators #. FPGA-accelerated full-system simulation using FireSim -#. FPGA prototyping on ``fpga-shells`` platforms Software RTL simulators of Chipyard designs run at O(1 KHz), but compile -quickly and provide full waveforms. Conversely, FPGA-accelerated simulators and FPGA prototyping run +quickly and provide full waveforms. Conversely, FPGA-accelerated simulators run at O(100 MHz), making them appropriate for booting an operating system and running a complete workload, but have multi-hour compile times and poorer debug -visibility. However, FPGA-accelerated simulators differ from FPGA prototyping by providing deterministic -cycle-accurate results. +visibility. Click next to see how to run a simulation. @@ -22,5 +20,3 @@ Click next to see how to run a simulation. Software-RTL-Simulation FPGA-Accelerated-Simulation - FPGA-Prototyping - diff --git a/docs/index.rst b/docs/index.rst index d776b353..5efa417a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -45,6 +45,8 @@ Table of Contents TileLink-Diplomacy-Reference/index + Prototyping/index + Indices and tables ================== From 38a6bae872fa99428e00bcc051614b16bba9bd26 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 7 Nov 2020 17:27:19 -0800 Subject: [PATCH 329/457] Add CI for Arty/VCU118 (just verilog) --- .circleci/README.md | 18 ++++++++---- .circleci/check-commit.sh | 9 ++++++ .circleci/config.yml | 10 +++++++ .circleci/defaults.sh | 5 ++++ .circleci/do-fpga-rtl-build.sh | 52 ++++++++++++++++++++++++++++++++++ 5 files changed, 89 insertions(+), 5 deletions(-) create mode 100755 .circleci/do-fpga-rtl-build.sh diff --git a/.circleci/README.md b/.circleci/README.md index a50fc44a..0c53405d 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -34,11 +34,19 @@ Here the key is built from a string where the `checksum` portion converts the fi This directory contains all the collateral for the Chipyard CI to work. The following is included: - `build-toolchains.sh` # build either riscv-tools or esp-tools - `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work - `do-rtl-build.sh` # use verilator to build a sim executable (remotely) - `config.yml` # main circleci config script to enumerate jobs/workflows - `defaults.sh` # default variables used + `build-toolchains.sh` # build either riscv-tools or esp-tools + `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work + `do-rtl-build.sh` # use verilator to build a sim executable (remotely) + `config.yml` # main circleci config script to enumerate jobs/workflows + `defaults.sh` # default variables used + `check-commit.sh` # check that submodule commits are valid + `build-extra-tests.sh` # build default chipyard tests located in tests/ + `clean-old-files.sh` # clean up build server files + `do-fpga-rtl-build.sh` # similar to `do-rtl-build` but using fpga/ + `install-verilator.sh` # install verilator on build server + `run-firesim-scala-tests.sh` # run firesim scala tests + `run-tests.sh # run tests for a specific set of designs + `images/` # docker image used in CI How things are setup for Chipyard --------------------------------- diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 68cc975c..51e56449 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -120,6 +120,15 @@ dir="vlsi" branches=("master") search +submodules=("fpga-shells") +dir="fpga" +if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +then + branches=("master") +else + branches=("master" "dev") +fi +search # turn off verbose printing to make this easier to read set +x diff --git a/.circleci/config.yml b/.circleci/config.yml index 4ee84ced..f5130930 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -361,6 +361,12 @@ jobs: project-key: "firesim-multiclock" run-script: "run-firesim-scala-tests.sh" timeout: "20m" + prepare-chipyard-fpga: + executor: main-env + steps: + - prepare-rtl: + group-key: "group-fpga" + build-script: "do-fpga-rtl-build.sh" # Order and dependencies of jobs to run workflows: @@ -500,4 +506,8 @@ workflows: - install-verilator - build-extra-tests + # Prepare the fpga builds (just Verilog) + - prepare-chipyard-fpga: + requires: + - install-riscv-toolchain diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e628de7b..0b6b6fc9 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,6 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim +REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install @@ -52,6 +53,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spifl grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-other"]="icenet testchipip" +grouping["group-fpga"]="arty vcu118" # key value store to get the build strings declare -A mapping @@ -81,3 +83,6 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" + +mapping["arty"]="SUB_PROJECT=arty verilog" +mapping["vcu118"]="SUB_PROJECT=vcu118 verilog" diff --git a/.circleci/do-fpga-rtl-build.sh b/.circleci/do-fpga-rtl-build.sh new file mode 100755 index 00000000..29a5dac2 --- /dev/null +++ b/.circleci/do-fpga-rtl-build.sh @@ -0,0 +1,52 @@ +#!/bin/bash + +# create the different verilator builds +# argument is the make command string + +# turn echo on and error on earliest command +set -ex + +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +# call clean on exit +trap clean EXIT + +cd $LOCAL_CHIPYARD_DIR +./scripts/init-submodules-no-riscv-tools.sh + +# set stricthostkeychecking to no (must happen before rsync) +run "echo \"Ping $SERVER\"" + +clean + +# copy over riscv/esp-tools, and chipyard to remote +run "mkdir -p $REMOTE_CHIPYARD_DIR" +copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR + +run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" +run "cp -r ~/.sbt $REMOTE_WORK_DIR" + +TOOLS_DIR=$REMOTE_RISCV_DIR +LD_LIB_DIR=$REMOTE_RISCV_DIR/lib + +run "mkdir -p $REMOTE_RISCV_DIR" +copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR + +# enter the verilator directory and build the specific config on remote server +run "export RISCV=\"$TOOLS_DIR\"; \ + make -C $REMOTE_FPGA_DIR clean;" + +read -a keys <<< ${grouping[$1]} + +for key in "${keys[@]}" +do + run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -j$REMOTE_MAKE_NPROC -C $REMOTE_FPGA_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" +done + +run "rm -rf $REMOTE_CHIPYARD_DIR/project" From a559d624df583fa1968ac52ede8cd1bfb22356be Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 18:42:29 -0800 Subject: [PATCH 330/457] [clocking] Drive all buses directly from the asyncClockGroup --- .../src/main/scala/CustomBusTopologies.scala | 22 +++++++++++++++++-- .../chipyard/src/main/scala/Subsystem.scala | 17 ++++++++++++++ 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index c1c09285..db617f83 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -36,17 +36,35 @@ case class CoherentMulticlockBusTopologyParams( (SBUS, L2, TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()), (L2, MBUS, TLBusWrapperConnection.crossTo( xType = sbusToMbusXType, - driveClockFromMaster = Some(true), + driveClockFromMaster = None, nodeBinding = BIND_QUERY)) ) ) +// This differs from upstream only in that it does not use the legacy crossTo +// and crossFrom functions to ensure driveClockFromMaster = None +case class HierarchicalMulticlockBusTopologyParams( + pbus: PeripheryBusParams, + fbus: FrontBusParams, + cbus: PeripheryBusParams, + xTypes: SubsystemCrossingParams +) extends TLBusWrapperTopology( + instantiations = List( + (PBUS, pbus), + (FBUS, fbus), + (CBUS, cbus)), + connections = List( + (SBUS, CBUS, TLBusWrapperConnection(xType = xTypes.sbusToCbusXType, nodeBinding = BIND_STAR)()), + (CBUS, PBUS, TLBusWrapperConnection(xType = xTypes.cbusToPbusXType, nodeBinding = BIND_STAR)()), + (FBUS, SBUS, TLBusWrapperConnection(xType = xTypes.fbusToSbusXType, nodeBinding = BIND_QUERY, flipRendering = true)())) +) + // For subsystem/Configs.scala class WithMulticlockCoherentBusTopology extends Config((site, here, up) => { case TLNetworkTopologyLocated(InSubsystem) => List( JustOneBusTopologyParams(sbus = site(SystemBusKey)), - HierarchicalBusTopologyParams( + HierarchicalMulticlockBusTopologyParams( pbus = site(PeripheryBusKey), fbus = site(FrontBusKey), cbus = site(ControlBusKey), diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 5dd6ac18..40b8cc8c 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -56,6 +56,23 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem case b: BoomTile => b.module.core.coreMonitorBundle }.toList + + // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for + // bus-couplings that are not asynchronous strips the bus name from the sink + // ClockGroup. This makes it impossible to determine which clocks are driven + // by which bus based on the member names, which is problematic when there is + // a rational crossing between two buses. Instead, provide all bus clocks + // directly from the asyncClockGroupsNode in the subsystem to ensure bus + // names are always preserved in the top-level clock names. + // + // For example, using a RationalCrossing between the Sbus and Cbus, and + // driveClockFromMaster = Some(true) results in all cbus-attached device and + // bus clocks to be given names of the form "subsystem_sbus_[0-9]*". + // Conversly, if an async crossing is used, they instead receive names of the + // form "subsystem_cbus_[0-9]*". The assignment below the latter names in all cases. + Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc => + tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode } + } override lazy val module = new ChipyardSubsystemModuleImp(this) } From 244205e2b40aee6029627f1864b96ae427946f26 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 8 Nov 2020 17:49:32 -0800 Subject: [PATCH 331/457] Separate new sys_clk and ddr2 from TSI --- fpga/src/main/scala/vcu118/TestHarness.scala | 2 + .../main/scala/vcu118/bringup/Configs.scala | 5 +- .../scala/vcu118/bringup/CustomOverlays.scala | 142 +++--------------- .../scala/vcu118/bringup/TestHarness.scala | 17 ++- 4 files changed, 39 insertions(+), 127 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 3d1d438e..ae019e21 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -38,6 +38,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) + val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) + val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index f6e4880c..913a4fc2 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -19,7 +19,7 @@ import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} import chipyard.{BuildSystem} -import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} +import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size} class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) @@ -38,6 +38,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { List.empty[GPIOParams] } } + case TSIClockMaxFrequency => 100 case PeripheryTSIHostKey => List( TSIHostParams( serialIfWidth = 4, @@ -50,7 +51,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { sourceId = IdRange(0, (1 << 13))))), managerPortParams = TLSlavePortParameters.v1( managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), + address = Seq(AddressSet(0, site(VCU118DDR2Size) - 1)), regionType = RegionType.UNCACHED, executable = true, supportsGet = TransferSizes(1, 64), diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 1881d821..ef25cea3 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.clocks._ import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} -import testchipip.{TSIHostParams, TSIHostWidgetIO} +import testchipip.{TSIHostWidgetIO} import chipyard.fpga.vcu118.{FMCPMap} @@ -152,21 +152,13 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp case class TSIHostShellInput() case class TSIHostDesignInput( - wrangler: ClockAdapterNode, - corePLL: PLLNode, - tsiHostParams: TSIHostParams, - node: BundleBridgeSource[TSIHostWidgetIO], - vc7074gbdimm: Boolean = false + serialIfWidth: Int, + node: BundleBridgeSource[TSIHostWidgetIO] )( implicit val p: Parameters) -case class TSIHostOverlayOutput(ddr: TLInwardNode) +case class TSIHostOverlayOutput() trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] -class TSIHostWithDDRIO(val w: Int, val size: BigInt) extends Bundle { - val tsi = new TSIHostWidgetIO(w) - val ddr = new XilinxVCU118MIGPads(size) -} - case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil) abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput) @@ -177,43 +169,16 @@ abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHos case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) - extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput) + extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput) { - val size = p(TSIHostVCU118DDRSize) - - // connect the DDR - val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.tsiHostParams.targetBaseAddress, size)) - val mig = LazyModule(new XilinxVCU118MIG(migParams)) - val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) - val topIONode = shell { ioNode.makeSink() } - val ddrUI = shell { ClockSourceNode(freqMHz = 200) } - val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } - areset := designInput.wrangler := ddrUI - - // since this uses a separate clk/rst need to put an async crossing - val asyncSink = LazyModule(new TLAsyncCrossingSink()) - val migClkRstNode = BundleBridgeSource(() => new Bundle { - val clock = Output(Clock()) - val reset = Output(Bool()) - }) - val topMigClkRstIONode = shell { migClkRstNode.makeSink() } - - // connect the TSI serial val tlTsiSerialSink = di.node.makeSink() - val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth)) + val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth)) val topTSIIONode = shell { tsiIoNode.makeSink() } - def overlayOutput = TSIHostOverlayOutput(ddr = mig.node) - def ioFactory = new TSIHostWithDDRIO(di.tsiHostParams.serialIfWidth, size) + def overlayOutput = TSIHostOverlayOutput() + def ioFactory = new TSIHostWidgetIO(di.serialIfWidth) InModuleBody { - // connect MIG - ioNode.bundle <> mig.module.io - - // setup async crossing - asyncSink.module.clock := migClkRstNode.bundle.clock - asyncSink.module.reset := migClkRstNode.bundle.reset - // connect TSI serial val tsiSourcePort = tsiIoNode.bundle val tsiSinkPort = tlTsiSerialSink.bundle @@ -225,48 +190,9 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready } - - // connect the DDR port - shell { InModuleBody { - require (shell.sys_clock2.get.isDefined, "Use of TSIHostVCU118Overlay depends on SysClock2VCU118Overlay") - val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0) - val (ui, _) = ddrUI.out(0) - val (ar, _) = areset.in(0) - - // connect the async fifo sink to sys_clock2 - topMigClkRstIONode.bundle.clock := sys.clock - topMigClkRstIONode.bundle.reset := sys.reset - - val ddrPort = topIONode.bundle.port - io.ddr <> ddrPort - ui.clock := ddrPort.c0_ddr4_ui_clk - ui.reset := /*!ddrPort.mmcm_locked ||*/ ddrPort.c0_ddr4_ui_clk_sync_rst - ddrPort.c0_sys_clk_i := sys.clock.asUInt - ddrPort.sys_rst := sys.reset // pllReset - ddrPort.c0_ddr4_aresetn := !ar.reset - - // This was just copied from the SiFive example, but it's hard to follow. - // The pins are emitted in the following order: - // adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7] - val allddrpins = Seq( - "AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13] - "AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg - "AR25", "AU28", // ba[0->1] - "BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt - "BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15] - "AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31] - "BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47] - "BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63] - "BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7] - "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] - "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] - - (IOPin.of(io.ddr) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } - } } - - shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) } +case object TSIClockMaxFrequency extends Field[Int](50) // in MHz class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) { @@ -274,25 +200,25 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes shell { InModuleBody { // connect TSI signals val tsiPort = topTSIIONode.bundle - io.tsi <> tsiPort + io <> tsiPort - require(di.tsiHostParams.serialIfWidth == 4) + require(di.serialIfWidth == 4) - val clkIo = IOPin(io.tsi.serial_clock) + val clkIo = IOPin(io.serial_clock) val packagePinsWithPackageIOs = Seq( (FMCPMap("D8"), clkIo), - (FMCPMap("D17"), IOPin(io.tsi.serial.out.ready)), - (FMCPMap("D18"), IOPin(io.tsi.serial.out.valid)), - (FMCPMap("D11"), IOPin(io.tsi.serial.out.bits, 0)), - (FMCPMap("D12"), IOPin(io.tsi.serial.out.bits, 1)), - (FMCPMap("D14"), IOPin(io.tsi.serial.out.bits, 2)), - (FMCPMap("D15"), IOPin(io.tsi.serial.out.bits, 3)), - (FMCPMap("D26"), IOPin(io.tsi.serial.in.ready)), - (FMCPMap("D27"), IOPin(io.tsi.serial.in.valid)), - (FMCPMap("D20"), IOPin(io.tsi.serial.in.bits, 0)), - (FMCPMap("D21"), IOPin(io.tsi.serial.in.bits, 1)), - (FMCPMap("D23"), IOPin(io.tsi.serial.in.bits, 2)), - (FMCPMap("D24"), IOPin(io.tsi.serial.in.bits, 3))) + (FMCPMap("D17"), IOPin(io.serial.out.ready)), + (FMCPMap("D18"), IOPin(io.serial.out.valid)), + (FMCPMap("D11"), IOPin(io.serial.out.bits, 0)), + (FMCPMap("D12"), IOPin(io.serial.out.bits, 1)), + (FMCPMap("D14"), IOPin(io.serial.out.bits, 2)), + (FMCPMap("D15"), IOPin(io.serial.out.bits, 3)), + (FMCPMap("D26"), IOPin(io.serial.in.ready)), + (FMCPMap("D27"), IOPin(io.serial.in.valid)), + (FMCPMap("D20"), IOPin(io.serial.in.bits, 0)), + (FMCPMap("D21"), IOPin(io.serial.in.bits, 1)), + (FMCPMap("D23"), IOPin(io.serial.in.bits, 2)), + (FMCPMap("D24"), IOPin(io.serial.in.bits, 3))) packagePinsWithPackageIOs foreach { case (pin, io) => { shell.xdc.addPackagePin(io, pin) @@ -304,7 +230,7 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes shell.xdc.addIOB(io) } } - shell.sdc.addClock("TSI_CLK", clkIo, 50) + shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequency)) shell.sdc.addGroup(pins = Seq(clkIo)) shell.xdc.clockDedicatedRouteFalse(clkIo) } } @@ -314,21 +240,3 @@ class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val s extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] { def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } - -class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) - extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) -{ - val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) } - - shell { InModuleBody { - shell.xdc.addPackagePin(io.p, "AW26") - shell.xdc.addPackagePin(io.n, "AW27") - shell.xdc.addIOStandard(io.p, "DIFF_SSTL12") - shell.xdc.addIOStandard(io.n, "DIFF_SSTL12") - } } -} -class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) - extends ClockInputShellPlacer[VCU118ShellBasicOverlays] -{ - def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 95025dc7..6a4c8e2d 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -19,7 +19,7 @@ import sifive.blocks.devices.gpio._ import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter} -import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp} +import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer} import chipyard.{ChipTop} @@ -71,21 +71,22 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends require(dp(PeripheryTSIHostKey).size == 1) // use the 2nd system clock for the 2nd DDR - val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node val ddr2PLL = dp(PLLFactoryKey)() ddr2PLL := sysClk2Node - val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val ddrWrangler = LazyModule(new ResetWrangler) - val ddrGroup = ClockGroup() - ddrClock := ddrWrangler.node := ddrGroup := ddr2PLL + val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val ddr2Wrangler = LazyModule(new ResetWrangler) + val ddr2Group = ClockGroup() + ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) + val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetBaseAddress, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr + val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - val tsiDdrNode = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)).overlayOutput.ddr + dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.serialIfWidth, io_tsi_serial_bb)) // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => @@ -94,7 +95,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends } } val tsiDdrClient = TLClientNode(Seq(inTsiParams.master)) - (tsiDdrNode + (ddr2Node := TLFragmenter(8,64,holdFirstDeny=true) := TLCacheCork() := TLAtomicAutomata(passthrough=false) From 082b2304520a48c78f2a0dd1f8a98857c53df140 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 8 Nov 2020 17:51:21 -0800 Subject: [PATCH 332/457] Add missing file --- .../main/scala/vcu118/CustomOverlays.scala | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 fpga/src/main/scala/vcu118/CustomOverlays.scala diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala new file mode 100644 index 00000000..a58fb424 --- /dev/null +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -0,0 +1,110 @@ +package chipyard.fpga.vcu118 + +import chisel3._ + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} + +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.clocks._ +import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} + +class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) + extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) +{ + val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) } + + shell { InModuleBody { + shell.xdc.addPackagePin(io.p, "AW26") + shell.xdc.addPackagePin(io.n, "AW27") + shell.xdc.addIOStandard(io.p, "DIFF_SSTL12") + shell.xdc.addIOStandard(io.n, "DIFF_SSTL12") + } } +} +class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) + extends ClockInputShellPlacer[VCU118ShellBasicOverlays] +{ + def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +case object VCU118DDR2Size extends Field[BigInt](0x40000000L * 2) // 2GB +class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) + extends DDRPlacedOverlay[XilinxVCU118MIGPads](name, designInput, shellInput) +{ + val size = p(VCU118DDRSize) + + val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.baseAddress, size)) + val mig = LazyModule(new XilinxVCU118MIG(migParams)) + val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val ddrUI = shell { ClockSourceNode(freqMHz = 200) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := ddrUI + + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + + def overlayOutput = DDROverlayOutput(ddr = mig.node) + def ioFactory = new XilinxVCU118MIGPads(size) + + InModuleBody { + ioNode.bundle <> mig.module.io + + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + } + + shell { InModuleBody { + require (shell.sys_clock2.get.isDefined, "Use of DDRVCU118Overlay depends on SysClock2VCU118Overlay") + val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + + // connect the async fifo sync to sys_clock2 + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + + val port = topIONode.bundle.port + io <> port + ui.clock := port.c0_ddr4_ui_clk + ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst + port.c0_sys_clk_i := sys.clock.asUInt + port.sys_rst := sys.reset // pllReset + port.c0_ddr4_aresetn := !ar.reset + + // This was just copied from the SiFive example, but it's hard to follow. + // The pins are emitted in the following order: + // adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7] + val allddrpins = Seq( + "AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13] + "AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg + "AR25", "AU28", // ba[0->1] + "BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt + "BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15] + "AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31] + "BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47] + "BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63] + "BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7] + "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] + "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] + + (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + } } + + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) +} + +class DDR2VCU118ShellPlacer(shell: VCU118FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName) + extends DDRShellPlacer[VCU118FPGATestHarness] { + def place(designInput: DDRDesignInput) = new DDR2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + From 04cd6b59bdb9aff69164dc894a4704c7eabe4c36 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 18:45:48 -0800 Subject: [PATCH 333/457] [clocking] Add a fragment to set bus clock-sink freqs more intuitively --- .../src/main/scala/ConfigFragments.scala | 30 +++++++++++++++++++ .../chipyard/src/main/scala/Subsystem.scala | 2 +- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 0db4ed4c..fb706895 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -1,5 +1,6 @@ package chipyard.config +import scala.util.matching.Regex import chisel3._ import chisel3.util.{log2Up} @@ -11,6 +12,7 @@ import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, D import freechips.rocketchip.groundtest.{GroundTestSubsystem} import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} +import freechips.rocketchip.tilelink.{HasTLBusParams} import freechips.rocketchip.util.{AsyncResetReg, Symmetric} import freechips.rocketchip.prci._ @@ -183,6 +185,34 @@ class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble }) +class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => { + case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble +}) + +class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => { + case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ + Seq((cName: String) => site(key).dtsFrequency.flatMap { f => + re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble } + }) +}) + +/** + * Provides a diplomatic frequency for all clock sinks with an unspecified + * frequency bound to each bus. + * + * For example, the L2 cache, when bound to the sbus, receives a separate + * clock that appears as "subsystem_sbus_". This fragment ensures that + * clock requests the same frequency as the sbus itself. + */ + +class WithInheritBusFrequencyAssignments extends Config( + new BusFrequencyAssignment("subsystem_sbus_\\d+".r, SystemBusKey) ++ + new BusFrequencyAssignment("subsystem_pbus_\\d+".r, PeripheryBusKey) ++ + new BusFrequencyAssignment("subsystem_cbus_\\d+".r, ControlBusKey) ++ + new BusFrequencyAssignment("subsystem_fbus_\\d+".r, FrontBusKey) ++ + new BusFrequencyAssignment("subsystem_mbus_\\d+".r, MemoryBusKey) +) + /** * Mixins to specify crossing types between the 5 traditional TL buses * diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 40b8cc8c..09e35d95 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -69,7 +69,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem // driveClockFromMaster = Some(true) results in all cbus-attached device and // bus clocks to be given names of the form "subsystem_sbus_[0-9]*". // Conversly, if an async crossing is used, they instead receive names of the - // form "subsystem_cbus_[0-9]*". The assignment below the latter names in all cases. + // form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases. Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc => tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode } } From 4da9e49fc169d87da4462f8d244dfba53e67ffcb Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 21:24:04 -0800 Subject: [PATCH 334/457] [clocking] Fix up() invocations in freq specification fragments --- .../chipyard/src/main/scala/ConfigFragments.scala | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index fb706895..479120ba 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -242,16 +242,19 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, * up the diplomatic graph to the clock sources. */ class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case SystemBusKey => up(SystemBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case ControlBusKey => up(ControlBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) From 08c31014ccae0774c4621802c8ae1e812c515db0 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 21:29:31 -0800 Subject: [PATCH 335/457] Build out a more complete multiclock example configuration --- .../src/main/scala/CustomBusTopologies.scala | 2 +- .../main/scala/config/AbstractConfig.scala | 3 ++- .../src/main/scala/config/RocketConfigs.scala | 19 +++++++++++++------ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index db617f83..2f6f3de7 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -42,7 +42,7 @@ case class CoherentMulticlockBusTopologyParams( ) // This differs from upstream only in that it does not use the legacy crossTo -// and crossFrom functions to ensure driveClockFromMaster = None +// and crossFrom functions, and it ensures driveClockFromMaster = None case class HierarchicalMulticlockBusTopologyParams( pbus: PeripheryBusParams, fbus: FrontBusParams, diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 301c03d7..347b0c06 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -43,7 +43,8 @@ class AbstractConfig extends Config( new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified clocks will match the frequency specified by the pbus dtsFrequency parameter + new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index d413cc12..1afb4515 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,6 +1,7 @@ package chipyard import freechips.rocketchip.config.{Config} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // -------------- // Rocket Configs @@ -175,13 +176,19 @@ class MMIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class DividedClockRocketConfig extends Config( - new chipyard.config.WithTileFrequency(200.0) ++ - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore +class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.WithMemoryBusFrequency(50.0) ++ - new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing ++ + // Frequency specifications + new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) + new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency + new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz) + // Crossing specifications + new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS + new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( From 098a83ce98b0bf301bf53c486086c8ccbdf67086 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 21:57:18 -0800 Subject: [PATCH 336/457] [CI] Add a multiclock config --- .circleci/config.yml | 6 ++++++ .circleci/defaults.sh | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 6e74b9d5..f18f0e62 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -248,6 +248,12 @@ jobs: group-key: "group-cores" project-key: "chipyard-sodor" timeout: "30m" + chipyard-multiclock-rocket-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-cores" + project-key: "chipyard-multiclock-rocket" chipyard-dmirocket-run-tests: executor: main-env steps: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index c0bce62d..e9ccdfb5 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop" +grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -75,6 +75,7 @@ mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" +mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" From 230bd81e0eeebe02021f3a094ce88ce5f9a8e715 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 8 Nov 2020 11:20:24 -0800 Subject: [PATCH 337/457] [firechip] Update legacy firechip config --- generators/firechip/src/main/scala/TargetConfigs.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 89ac8073..e8f2afb5 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -201,8 +201,6 @@ class FireSimCVA6Config extends Config( //*********************************************************************************/ class FireSimMulticlockRocketConfig extends Config( new chipyard.config.WithTileFrequency(6400.0) ++ //lol - new WithDefaultFireSimBridges ++ - new WithDefaultMemModel ++ - new WithFireSimConfigTweaks ++ - new chipyard.DividedClockRocketConfig) + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new FireSimRocketConfig) From 714fb56423e612c49f82ba9badc2a026b12f681c Mon Sep 17 00:00:00 2001 From: dunn Date: Mon, 9 Nov 2020 14:56:54 -0800 Subject: [PATCH 338/457] Addressing PR comments in docs. --- docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- docs/Prototyping/Arty.rst | 22 +++++++++----------- docs/Prototyping/index.rst | 6 +++--- 3 files changed, 14 insertions(+), 16 deletions(-) diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 3e45f99f..ba6a8774 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -129,7 +129,7 @@ Prototyping **FPGA Prototyping** FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. - Some examples of FPGAs supported are the Arty and VCU118 boards. + Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards. To instead do an fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. See :ref:`Prototyping Flow` for more information on FPGA prototypes. diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst index fe36a4ef..d01cc5c2 100644 --- a/docs/Prototyping/Arty.rst +++ b/docs/Prototyping/Arty.rst @@ -4,25 +4,23 @@ Running a Design on Arty Basic Design ------------ -The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. -The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. -The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. -To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. -Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. +The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__. +The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC. +To extend this design, a user may create their own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. +Adding this config. fragment will enable and connect the JTAG and UART interfaces to your Chipyard design. .. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala :language: scala :start-after: DOC include start: AbstractArty and Rocket :end-before: DOC include end: AbstractArty and Rocket -Future peripherals to be supported include the Arty's SPI Flash EEPROM. +Future peripherals to be supported include the Arty 35T SPI Flash EEPROM, and I2C/PWM/SPI over the Arty 35T GPIO pins. These peripherals are available as part of sifive-blocks. Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral ----------------------------------------------------------------------------------- -The basis for the Arty design is the creation of a special test harness that connects the external FPGA IO (which exist as Xilinx IP blackboxes) to the Chipyard design. -This is done with the ``ArtyTestHarness`` in the basic default Arty target. -However, unlike the more complicated ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects ``ChipTop`` IO to the ports of the external FPGA IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. -Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. -If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. -The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the ``ChipTop`` using ``HarnessBinders`` and ``IOBinders``. +Like the VCU118, the basis for the Arty 35T design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. +This is done with the ``ArtyTestHarness`` in the basic default Arty 35T target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. +Unlike the VCU118 and other more complicated test harnesses, the Arty 35T Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. +If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``. +Examples of a simple ``IOBinder`` and ``HarnessBinder`` for routing signals (in this case the debug and JTAG resets) from the core to the test harness are the ``WithResetPassthrough`` and ``WithArtyResetHarnessBinder``. diff --git a/docs/Prototyping/index.rst b/docs/Prototyping/index.rst index 695c588f..118ce745 100644 --- a/docs/Prototyping/index.rst +++ b/docs/Prototyping/index.rst @@ -2,11 +2,11 @@ Prototyping Flow ================ Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. -This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board. FPGA prototyping allows for orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times and less design introspection. -.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. - However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. +.. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard. + However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells. .. toctree:: :maxdepth: 2 From 80487cc3710616c60871bf83a341ac4017607f82 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 10 Nov 2020 11:58:53 -0800 Subject: [PATCH 339/457] Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out} --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index 2f6f3de7..ee694d22 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -54,9 +54,9 @@ case class HierarchicalMulticlockBusTopologyParams( (FBUS, fbus), (CBUS, cbus)), connections = List( - (SBUS, CBUS, TLBusWrapperConnection(xType = xTypes.sbusToCbusXType, nodeBinding = BIND_STAR)()), - (CBUS, PBUS, TLBusWrapperConnection(xType = xTypes.cbusToPbusXType, nodeBinding = BIND_STAR)()), - (FBUS, SBUS, TLBusWrapperConnection(xType = xTypes.fbusToSbusXType, nodeBinding = BIND_QUERY, flipRendering = true)())) + (SBUS, CBUS, TLBusWrapperConnection. crossTo(xType = xTypes.sbusToCbusXType, driveClockFromMaster = None)), + (CBUS, PBUS, TLBusWrapperConnection. crossTo(xType = xTypes.cbusToPbusXType, driveClockFromMaster = None)), + (FBUS, SBUS, TLBusWrapperConnection.crossFrom(xType = xTypes.fbusToSbusXType, driveClockFromMaster = None))) ) // For subsystem/Configs.scala From 1110dd702cd02510f47e5a8cfd7bdbc88181a164 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 11 Nov 2020 18:57:16 +0000 Subject: [PATCH 340/457] Bump RC, firesim and barstools for chisel3.4 updates Note: firesim and barstools point to commits in the sifive forks of those repos I didn't update the URL in .gitmodules because I'm not sure how that works in a PR (because you wouldn't really want to merge sync'ing to the sifive repo). Requires: ucb-bar/barstools#92 and firesim/firesim#658 The version of rocket-chip, chisel3 and firrtl is chosen here because it is the latest known to pass my tests. You will likely want to bump further. --- generators/rocket-chip | 2 +- sims/firesim | 2 +- tools/barstools | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 6eb1a3de..577994e3 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 6eb1a3de082e27c752d9e4c1ae971c693cc192eb +Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e diff --git a/sims/firesim b/sims/firesim index 37fe89a6..f89d746a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 37fe89a65f1c1ccd8d2cc0d1efd0c06308d0224d +Subproject commit f89d746aa3c0c35c78a883c22c58679aeb9e2030 diff --git a/tools/barstools b/tools/barstools index 4a5c75fc..20d370be 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 4a5c75fcf85f03af858f1d7db04303d4b0733de7 +Subproject commit 20d370be496d3f9e873e5e63bf8d220727701dff diff --git a/tools/chisel3 b/tools/chisel3 index cc2971fe..d379dca4 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit cc2971feb15d4bc8cb4a8138b5a095ccbc92dcc3 +Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9 diff --git a/tools/firrtl b/tools/firrtl index c07da8a5..05d047a9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit c07da8a581789b88f7e6ffc98c8e810565034ad9 +Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9 From 7ca3be236cd5c3e1ab3f8b4b3b733727a60f54fd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 11:47:16 -0800 Subject: [PATCH 341/457] Bump bringup VCU118 | Ignore HTIF if no-debug module --- .gitmodules | 2 +- fpga/fpga-shells | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 1 - .../main/scala/vcu118/bringup/Configs.scala | 10 ++--- .../scala/vcu118/bringup/CustomOverlays.scala | 45 ++----------------- .../scala/vcu118/bringup/DigitalTop.scala | 3 +- .../scala/vcu118/bringup/HarnessBinders.scala | 13 ------ .../scala/vcu118/bringup/TestHarness.scala | 11 ----- .../chipyard/src/main/scala/Subsystem.scala | 4 +- generators/testchipip | 2 +- 10 files changed, 14 insertions(+), 79 deletions(-) diff --git a/.gitmodules b/.gitmodules index 8756fbc9..04c01f12 100644 --- a/.gitmodules +++ b/.gitmodules @@ -133,4 +133,4 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = git@github.com:sifive/fpga-shells.git + url = git@github.com:abejgonzalez/fpga-shells.git diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 89a5efec..fcfadb4c 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 89a5efec011ebc21b9455923501df70783161cb8 +Subproject commit fcfadb4cf36dfbcd7cfee525404b56bf661793b9 diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index a08ce0f2..77f03acf 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -28,7 +28,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { class WithSystemModifications extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module - case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS case SystemBusKey => up(SystemBusKey).copy( errorDevice = Some(DevNullParams( Seq(AddressSet(0x3000, 0xfff)), diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 913a4fc2..5e19cc5c 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy._ import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} -import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} @@ -23,7 +22,6 @@ import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) - case PeripherySPIKey => up(PeripherySPIKey, site) ++ List(SPIParams(rAddress = BigInt(0x64004000L))) case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { @@ -38,12 +36,13 @@ class WithBringupPeripherals extends Config((site, here, up) => { List.empty[GPIOParams] } } - case TSIClockMaxFrequency => 100 + case TSIClockMaxFrequencyKey => 100 case PeripheryTSIHostKey => List( TSIHostParams( serialIfWidth = 4, mmioBaseAddress = BigInt(0x64006000), mmioSourceId = 1 << 13, // manager source + targetSize = site(VCU118DDR2Size), serdesParams = TSIHostSerdesParams( clientPortParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( @@ -51,7 +50,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { sourceId = IdRange(0, (1 << 13))))), managerPortParams = TLSlavePortParameters.v1( managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0, site(VCU118DDR2Size) - 1)), + address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip regionType = RegionType.UNCACHED, executable = true, supportsGet = TransferSizes(1, 64), @@ -71,7 +70,6 @@ class WithBringupVCU118System extends Config((site, here, up) => { class WithBringupAdditions extends Config( new WithBringupUART ++ - new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ new WithBringupTSIHost ++ @@ -87,7 +85,7 @@ class RocketBringupConfig extends Config( new chipyard.RocketConfig) class BoomBringupConfig extends Config( - new WithFPGAFrequency(75) ++ + new WithFPGAFrequency(70) ++ new WithBringupAdditions ++ new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index ef25cea3..a47a6a3b 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -69,46 +69,7 @@ class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } -/* Connect SPI to ADI device */ -class BringupSPIVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) - extends SDIOXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - val packagePinsWithPackageIOs = Seq((FMCPMap("H37"), IOPin(io.spi_clk)), - (FMCPMap("H19"), IOPin(io.spi_cs)), - (FMCPMap("H17"), IOPin(io.spi_dat(0))), - (FMCPMap("H28"), IOPin(io.spi_dat(1))), - (FMCPMap("H29"), IOPin(io.spi_dat(2))), - (FMCPMap("H16"), IOPin(io.spi_dat(3)))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - } } - packagePinsWithPackageIOs drop 1 foreach { case (pin, io) => { - shell.xdc.addPullup(io) - shell.xdc.addIOB(io) - } } - } } -} - -class BringupSPIVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: SPIShellInput)(implicit val valName: ValName) - extends SPIShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -// TODO: Move this to a different location -// SPI device description for ADI part -class ADISPIDevice(spi: Device, maxMHz: Double = 1) extends SimpleDevice("clkgen", Seq("analog,adi9516-4")) { - override def parent = Some(spi) - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - val extra = Map("spi-max-frequency" -> Seq(ResourceInt(maxMHz * 1000000))) - Description(name, mapping ++ extra) - } -} - -/* Connect GPIOs to FMC */ +/* Connect GPIOs to FPGA I/Os */ abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) extends GPIOPlacedOverlay(name, di, si) { @@ -192,7 +153,7 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: } } -case object TSIClockMaxFrequency extends Field[Int](50) // in MHz +case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) { @@ -230,7 +191,7 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes shell.xdc.addIOB(io) } } - shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequency)) + shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey)) shell.sdc.addGroup(pins = Seq(clkIo)) shell.xdc.clockDedicatedRouteFalse(clkIo) } } diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index 42ea7af2..251ea8e9 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -10,8 +10,9 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} + // ------------------------------------ -// BringupVCU118 DigitalTop +// Bringup VCU118 DigitalTop // ------------------------------------ class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 02b821b4..27689ca8 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -27,17 +27,6 @@ class WithBringupUART extends ComposeHarnessBinder({ } }) -/*** SPI ***/ -class WithBringupSPI extends ComposeHarnessBinder({ - (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - require(ports.size == 2) - - vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last - } } - } -}) - /*** I2C ***/ class WithBringupI2C extends OverrideHarnessBinder({ (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { @@ -79,5 +68,3 @@ class WithBringupTSIHost extends OverrideHarnessBinder({ } } } }) - - diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 6a4c8e2d..2e86e646 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -36,17 +36,6 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb)) - /*** SPI ***/ - - require(dp(PeripherySPIKey).size == 2) - - // 2nd SPI goes to the ADI port - - val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - - val io_adi_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) - dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_adi_spi_bb)) - /*** I2C ***/ val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 5dd6ac18..20529ab5 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -11,7 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.prci._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} @@ -31,7 +31,7 @@ trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true - case _: HasPeripheryDebug if p(ExportDebug).dmi => true + case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true case _ => false }) { ResourceBinding { diff --git a/generators/testchipip b/generators/testchipip index e956a60c..9c0163ab 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e956a60cbfd848c31bd849ffe0140eb0f9af2524 +Subproject commit 9c0163ab9399cda10ed6da49bf959f5fefc3daaa From d5a0fd1a8e3ae47aa40ca3f522565b5d55083356 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:30:43 -0800 Subject: [PATCH 342/457] Address CircleCI --- .circleci/check-commit.sh | 7 +---- .circleci/config.yml | 7 +++-- .circleci/do-fpga-rtl-build.sh | 52 ---------------------------------- .circleci/do-rtl-build.sh | 29 +++++++++++++++---- 4 files changed, 29 insertions(+), 66 deletions(-) delete mode 100755 .circleci/do-fpga-rtl-build.sh diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 51e56449..ae05eb56 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -122,12 +122,7 @@ search submodules=("fpga-shells") dir="fpga" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] -then - branches=("master") -else - branches=("master" "dev") -fi +branches=("master") search # turn off verbose printing to make this easier to read diff --git a/.circleci/config.yml b/.circleci/config.yml index f5130930..25de2322 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -81,12 +81,15 @@ commands: build-script: type: string default: "do-rtl-build.sh" + build-type: + type: string + default: "sim" steps: - setup-tools: tools-version: "<< parameters.tools-version >>" - run: name: Building << parameters.group-key >> subproject using Verilator - command: .circleci/<< parameters.build-script >> << parameters.group-key >> + command: .circleci/<< parameters.build-script >> << parameters.group-key >> << parameters.build-type >> no_output_timeout: << parameters.timeout >> - save_cache: key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} @@ -366,7 +369,7 @@ jobs: steps: - prepare-rtl: group-key: "group-fpga" - build-script: "do-fpga-rtl-build.sh" + build-type: "fpga" # Order and dependencies of jobs to run workflows: diff --git a/.circleci/do-fpga-rtl-build.sh b/.circleci/do-fpga-rtl-build.sh deleted file mode 100755 index 29a5dac2..00000000 --- a/.circleci/do-fpga-rtl-build.sh +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/bash - -# create the different verilator builds -# argument is the make command string - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# call clean on exit -trap clean EXIT - -cd $LOCAL_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh - -# set stricthostkeychecking to no (must happen before rsync) -run "echo \"Ping $SERVER\"" - -clean - -# copy over riscv/esp-tools, and chipyard to remote -run "mkdir -p $REMOTE_CHIPYARD_DIR" -copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR - -run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" -run "cp -r ~/.sbt $REMOTE_WORK_DIR" - -TOOLS_DIR=$REMOTE_RISCV_DIR -LD_LIB_DIR=$REMOTE_RISCV_DIR/lib - -run "mkdir -p $REMOTE_RISCV_DIR" -copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR - -# enter the verilator directory and build the specific config on remote server -run "export RISCV=\"$TOOLS_DIR\"; \ - make -C $REMOTE_FPGA_DIR clean;" - -read -a keys <<< ${grouping[$1]} - -for key in "${keys[@]}" -do - run "export RISCV=\"$TOOLS_DIR\"; \ - export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ - export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_FPGA_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" -done - -run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 784dbc04..9780f64b 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -1,7 +1,11 @@ #!/bin/bash # create the different verilator builds -# argument is the make command string +# usage: +# do-rtl-build.sh sim +# run rtl build for simulations and copy back results +# do-rtl-build.sh fpga +# run rtl build for fpga and don't copy back results # turn echo on and error on earliest command set -ex @@ -50,9 +54,19 @@ else copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR fi +# choose what make dir to use +case $2 in + "sim") + REMOTE_MAKE_DIR=$REMOTE_SIM_DIR + ;; + "fpga") + REMOTE_MAKE_DIR=$REMOTE_FPGA_DIR + ;; +esac + # enter the verilator directory and build the specific config on remote server run "export RISCV=\"$TOOLS_DIR\"; \ - make -C $REMOTE_SIM_DIR clean;" + make -C $REMOTE_MAKE_DIR clean;" read -a keys <<< ${grouping[$1]} @@ -63,11 +77,14 @@ do export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" + make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" done run "rm -rf $REMOTE_CHIPYARD_DIR/project" -# copy back the final build -mkdir -p $LOCAL_CHIPYARD_DIR -copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR +# choose to copy back results +if [ $2 = "sim" ]; then + # copy back the final build + mkdir -p $LOCAL_CHIPYARD_DIR + copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR +fi From 999ae05bfe0dcf3cb3744a6f7171e21f1a7b792a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:31:34 -0800 Subject: [PATCH 343/457] Address some docs, build.sbt, .gitmodules --- .gitmodules | 2 +- build.sbt | 2 +- docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- docs/Prototyping/General.rst | 18 ++++++++++-------- docs/Prototyping/VCU118.rst | 8 ++++---- docs/Prototyping/index.rst | 1 - 6 files changed, 17 insertions(+), 16 deletions(-) diff --git a/.gitmodules b/.gitmodules index 04c01f12..17025437 100644 --- a/.gitmodules +++ b/.gitmodules @@ -133,4 +133,4 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = git@github.com:abejgonzalez/fpga-shells.git + url = https://github.com/abejgonzalez/fpga-shells.git diff --git a/build.sbt b/build.sbt index 0de63b3a..f7b8aabe 100644 --- a/build.sbt +++ b/build.sbt @@ -222,7 +222,7 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testOptions in Test += Tests.Argument("-oF") ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) - .dependsOn(rocketchip, sifive_blocks, chipyard) + .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val fpga_platforms = (project in file("./fpga")) diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index ba6a8774..f0d170f2 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -130,7 +130,7 @@ Prototyping **FPGA Prototyping** FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards. - To instead do an fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. + For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. See :ref:`Prototyping Flow` for more information on FPGA prototypes. VLSI diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index d27cd66a..b9fc5da3 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -4,7 +4,7 @@ General Setup and Usage Sources and Submodule Setup --------------------------- -All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard directory. +All FPGA prototyping-related collateral and sources are located in the ``fpga`` top-level Chipyard directory. This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral. However, the ``fpga-shells`` submodule repository is not initialized by default. To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory: @@ -22,22 +22,22 @@ Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you c .. code-block:: shell - make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bit + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bitstream # or - make SUB_PROJECT= bit + make SUB_PROJECT= bitstream The ``SUB_PROJECT`` make variable is a way to meta make variable that sets all of the other make variables to a specific default. For example: .. code-block:: shell - make SUB_PROJECT=vcu118 bit + make SUB_PROJECT=vcu118 bitstream # converts to - make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bit + make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bitstream Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. @@ -47,22 +47,24 @@ For example, building the BOOM configuration on the VCU118: .. code-block:: shell - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bitstream That command will build the RTL and generate a bitstream using Vivado. +The generated bitstream will be located in your designs specific build folder (``generated-src//obj``). However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. Debugging with ILAs on Supported FPGAs -------------------------------------- -Adding an ILA (integrated logic analyzer) can be added to certain designs for debugging relevant signals. +ILA (integrated logic analyzers) can be added to certain designs for debugging relevant signals. First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. +This will create a new bitstream called ``debug_output`` in the same location as the normal bitstream (``generated-src//obj``). For example, running the bitstream build for an added ILA for a BOOM config.: .. code-block:: shell make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream -For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. +.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index a23b487e..9deb8739 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -4,10 +4,10 @@ Running a Design on VCU118 Basic Design ------------ -The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. +The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory. This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. -Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. +Adding this config fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. .. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala :language: scala @@ -50,6 +50,6 @@ For more information on harness binders and io binders, refer to :ref:`IOBinders An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. -.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. - For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. +.. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. + For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. See :ref:`Making a Bitstream` for information on the various make variables. diff --git a/docs/Prototyping/index.rst b/docs/Prototyping/index.rst index 118ce745..ba0dff49 100644 --- a/docs/Prototyping/index.rst +++ b/docs/Prototyping/index.rst @@ -3,7 +3,6 @@ Prototyping Flow Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board. -FPGA prototyping allows for orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times and less design introspection. .. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard. However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells. From 55f19f79d3372f118c7cb784bbf081790c2e77e9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:39:29 -0800 Subject: [PATCH 344/457] Address fpga srcs --- .../src/main/resources/vcu118/sdboot/Makefile | 5 +- .../vcu118/sdboot/include/platform.h | 7 +- .../sdboot/include/riscv_test_defaults.h | 81 ------------------- .../vcu118/sdboot/linker/sdboot.elf.lds | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 11 +-- fpga/src/main/scala/vcu118/TestHarness.scala | 2 +- 6 files changed, 10 insertions(+), 98 deletions(-) delete mode 100644 fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h diff --git a/fpga/src/main/resources/vcu118/sdboot/Makefile b/fpga/src/main/resources/vcu118/sdboot/Makefile index b9c21470..e4636129 100644 --- a/fpga/src/main/resources/vcu118/sdboot/Makefile +++ b/fpga/src/main/resources/vcu118/sdboot/Makefile @@ -10,7 +10,10 @@ CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 CFLAGS+= -I $(ROOT_DIR)/include -I. LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds -#PBUS_CLK passed in +PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden + +default: elf bin dump + elf := $(BUILD_DIR)/sdboot.elf $(elf): head.S kprintf.c sd.c mkdir -p $(BUILD_DIR) diff --git a/fpga/src/main/resources/vcu118/sdboot/include/platform.h b/fpga/src/main/resources/vcu118/sdboot/include/platform.h index c240e0e5..21ebb0b3 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/platform.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/platform.h @@ -1,10 +1,9 @@ // See LICENSE for license details. -#ifndef _EAGLE_PLATFORM_H -#define _EAGLE_PLATFORM_H +#ifndef _CHIPYARD_PLATFORM_H +#define _CHIPYARD_PLATFORM_H #include "const.h" -#include "riscv_test_defaults.h" #include "devices/clint.h" #include "devices/gpio.h" #include "devices/plic.h" @@ -105,4 +104,4 @@ // Misc -#endif /* _SIFIVE_PLATFORM_H */ +#endif /* _CHIPYARD_PLATFORM_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h deleted file mode 100644 index c9212737..00000000 --- a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h +++ /dev/null @@ -1,81 +0,0 @@ -// See LICENSE.Sifive for license details. -#ifndef _RISCV_TEST_DEFAULTS_H -#define _RISCV_TEST_DEFAULTS_H - -#define TESTNUM x28 -#define TESTBASE 0x4000 - -#define RVTEST_RV32U \ - .macro init; \ - .endm - -#define RVTEST_RV64U \ - .macro init; \ - .endm - -#define RVTEST_RV32UF \ - .macro init; \ - /* If FPU exists, initialize FCSR. */ \ - csrr t0, misa; \ - andi t0, t0, 1 << ('F' - 'A'); \ - beqz t0, 1f; \ - /* Enable FPU if it exists. */ \ - li t0, MSTATUS_FS; \ - csrs mstatus, t0; \ - fssr x0; \ -1: ; \ - .endm - -#define RVTEST_RV64UF \ - .macro init; \ - /* If FPU exists, initialize FCSR. */ \ - csrr t0, misa; \ - andi t0, t0, 1 << ('F' - 'A'); \ - beqz t0, 1f; \ - /* Enable FPU if it exists. */ \ - li t0, MSTATUS_FS; \ - csrs mstatus, t0; \ - fssr x0; \ -1: ; \ - .endm - -#define RVTEST_CODE_BEGIN \ - .section .text.init; \ - .globl _prog_start; \ -_prog_start: \ - init; - -#define RVTEST_CODE_END \ - unimp - -#define RVTEST_PASS \ - fence; \ - li t0, TESTBASE; \ - li t1, 0x5555; \ - sw t1, 0(t0); \ -1: \ - j 1b; - -#define RVTEST_FAIL \ - li t0, TESTBASE; \ - li t1, 0x3333; \ - slli a0, a0, 16; \ - add a0, a0, t1; \ - sw a0, 0(t0); \ -1: \ - j 1b; - -#define EXTRA_DATA - -#define RVTEST_DATA_BEGIN \ - EXTRA_DATA \ - .align 4; .global begin_signature; begin_signature: - -#define RVTEST_DATA_END \ - _msg_init: .asciz "RUN\r\n"; \ - _msg_pass: .asciz "PASS"; \ - _msg_fail: .asciz "FAIL "; \ - _msg_end: .asciz "\r\n"; \ - .align 4; .global end_signature; end_signature: - -#endif /* _RISCV_TEST_DEFAULTS_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds index 7a0a42fe..6843436f 100644 --- a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds +++ b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds @@ -47,7 +47,7 @@ SECTIONS .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.dtb) + *(.dtb) /* Must be last if this code is added to RC's BootROM */ } >bootrom_mem :data PROVIDE(_data = ADDR(.rodata)); diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 77f03acf..07eefd19 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -28,16 +28,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { class WithSystemModifications extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module - case SystemBusKey => up(SystemBusKey).copy( - errorDevice = Some(DevNullParams( - Seq(AddressSet(0x3000, 0xfff)), - maxAtomic=site(XLen)/8, - maxTransfer=128, - region = RegionType.TRACKED))) - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = - Some(BigDecimal(site(FPGAFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) - case ControlBusKey => up(ControlBusKey, site).copy( - errorDevice = None) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for sdboot diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index ae019e21..cd88ff8e 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -41,7 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput())) - val topDesign = LazyModule(p(BuildTop)(dp)) + val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") // DOC include start: ClockOverlay // place all clocks in the shell From 63b3d4290fae5388ecec17f787ad9a127ac4ff91 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:39:47 -0800 Subject: [PATCH 345/457] Change NotSimulator to NoSimulator --- generators/utilities/src/main/scala/Simulator.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index 45939343..d7f4d007 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -11,7 +11,7 @@ case class GenerateSimConfig( sealed trait Simulator object VerilatorSimulator extends Simulator object VCSSimulator extends Simulator -object NotSimulator extends Simulator +object NoSimulator extends Simulator trait HasGenerateSimConfig { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { @@ -23,7 +23,7 @@ trait HasGenerateSimConfig { .action((x, c) => x match { case "verilator" => c.copy(simulator = VerilatorSimulator) case "vcs" => c.copy(simulator = VCSSimulator) - case "none" => c.copy(simulator = NotSimulator) + case "none" => c.copy(simulator = NoSimulator) case _ => throw new Exception(s"Unrecognized simulator $x") }) .text("Name of simulator to generate files for (verilator, vcs, none)") @@ -52,7 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case VerilatorSimulator => s"-FI ${fname}" // vcs pulls headers in with +incdir, doesn't have anything like verilator.h case VCSSimulator => "" - case _ => "" + case NoSimulator => "" } } else { // do nothing otherwise fname @@ -99,7 +99,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { "/csrc/remote_bitbang.cc", "/vsrc/EICG_wrapper.v", ) ++ (sim match { - case NotSimulator => Seq() + case NoSimulator => Seq() case _ => Seq( "/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimDRAM.cc", @@ -120,7 +120,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case VCSSimulator => Seq( "/vsrc/TestDriver.v", ) - case _ => Seq() + case NoSimulator => Seq() }) def writeBootrom(): Unit = { From d4d989ce0f38c22557074de7775156cf3389aa7f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:41:05 -0800 Subject: [PATCH 346/457] Rename make target to bitstream | Delete unused make stuff / tcl --- fpga/Makefile | 12 +----- fpga/scripts/write_mmi.tcl | 75 -------------------------------------- 2 files changed, 2 insertions(+), 85 deletions(-) delete mode 100644 fpga/scripts/write_mmi.tcl diff --git a/fpga/Makefile b/fpga/Makefile index fa6847ef..12bfd754 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -103,8 +103,8 @@ $(BIT_FILE): $(synth_list_f) -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ -board "$(BOARD)" -.PHONY: bit -bit: $(BIT_FILE) +.PHONY: bitstream +bitstream: $(BIT_FILE) .PHONY: debug-bitstream debug-bitstream: $(build_dir)/obj/post_synth.dcp @@ -116,14 +116,6 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp xcvu9p-flga2104-2l-e \ $(build_dir)/obj/debug_output -# Build .mcs -MCS_FILE := $(build_dir)/obj/$(MODEL).mcs -$(MCS_FILE): $(BIT_FILE) - cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< - -.PHONY: mcs -mcs: $(MCS_FILE) - ######################################################################################### # general cleanup rules ######################################################################################### diff --git a/fpga/scripts/write_mmi.tcl b/fpga/scripts/write_mmi.tcl deleted file mode 100644 index e577dd2b..00000000 --- a/fpga/scripts/write_mmi.tcl +++ /dev/null @@ -1,75 +0,0 @@ -proc write_mmi {filepath inst} { - current_instance - current_instance $inst - set chn [open $filepath w] - puts $chn "" - puts $chn "" - puts $chn "\t" - set brams [dict create] - foreach cell [get_cells -hierarchical -filter { PRIMITIVE_GROUP =~ BLOCKRAM }] { - set name [get_property RTL_RAM_NAME $cell] - dict update brams $name name { - dict lappend name cells $cell - dict set name size [get_property RTL_RAM_BITS $cell] - } - } - proc compare {a b} { - set a_addr [get_property bram_addr_begin $a] - set b_addr [get_property bram_addr_begin $b] - if {$a_addr > $b_addr} { - return 1 - } elseif {$a_addr < $b_addr} { - return -1 - } - set a_slice [get_property bram_slice_begin $a] - set b_slice [get_property bram_slice_begin $b] - if {$a_slice > $b_slice} { - return 1 - } elseif {$a_slice < $b_slice} { - return -1 - } - return 0 - } - dict for {name desc} $brams { - dict with desc { - puts $chn "\t\t> 3]\">" - puts $chn "\t\t\t" - foreach cell [lsort -command compare $cells] { - set type [switch [get_property REF_NAME $cell] \ - RAMB36E2 {expr {"RAMB32"}} \ - RAMB36E1 {expr {"RAMB32"}}] - set loc [lindex [split [get_property LOC $cell] "_"] 1] - set lsb [get_property bram_slice_begin $cell] - set msb [get_property bram_slice_end $cell] - set addr_bgn [get_property bram_addr_begin $cell] - set addr_end [get_property bram_addr_end $cell] - puts $chn "\t\t\t\t" - puts $chn "\t\t\t\t\t" - puts $chn "\t\t\t\t\t" - puts $chn "\t\t\t\t\t" - puts $chn "\t\t\t\t" - } - puts $chn "\t\t\t" - puts $chn "\t\t" - } - } - puts $chn "\t" - puts $chn "\t" - puts $chn "\t\t" - puts $chn "" - close $chn - current_instance - -} - -if {$argc != 3} { - puts $argc - puts {Error: Invalid number of arguments} - puts {Usage: write_mmi.tcl checkpoint mmi_file instance} -} - -lassign $argv checkpoint mmi_file instance - -open_checkpoint $checkpoint -write_mmi $mmi_file $instance From 1b4826ad82552375ca50d42542fb336fbfc0c5e9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 16:20:22 -0800 Subject: [PATCH 347/457] Generalize debug-bitstream --- docs/Prototyping/General.rst | 2 +- fpga/Makefile | 20 +++++---- fpga/scripts/run_impl_bitstream.tcl | 69 ++++++++++++++++++----------- 3 files changed, 55 insertions(+), 36 deletions(-) diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index b9fc5da3..a9a02af9 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -60,7 +60,7 @@ ILA (integrated logic analyzers) can be added to certain designs for debugging r First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. -This will create a new bitstream called ``debug_output`` in the same location as the normal bitstream (``generated-src//obj``). +This will create a new bitstream called ``top.bit`` in a folder named ``generated-src//debug_obj/``. For example, running the bitstream build for an added ILA for a BOOM config.: .. code-block:: shell diff --git a/fpga/Makefile b/fpga/Makefile index 12bfd754..1437d8bc 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -27,6 +27,7 @@ ifeq ($(SUB_PROJECT),vcu118) TB ?= none # unused TOP ?= ChipTop BOARD ?= vcu118 + FPGA_BRAND ?= xilinx endif ifeq ($(SUB_PROJECT),bringup) @@ -40,6 +41,7 @@ ifeq ($(SUB_PROJECT),bringup) TB ?= none # unused TOP ?= ChipTop BOARD ?= vcu118 + FPGA_BRAND ?= xilinx endif ifeq ($(SUB_PROJECT),arty) @@ -54,6 +56,7 @@ ifeq ($(SUB_PROJECT),arty) TB ?= none # unused TOP ?= ChipTop BOARD ?= arty + FPGA_BRAND ?= xilinx endif include $(base_dir)/variables.mk @@ -67,7 +70,7 @@ default: $(mcs) ######################################################################################### # misc. directories ######################################################################################### -fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx +fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND) fpga_common_script_dir := $(fpga_dir)/common/tcl ######################################################################################### @@ -98,10 +101,10 @@ $(BIT_FILE): $(synth_list_f) -nojournal -mode batch \ -source $(fpga_common_script_dir)/vivado.tcl \ -tclargs \ - -top-module "$(MODEL)" \ - -F "$(synth_list_f)" \ - -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ - -board "$(BOARD)" + -top-module "$(MODEL)" \ + -F "$(synth_list_f)" \ + -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" .PHONY: bitstream bitstream: $(BIT_FILE) @@ -112,9 +115,10 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp -nojournal -mode batch \ -source $(sim_dir)/scripts/run_impl_bitstream.tcl \ -tclargs \ - $(build_dir)/obj/post_synth.dcp \ - xcvu9p-flga2104-2l-e \ - $(build_dir)/obj/debug_output + $(build_dir)/obj/post_synth.dcp \ + $(BOARD) \ + $(build_dir)/debug_obj \ + $(fpga_common_script_dir) ######################################################################################### # general cleanup rules diff --git a/fpga/scripts/run_impl_bitstream.tcl b/fpga/scripts/run_impl_bitstream.tcl index ec3828e8..31175904 100644 --- a/fpga/scripts/run_impl_bitstream.tcl +++ b/fpga/scripts/run_impl_bitstream.tcl @@ -2,44 +2,59 @@ # argv[0] = absolute path to post_synth checkpoint file # argv[1] = part # argv[2] = output directory +# argv[3] = common fpga brand tcl set synth_checkpoint_file [lindex $argv 0] -set part [lindex $argv 1] -set output_dir [lindex $argv 2] +set board [lindex $argv 1] +set wrkdir [lindex $argv 2] + +set scriptdir [lindex $argv 3] + +# Set the variable for all the common files +set commondir [file dirname $scriptdir] + +# Set the variable that points to board specific files +set boarddir [file join [file dirname $commondir] $board] +source [file join $boarddir tcl board.tcl] # Set the project part to the part passed into this script -set_part ${part} +set_part $part_fpga -# Create output directory if it doesn't exist -file mkdir ${output_dir} -file mkdir ${output_dir}/reports -file mkdir ${output_dir}/outputs +# Create output directories if they doesn't exist +file mkdir $wrkdir +set rptdir [file join $wrkdir report] +file mkdir $rptdir # Load synthesis checkpoint -open_checkpoint ${synth_checkpoint_file} +open_checkpoint $synth_checkpoint_file -# Run implementation and save reports as needed +# opt opt_design +write_checkpoint -force [file join $wrkdir post_opt] + +# place place_design phys_opt_design -write_checkpoint -force ${output_dir}/outputs/post_place -report_timing_summary -file ${output_dir}/reports/post_place_timing_summary.rpt -report_drc -file ${output_dir}/reports/post_place_drc.rpt +write_checkpoint -force [file join $wrkdir post_place] +report_timing_summary -file [file join $rptdir post_place_timing_summary.rpt] +report_drc -file [file join $rptdir post_place_drc.rpt] + +# route route_design -write_checkpoint -force ${output_dir}/outputs/post_route -report_timing_summary -file ${output_dir}/reports/post_route_timing_summary.rpt -report_timing -sort_by group -max_paths 100 -path_type summary -file ${output_dir}/reports/post_route_timing.rpt -report_clock_utilization -file ${output_dir}/reports/post_route_clock_utilization.rpt -report_utilization -file ${output_dir}/reports/post_route_utilization.rpt -report_drc -file ${output_dir}/reports/post_route_drc.rpt -report_cdc -details -file ${output_dir}/reports/post_route_cdc.rpt -report_clock_interaction -file ${output_dir}/reports/post_route_clock_interaction.rpt -report_bus_skew -file ${output_dir}/reports/post_route_bus_skew.rpt -report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file ${output_dir}/reports/post_route_timing_violations.rpt +write_checkpoint -force [filel join $wrkdir post_route] +report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt] +report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt] +report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt] +report_utilization -file [file join $rptdir post_route_utilization.rpt] +report_drc -file [file join $rptdir post_route_drc.rpt] +report_cdc -details -file [file join $rptdir post_route_cdc.rpt] +report_clock_interaction -file [file join $rptdir post_route_clock_interaction.rpt] +report_bus_skew -file [file join $rptdir post_route_bus_skew.rpt] +report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file [file join $rptdir post_route_timing_violations.rpt] -write_verilog -force ${output_dir}/outputs/post_route.v -write_xdc -no_fixed_only -force ${output_dir}/outputs/post_route.xdc - -write_bitstream -force ${output_dir}/outputs/top.bit -write_debug_probes -force ${output_dir}/outputs/debug_nets.ltx +# bitstream +write_verilog -force [file join $wrkdir post_route.v] +write_xdc -no_fixed_only -force [file join $wrkdir post_route.xdc] +write_bitstream -force [file join $wrkdir top.bit] +write_debug_probes -force [file join $wrkdir debug_nets.ltx] From 61e1730c90f46ac9dcb3c91de36c95161ecfbe61 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 16:23:05 -0800 Subject: [PATCH 348/457] Small fix to docs --- docs/Prototyping/General.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index a9a02af9..a653f20a 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -22,7 +22,7 @@ Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you c .. code-block:: shell - make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bitstream + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... FPGA_BRAND=... bitstream # or @@ -37,7 +37,7 @@ For example: # converts to - make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bitstream + make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. From f8bd8eaa2799a446dbc8eb7593952f1152d6e04b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 16:24:10 -0800 Subject: [PATCH 349/457] Small fix to run_impl_bitstream --- fpga/scripts/run_impl_bitstream.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/scripts/run_impl_bitstream.tcl b/fpga/scripts/run_impl_bitstream.tcl index 31175904..8d9960c7 100644 --- a/fpga/scripts/run_impl_bitstream.tcl +++ b/fpga/scripts/run_impl_bitstream.tcl @@ -42,7 +42,7 @@ report_drc -file [file join $rptdir post_place_drc.rpt] # route route_design -write_checkpoint -force [filel join $wrkdir post_route] +write_checkpoint -force [file join $wrkdir post_route] report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt] report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt] report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt] From 06f90119f6ef6ef4d17fd169397baaf48dcbfd9a Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Sun, 15 Nov 2020 09:56:45 -0800 Subject: [PATCH 350/457] update example yml files --- vlsi/example-design.yml | 26 +++++++++++++++++++++++++- vlsi/example-tools.yml | 2 +- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index c277c916..49439de7 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,5 +10,29 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock", period: "2ns", uncertainty: "0.1ns"} ] + +# Specify pin properties +# Default pin placement can be set by the tool +# Default pin layer assignments can be found in some tech plug-ins +vlsi.inputs.pin_mode: generated +vlsi.inputs.pin.generate_mode: semi_auto + +# Specify the floorplan +# Default floor plan can be set by the tool +# The path name should match the VLSI_TOP makefile parameter if it is set +par.innovus.floorplan_mode: "auto" +vlsi.inputs.placement_constraints: +# - path: "ChipTop" + - path: "Gemmini" + type: toplevel + x: 0 + y: 0 + width: 300 + height: 300 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 diff --git a/vlsi/example-tools.yml b/vlsi/example-tools.yml index 52f5e373..1f86913f 100644 --- a/vlsi/example-tools.yml +++ b/vlsi/example-tools.yml @@ -14,7 +14,7 @@ synthesis.genus.version: "1813" vlsi.core.par_tool: "innovus" vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] vlsi.core.par_tool_path_meta: "append" -par.innovus.version: "181" +par.innovus.version: "191_ISR3" par.innovus.design_flow_effort: "standard" par.inputs.gds_merge: true # Calibre options From d7cc6b9963c50b9fd23e69b16a7a37936bbb3d53 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sun, 15 Nov 2020 10:00:40 -0800 Subject: [PATCH 351/457] update hammer basic flow doc --- docs/VLSI/Basic-Flow.rst | 106 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 8 deletions(-) diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 96504097..c616ff56 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -22,7 +22,7 @@ For example, for an imaginary process technology called tsmintel3: .. code-block:: shell cd vlsi - git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git + git clone git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git Next, we define the Hammer environment into the shell: @@ -34,19 +34,21 @@ Next, we define the Hammer environment into the shell: source $HAMMER_HOME/sourceme.sh +.. Note:: Some VLSI EDA tools are supported only on RHEL-based operating systems. We recommend using Chipyard on RHEL7 and above. However, many VLSI server still have old operating systems such as RHEL6, which have software packages older than the basic chipyard requirements. In order to build Chipyard on RHEL6, you will likely need to build from source gcc, git, gmake, make, dtc, cc, bison, libexpat and liby. + Setting up the Hammer Configuration Files -------------------------------------------- -The first configuration files that needs to be set up is the Hammer environment configuration files ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you need to fill the paths only for the tools that you will be using. +The first configuration file that needs to be set up is the Hammer environment configuration file ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you need to fill the paths only for the tools that you will be using. If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`Advanced Environment Setup` segment of this documentation page. Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``nangate45`` OpenRoad example), the generally applicable way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design. The ``vlsi`` directory includes three such example configuration files matching the three concerns: ``example-tools.yml``, ``example-tech.yml``, and ``example-design.yml``. -The ``example-tools.yml`` file configures which EDA tools hammer will use. This example files uses Cadence Innovus, Genus and Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). +The ``example-tools.yml`` file configures which EDA tools hammer will use. This example files uses Cadence Innovus, Genus and Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). Note that tool versions are highly sensitive to the process-technology in-use. Hence, tool versions that work with one process technology may not work with another (for example, ASAP7 will not work with an Innovus version newer than 18.1, while other proprietary process technologies will likely require newer versions such as 19.1). -The ``example-design.yml`` file contrain basic build system information (how many cores/threads to use, etc.), as well as configuration that are specific to the design we are working on such as clock signal, power modes, and additional contraints that we will add later on. +The ``example-design.yml`` file contrain basic build system information (how many cores/threads to use, etc.), as well as configuration that are specific to the design we are working on such as clock signal name and frequency, power modes, floorplan, and additional contraints that we will add later on. Finally, the ``example-tech`` file is a template file for a process technology plugin configuration. We will copy this file, and replace its fields with the appropriate process technology details for the tech plugin that we have access to. For example, for the ``asap7`` tech plugin we will replace the field with "asap7", the Node size "N" with "7", and the path to the process technology files installation directory. @@ -85,7 +87,7 @@ Synthesis ^^^^^^^^^ In order to run synthesis, we run ``make syn`` with the matching Make variables. -Post-synthesis logs and collateral will be saved in ``build/syn-rundir``. The raw QoR data wil be found in ``build/syn-rundir/reports``. +Post-synthesis logs and collateral will be saved in ``build//syn-rundir``. The raw QoR data (area, timing, gate counts, etc.) will be found in ``build//syn-rundir/reports``. Hence, if we want to monolitically synthesize the entire SoC, the relevant command would be .. code-block:: shell @@ -98,6 +100,84 @@ In a more typical scenario of working on a single module, for example the Gemmin make syn CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" +It is worth checking the final-qor.rpt report to make sure that the synthesized design meets timing before moving to the place-and-route step. + +Place-and-Route +^^^^^^^^^^^^^^^ +In order to run place-and-route, we run ``make par`` with the matching Make variables. +Post-PnR logs and collateral will be saved in ``build//par-rundir``. Specifically, the resulting GDSII file will be in that directory with the suffix ``*.gds``. and timing reports can be found in ``build//par-rundir/timingReports``. +Place-and-route is requires more design details in contrast to synthesis. For example, place-and-route requires some basic floorplanning constraints. The default ``example-design.yml`` configuration file template allows the tool (specifically, the Cadence Innovus tool) to use it's automatic floorplanning capability within the top level of the design (``ChipTop``). However, if we choose to place-and-route a specific block which is not the SoC top level, we need to change the top-level path name to match the ``VLSI_TOP`` make parameter we are using. + +Hence, if we want to monolitically place-and-route the entire SoC with the default tech plug-in parameters for power-straps and corners, the relevant command would be +.. code-block:: shell + + make par CONFIG= tech_name= INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + +In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, + +.. code-block:: shell + vlsi.inputs.placement_constraints: + - path: "Gemmini" + type: toplevel + x: 0 + y: 0 + width: 300 + height: 300 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + +The relevant ``make`` command would then be +.. code-block:: shell + + make par CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + + +Place-and-route generally requires more fine-grained input specifications regarding power nets, clock nets, pin assignments and floorplanning. While the template configuration files provide defaults for automatic tool defaults, these will usually result in very bad QoR, and therefore it is recommended to specify better-informed floorplans, pin assignments and power nets. For more information about cutomizing theses parameters, please refer to the :ref:`Customizing Your VLSI Flow in Hammer` sections or to the Hammer documentation. +Additionally, some Hammer process technology plugins do not provide sufficient default values for requires settings such as power nets and pin assignments (for example, ASAP7). In those cases, these contraint will need to be specified manually in the top-level configuration yml files, as is the case in the ``example-asap7.yml`` configuration file. + +Place-and-route tools are very sensitive to process technologes (significantly more sensitive than synthesis tools), and different process technologies may work only on specific tool versions. It is recommended to check what is the appropriate tool version for the specific process technology you are working with. + + +.. Note:: If you edit the yml configuration files in between synthesis and place-and-route, the `make par` command will automatically re-run synthesis. If you would like to avoid that and are confident that your configuration file changes do not affect synthesis results, you may use the `make redo-par` instead. + + + +Power Estimation +^^^^^^^^^^^^^^^^^^^^ + + + +Signoff +^^^^^^^^^ + +During chip tapeout, you will need to perform sign-off check to make sure the generated GDSII can be fabricated as intended. This is done using dedicated signoff tools that perform design rule checking (DRC) and layout versus schematic (LVS) verification. +In most cases, placed-and-routed designs will not pass DRC and LVS on first attempts due to nuanced design rules and silent failures of the place-and-route tools. Passing DRC and LVS will often requires adding manual placement constraints to "force" the EDA tools into certain patterns. +If you have placed-and-routed a design with the goal of getting area and power estimates, DRC and LVS are not strictly neccessary and the results will likely be quite similar. If you are intending to tapeout and fabricate a chip, DRC and LVS are mandatory and will likely requires multiple-iterations of refining manual placement constraints. + + +Since signoff checks are required only for a complete chip tapeout, they are currently not fully automated in Hammer, and often require some additional manual inclusion of custom Makefiles associated with specific process technologies. However, the general steps from running signoff within Hammer (under the assumption of a fully automated tech plug-in) are Make commands similar to the previous steps. + +In order to run DRC, the relevant ``make`` command is ``make drc``. As in the previous stages, the make command should be accompanied by the relevant configuration Make variables: + +.. code-block:: shell + + make drc CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + + +DRC does not emit autmated reports, but rather scripts that enable opening the DRC error database within the appropriate tool. These generated scripts can be called from ``./build//drc-rundir/generated-scripts/view_drc``. + + +In order to run LVS, the relevant ``make`` command is ``make lvs``. As in the previous stages, the make command should be accompanied by the relevant configuration Make variables: + +.. code-block:: shell + + make lvs CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" + +LVS does not emit autmated reports, but rather scripts that enable opening the LVS error database within the appropriate tool. These generated scripts can be called from ``./build//lvs-rundir/generated-scripts/view_lvs``. + Customizing Your VLSI Flow in Hammer ---------------------------------------- @@ -122,6 +202,16 @@ If you have access to a shared LSF cluster and you would like Hammer to submit i settings_meta: "append" -example-vlsi -^^^^^^^^^^^^ -This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. +Specifying a Custom Floorplan +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + + +Composing a Hierarchical Design +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + + +Customizing Generated Tcl Scripts +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The ``example-vlsi`` python script is the Hammer entry script with placeholders for hooks. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in the ``example-vlsi`` entry script example. In this particular example, a list of hooks is paased in the ``get_extra_par_hooks`` function in the ``ExampleDriver`` class. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. From c8add488ad0050b82eb55554cd44d5ec1937ffed Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 14:31:14 -0800 Subject: [PATCH 352/457] Reduce BOOM default freq. (play it safe) --- fpga/src/main/scala/vcu118/Configs.scala | 2 +- fpga/src/main/scala/vcu118/bringup/Configs.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 07eefd19..3c52f249 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -60,7 +60,7 @@ class RocketVCU118Config extends Config( // DOC include end: AbstractVCU118 and Rocket class BoomVCU118Config extends Config( - new WithFPGAFrequency(75) ++ + new WithFPGAFrequency(50) ++ new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 5e19cc5c..ec1ea1e3 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -85,7 +85,7 @@ class RocketBringupConfig extends Config( new chipyard.RocketConfig) class BoomBringupConfig extends Config( - new WithFPGAFrequency(70) ++ + new WithFPGAFrequency(50) ++ new WithBringupAdditions ++ new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) From d94a8efd4368763d141e6ee342c509a1fe19759d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 15:44:38 -0800 Subject: [PATCH 353/457] Fix TLMemPort comment | Use Option instead of NoSimulator --- fpga/src/main/scala/vcu118/DigitalTop.scala | 2 +- .../utilities/src/main/scala/Simulator.scala | 25 +++++++++---------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala index 9fe42bc8..d5c747fa 100644 --- a/fpga/src/main/scala/vcu118/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/DigitalTop.scala @@ -69,7 +69,7 @@ class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends // VCU118 Mem Port Mixin // ------------------------------------ -/** Adds a TileLink port to the system intended to master an MMIO device bus */ +/** Adds a port to the system intended to master an TL DRAM controller. */ trait CanHaveMasterTLMemPort { this: BaseSubsystem => private val memPortParamsOpt = p(ExtMem) private val portName = "tl_mem" diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index d7f4d007..fa157a36 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -5,13 +5,12 @@ import java.io.File case class GenerateSimConfig( targetDir: String = ".", dotFName: String = "sim_files.f", - simulator: Simulator = VerilatorSimulator, + simulator: Option[Simulator] = Some(VerilatorSimulator) ) sealed trait Simulator object VerilatorSimulator extends Simulator object VCSSimulator extends Simulator -object NoSimulator extends Simulator trait HasGenerateSimConfig { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { @@ -21,9 +20,9 @@ trait HasGenerateSimConfig { .abbr("sim") .valueName("") .action((x, c) => x match { - case "verilator" => c.copy(simulator = VerilatorSimulator) - case "vcs" => c.copy(simulator = VCSSimulator) - case "none" => c.copy(simulator = NoSimulator) + case "verilator" => c.copy(simulator = Some(VerilatorSimulator)) + case "vcs" => c.copy(simulator = Some(VCSSimulator)) + case "none" => c.copy(simulator = None) case _ => throw new Exception(s"Unrecognized simulator $x") }) .text("Name of simulator to generate files for (verilator, vcs, none)") @@ -49,10 +48,10 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { if (fname.takeRight(2) == ".h") { cfg.simulator match { // verilator needs to explicitly include verilator.h, so use the -FI option - case VerilatorSimulator => s"-FI ${fname}" + case Some(VerilatorSimulator) => s"-FI ${fname}" // vcs pulls headers in with +incdir, doesn't have anything like verilator.h - case VCSSimulator => "" - case NoSimulator => "" + case Some(VCSSimulator) => "" + case None => "" } } else { // do nothing otherwise fname @@ -84,7 +83,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { out.write(text) out.close() } - def resources(sim: Simulator): Seq[String] = Seq( + def resources(sim: Option[Simulator]): Seq[String] = Seq( "/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/testchip_tsi.cc", "/testchipip/csrc/testchip_tsi.h", @@ -99,7 +98,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { "/csrc/remote_bitbang.cc", "/vsrc/EICG_wrapper.v", ) ++ (sim match { - case NoSimulator => Seq() + case None => Seq() case _ => Seq( "/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimDRAM.cc", @@ -113,14 +112,14 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { "/csrc/remote_bitbang.cc", ) }) ++ (sim match { // simulator specific files to include - case VerilatorSimulator => Seq( + case Some(VerilatorSimulator) => Seq( "/csrc/emulator.cc", "/csrc/verilator.h", ) - case VCSSimulator => Seq( + case Some(VCSSimulator) => Seq( "/vsrc/TestDriver.v", ) - case NoSimulator => Seq() + case None => Seq() }) def writeBootrom(): Unit = { From ba59d0318fe8552d0b9018d9305ba0433ae1c40e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 16:14:38 -0800 Subject: [PATCH 354/457] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 20d370be..8e5757b5 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 20d370be496d3f9e873e5e63bf8d220727701dff +Subproject commit 8e5757b5ceb8a2c0246e3368baa5bc347dd6f99b From 70d43210d880a1257f864141d87fa5a4d6c6fe58 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 18:18:04 -0800 Subject: [PATCH 355/457] [temp] Unable to build/get past chisel-testers --- .sbtopts | 2 ++ build.sbt | 8 ++------ common.mk | 20 +------------------- generators/boom | 2 +- generators/cva6 | 2 +- generators/hwacha | 2 +- generators/riscv-sodor | 2 +- generators/sifive-blocks | 2 +- generators/sifive-cache | 2 +- project/build.properties | 2 +- project/plugins.sbt | 6 ++++-- tools/chisel-testers | 2 +- tools/firrtl-interpreter | 2 +- tools/treadle | 2 +- variables.mk | 8 +++++++- 15 files changed, 26 insertions(+), 38 deletions(-) create mode 100644 .sbtopts diff --git a/.sbtopts b/.sbtopts new file mode 100644 index 00000000..e6cc0650 --- /dev/null +++ b/.sbtopts @@ -0,0 +1,2 @@ +-Dsbt.sourcemode=true +-Dsbt.workspace=$PWD diff --git a/build.sbt b/build.sbt index bbf7964f..e6320076 100644 --- a/build.sbt +++ b/build.sbt @@ -14,7 +14,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.8" % "test", + libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.0" % "test", libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", @@ -77,11 +77,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => } toSeq // Subproject definitions begin -// -// FIRRTL is handled as an unmanaged dependency. Make will build the firrtl jar -// before launching sbt if any of the firrtl source files has been updated -// The jar is dropped in chipyard's lib/ directory, which is used as the unmanagedBase -// for all subprojects + lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) diff --git a/common.mk b/common.mk index ca34ffce..d0b11fe3 100644 --- a/common.mk +++ b/common.mk @@ -65,24 +65,6 @@ VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt -######################################################################################### -# jar creation variables and rules -######################################################################################### -FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar - -$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) - $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala - mkdir -p $(@D) - cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ - touch $@ - -$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) - cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly" - mkdir -p $(@D) - cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ - touch $@ - ######################################################################################### # Bloop Project Definitions ######################################################################################### @@ -93,7 +75,7 @@ $(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) ######################################################################################### # create list of simulation file inputs ######################################################################################### -$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS) +$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS) $(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name)) ######################################################################################### diff --git a/generators/boom b/generators/boom index dc22cacf..2dfec3d0 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit dc22cacf71fe88b95f3393d622f53648bf0440bd +Subproject commit 2dfec3d012e61ff07108af6034a86e60979deecd diff --git a/generators/cva6 b/generators/cva6 index 8a11e2c9..c2b9fc41 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 8a11e2c97627459d0449853447bfc7ca64608b82 +Subproject commit c2b9fc412179a386fb4b662d13e588a9613f41d5 diff --git a/generators/hwacha b/generators/hwacha index e29b65db..c1b7306f 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e29b65db86e4486ebdfd4f39d1265df83a2d7d9d +Subproject commit c1b7306f319aef6ea9ff0fd88d11d10244ee9e87 diff --git a/generators/riscv-sodor b/generators/riscv-sodor index d92a8476..cca8a7aa 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit d92a8476e4afbae189381d708136aef7d3970952 +Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c240e629..612ed01d 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c240e629e2fc111cbb12e4fe707be898b5204984 +Subproject commit 612ed01df3be83ad0198fb9bd7e367ea43df3d56 diff --git a/generators/sifive-cache b/generators/sifive-cache index 4ebefa3e..d4db623f 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 4ebefa3e30ec44bd2f4ff82747025fb7b362b954 +Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0 diff --git a/project/build.properties b/project/build.properties index 8522443d..0837f7a1 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.3.2 +sbt.version=1.3.13 diff --git a/project/plugins.sbt b/project/plugins.sbt index 3fe776fa..8c0937ed 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -5,16 +5,18 @@ resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") -addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0") +addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0") addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") -addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") +addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") +addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") +addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" diff --git a/tools/chisel-testers b/tools/chisel-testers index 1aa906fe..c5b99a45 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 1aa906fe168eb5ddca705ec955b27cf5c8856e4d +Subproject commit c5b99a452f84af3f581d34e9c51c6c65b6c2a63c diff --git a/tools/firrtl-interpreter b/tools/firrtl-interpreter index a881c07d..5ab0cfe7 160000 --- a/tools/firrtl-interpreter +++ b/tools/firrtl-interpreter @@ -1 +1 @@ -Subproject commit a881c07df6bceea462dbbd9a28e25721a1e88567 +Subproject commit 5ab0cfe7020ca17804078c85d020730764ee176f diff --git a/tools/treadle b/tools/treadle index 1c67bc84..925687ad 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit 1c67bc846aafc3bdd707f76ead8cefd5f93e0376 +Subproject commit 925687ad22c42dd2c8b4dc127c0476f9902b3163 diff --git a/variables.mk b/variables.mk index b187a23d..2828366c 100644 --- a/variables.mk +++ b/variables.mk @@ -154,6 +154,12 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M SCALA_VERSION=2.12.10 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar +# Running with sbt-launch.jar doesn't read .sbtopts by default +# # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) +sbtopts_file := $(base_dir)/.sbtopts +ifneq (,$(wildcard $(sbtopts_file))) + SBT_OPTS ?= $(shell cat $(sbtopts_file)) +endif BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop @@ -176,7 +182,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) $(SBT_OPTS) "project $(1)" "runMain $(2) $(3)" endef endif From 9d9813fe0abf8146aaade002ef06203b8065c491 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 16 Nov 2020 22:24:18 -0800 Subject: [PATCH 356/457] [temp] Following RC's way to build Chisel from source or Maven [ci skip] --- .sbtopts | 2 +- build.sbt | 25 ++++++++++++++++++++----- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/.sbtopts b/.sbtopts index e6cc0650..2358d787 100644 --- a/.sbtopts +++ b/.sbtopts @@ -1,2 +1,2 @@ -Dsbt.sourcemode=true --Dsbt.workspace=$PWD +-Dsbt.workspace=$PWD/tools diff --git a/build.sbt b/build.sbt index e6320076..cffc235d 100644 --- a/build.sbt +++ b/build.sbt @@ -78,7 +78,15 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -lazy val chisel = (project in file("tools/chisel3")) +// This needs to stay in sync with the chisel3 and firrtl git submodules +val chiselVersion = "3.4.0" + +lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") +lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +// While not built from source, *must* be in sync with the chisel3 git submodule +// Building from source requires extending sbt-sriracha or a similar plugin and +// keeping scalaVersion in sync with chisel3 to the minor version +lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) @@ -87,7 +95,9 @@ lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(chisel, firrtl_interpreter, treadle) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(firrtl_interpreter, treadle) + .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( @@ -113,15 +123,18 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(hardfloat, rocketMacros, rocketConfig) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) - .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .dependsOn(chisel) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) @@ -184,7 +197,9 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .dependsOn(chisel, chisel_testers) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(chisel_testers) + .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( From a0d479f3ea996524c9a57a65dff4128b2da5604f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 16 Nov 2020 22:55:04 -0800 Subject: [PATCH 357/457] Working FIRRTL/RC/Chisel3 build | chisel-testers still broken --- build.sbt | 27 +++++++++------------------ project/plugins.sbt | 2 +- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/build.sbt b/build.sbt index cffc235d..27b08a3b 100644 --- a/build.sbt +++ b/build.sbt @@ -79,14 +79,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin // This needs to stay in sync with the chisel3 and firrtl git submodules -val chiselVersion = "3.4.0" - -lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") -lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion -// While not built from source, *must* be in sync with the chisel3 git submodule -// Building from source requires extending sbt-sriracha or a similar plugin and -// keeping scalaVersion in sync with chisel3 to the minor version -lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full +lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) @@ -95,9 +88,7 @@ lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .sourceDependency(chiselRef, chiselLib) - .dependsOn(firrtl_interpreter, treadle) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(firrtl_interpreter, treadle, chisel) .settings( commonSettings, libraryDependencies ++= Seq( @@ -123,18 +114,20 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .sourceDependency(chiselRef, chiselLib) - .dependsOn(hardfloat, rocketMacros, rocketConfig) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(hardfloat, rocketMacros, rocketConfig, chisel) .settings(commonSettings) + .settings( // Settings for scalafix + semanticdbEnabled := true, + semanticdbVersion := scalafixSemanticdb.revision, + scalacOptions += "-Ywarn-unused-import" + ) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .sourceDependency(chiselRef, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(chisel) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) @@ -197,9 +190,7 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .sourceDependency(chiselRef, chiselLib) .dependsOn(chisel_testers) - .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( diff --git a/project/plugins.sbt b/project/plugins.sbt index 8c0937ed..b6fe132a 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -13,7 +13,7 @@ addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") -addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") +addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") From 1b00d540f0a964dfbe86449df6491eda7910d639 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Nov 2020 15:14:30 -0800 Subject: [PATCH 358/457] Add config fragment for replacing L2 with broadcastManager --- generators/chipyard/src/main/scala/ConfigFragments.scala | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 479120ba..c5c85e47 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -151,6 +151,11 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) +// Replaces the L2 with a broadcast manager for maintaining coherence +class WithBroadcastManager extends Config((site, here, up) => { + case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) +}) + class WithHwachaTest extends Config((site, here, up) => { case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { up(TestSuitesKey).apply(tileParams, suiteHelper, p) From 95e83651051e9ee49c5fed2e67cfb90e42f6b458 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 18 Nov 2020 16:53:37 -0800 Subject: [PATCH 359/457] Small change to Arty reset binder name, per Jerry's PR comment. --- fpga/src/main/scala/arty/IOBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala index 205f8fcc..78a1f0ee 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.devices.debug._ import chipyard.iobinders.{ComposeIOBinder} -class WithResetPassthrough extends ComposeIOBinder({ +class WithDebugResetPassthrough extends ComposeIOBinder({ (system: HasPeripheryDebugModuleImp) => { // Debug module reset val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset") From 5b1b4b3efe65299360a0de838bcc2c7025880b38 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 15:28:24 -0800 Subject: [PATCH 360/457] Bump Gemmini/Hwacha/Sha3 --- generators/gemmini | 2 +- generators/hwacha | 2 +- generators/sha3 | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/gemmini b/generators/gemmini index caaf781e..371bc330 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit caaf781ec9d69e45443e496046bc6ab439e3e54f +Subproject commit 371bc33038e633779f52e26eaa0031f2820c2f0d diff --git a/generators/hwacha b/generators/hwacha index c1b7306f..e0109674 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit c1b7306f319aef6ea9ff0fd88d11d10244ee9e87 +Subproject commit e0109674572f4b40641a89db9e0429e51b5cb73a diff --git a/generators/sha3 b/generators/sha3 index 762d9d08..a4ea9602 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 762d9d08f8ccd96ba7ab12ead6d38a6b57fa8710 +Subproject commit a4ea960248fdf8267b515723d472b018b09ac24f From 222580a290ec243d8cc97154b61d5e1467b35c69 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 16:13:58 -0800 Subject: [PATCH 361/457] Bump dsptools --- tools/dsptools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dsptools b/tools/dsptools index e32ab8a0..ce6d87b2 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit e32ab8a0c77d419b52376064534090ff2583929d +Subproject commit ce6d87b2f23bf87085e4913e8324513147f43488 From 571e7517eb57deb10ad32e0e8e2d0ec1aaec036f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 20:06:28 -0800 Subject: [PATCH 362/457] Bump barstools, chisel-testers, dsptools | Split build.sbt dependencies between projects | Bump CY collateral --- .gitmodules | 2 +- build.sbt | 78 ++++++++++++------- .../scala/clocking/ResetSynchronizer.scala | 30 ------- .../src/main/scala/example/NodeTypes.scala | 8 +- .../src/main/scala/example/TutorialTile.scala | 2 + tools/barstools | 2 +- tools/chisel-testers | 2 +- tools/dsptools | 2 +- 8 files changed, 60 insertions(+), 66 deletions(-) delete mode 100644 generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala diff --git a/.gitmodules b/.gitmodules index 7054c14f..55b4be56 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/freechipsproject/chisel-testers.git + url = https://github.com/abejgonzalez/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/build.sbt b/build.sbt index 27b08a3b..77a0962a 100644 --- a/build.sbt +++ b/build.sbt @@ -14,14 +14,11 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.0" % "test", - libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", + libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.2" % "test", + libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", + libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", - libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", - libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", - libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -72,9 +69,9 @@ def freshProject(name: String, dir: File): Project = { // Fork each scala test for now, to work around persistent mutable state // in Rocket-Chip based generators def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => - val options = ForkOptions() - new Group(test.name, Seq(test), SubProcess(options)) - } toSeq + val options = ForkOptions() + new Group(test.name, Seq(test), SubProcess(options)) +} toSeq // Subproject definitions begin @@ -82,22 +79,32 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + )) lazy val treadle = (project in file("tools/treadle")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + "com.github.scopt" %% "scopt" % "3.7.1", + "org.json4s" %% "json4s-native" % "3.6.10" + )) lazy val chisel_testers = (project in file("tools/chisel-testers")) .dependsOn(firrtl_interpreter, treadle, chisel) .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.12", - "org.scalatest" %% "scalatest" % "3.0.5", - "org.scalacheck" %% "scalacheck" % "1.14.0", - "com.github.scopt" %% "scopt" % "3.7.0" - ) - ) + commonSettings, + libraryDependencies ++= Seq( + "junit" % "junit" % "4.13", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1", + "org.scalacheck" %% "scalacheck" % "1.14.3", + "com.github.scopt" %% "scopt" % "3.7.1" + )) // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS @@ -170,7 +177,11 @@ lazy val sha3 = (project in file("generators/sha3")) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scalanlp" %% "breeze" % "0.13.2" + )) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) @@ -182,26 +193,37 @@ lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeo .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "com.typesafe.play" %% "play-json" % "2.6.10" + )) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .dependsOn(firrtl_interpreter, mdf, rocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) +val dsptoolsDependencies = Seq( + "org.scalanlp" %% "breeze" % "1.0", + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" +) + lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.0.8", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" - )) + commonSettings, + libraryDependencies ++= dsptoolsDependencies + ) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= dsptoolsDependencies + ) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) diff --git a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala deleted file mode 100644 index 2ba8e855..00000000 --- a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala +++ /dev/null @@ -1,30 +0,0 @@ - -package chipyard.clocking - -import chisel3._ - -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.util.{ResetCatchAndSync} - -/** - * Instantiates a reset synchronizer on all clock-reset pairs in a clock group - */ -class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { - val node = ClockGroupAdapterNode() - lazy val module = new LazyRawModuleImp(this) { - (node.out zip node.in).map { case ((oG, _), (iG, _)) => - (oG.member.data zip iG.member.data).foreach { case (o, i) => - o.clock := i.clock - o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) - } - } - } -} - -object ClockGroupResetSynchronizer { - def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node -} - - diff --git a/generators/chipyard/src/main/scala/example/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala index 0e2b6565..914e5ba5 100644 --- a/generators/chipyard/src/main/scala/example/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala @@ -11,7 +11,7 @@ import testchipip.TLHelper // DOC include start: MyClient class MyClient(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeClientNode(TLClientParameters( + val node = TLHelper.makeClientNode(TLMasterParameters.v1( name = "my-client", sourceId = IdRange(0, 4), requestFifo = true, @@ -29,7 +29,7 @@ class MyClient(implicit p: Parameters) extends LazyModule { class MyManager(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("my-device", Seq("tutorial,my-device0")) val beatBytes = 8 - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x20000, 0xfff)), resources = device.reg, regionType = RegionType.UNCACHED, @@ -83,7 +83,7 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule { // DOC include start: MyManagerGroup class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x0, 0xfff)))) lazy val module = new LazyModuleImp(this) { @@ -92,7 +92,7 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule { } class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x1000, 0xfff)))) lazy val module = new LazyModuleImp(this) { diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 9af2cb54..23b05f76 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -43,6 +43,8 @@ case class MyCoreParams( val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check val useBPWatch: Boolean = false + val mcontextWidth: Int = 0 + val scontextWidth: Int = 0 val nPerfCounters: Int = 29 val haveBasicCounters: Boolean = true val haveFSDirty: Boolean = false diff --git a/tools/barstools b/tools/barstools index 8e5757b5..845af06b 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 8e5757b5ceb8a2c0246e3368baa5bc347dd6f99b +Subproject commit 845af06b1515c69b1d788726134e92b808bf45e4 diff --git a/tools/chisel-testers b/tools/chisel-testers index c5b99a45..5b9cc56d 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit c5b99a452f84af3f581d34e9c51c6c65b6c2a63c +Subproject commit 5b9cc56dd80c8d3bce67d54385d769037e2481d8 diff --git a/tools/dsptools b/tools/dsptools index ce6d87b2..74612fd7 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit ce6d87b2f23bf87085e4913e8324513147f43488 +Subproject commit 74612fd76645bfcfcc1c711ed43025cb8105e539 From 11ab0d73461f7322ce906f9beb0133a01fa4116c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 10:48:44 -0800 Subject: [PATCH 363/457] Put libdeps back into commonSettings in build.sbt --- build.sbt | 56 ++++++++++++++++++------------------------------------- 1 file changed, 18 insertions(+), 38 deletions(-) diff --git a/build.sbt b/build.sbt index 77a0962a..e58e7d60 100644 --- a/build.sbt +++ b/build.sbt @@ -18,7 +18,13 @@ lazy val commonSettings = Seq( libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, + libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1", + libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", + libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", + libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", + libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.10", + libraryDependencies += "junit" % "junit" % "4.13", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -75,27 +81,16 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -// This needs to stay in sync with the chisel3 and firrtl git submodules lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - )) + .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - "com.github.scopt" %% "scopt" % "3.7.1", - "org.json4s" %% "json4s-native" % "3.6.10" - )) + .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(firrtl_interpreter, treadle, chisel) + .dependsOn(chisel, firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -121,7 +116,7 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(hardfloat, rocketMacros, rocketConfig, chisel) + .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) .settings( // Settings for scalafix semanticdbEnabled := true, @@ -177,11 +172,7 @@ lazy val sha3 = (project in file("generators/sha3")) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scalanlp" %% "breeze" % "0.13.2" - )) + .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) @@ -193,37 +184,26 @@ lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeo .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "com.typesafe.play" %% "play-json" % "2.6.10" - )) + .settings(commonSettings) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .dependsOn(firrtl_interpreter, mdf, rocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) -val dsptoolsDependencies = Seq( - "org.scalanlp" %% "breeze" % "1.0", - "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" -) - lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) .settings( commonSettings, - libraryDependencies ++= dsptoolsDependencies - ) + libraryDependencies ++= Seq( + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" + )) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) - .settings( - commonSettings, - libraryDependencies ++= dsptoolsDependencies - ) + .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) From 2b4fb555af8dc06c8f6fe19c32d1002afebc0f09 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 12:15:19 -0800 Subject: [PATCH 364/457] Use ProjectRef for FIRRTL and use it for firrtl-interpreter --- build.sbt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index e58e7d60..51172677 100644 --- a/build.sbt +++ b/build.sbt @@ -81,9 +81,12 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -lazy val chisel = (project in file("tools/chisel3")) +lazy val chisel = (project in file("tools/chisel3")) + +lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) + .dependsOn(firrtl) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) @@ -107,7 +110,8 @@ lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") - .settings(commonSettings).dependsOn(midasTargetUtils) + .dependsOn(midasTargetUtils) + .settings(commonSettings) lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) From 51b254f6b34f4f2535c260d4ba71030992f9f113 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 13:52:38 -0800 Subject: [PATCH 365/457] Small build.sbt cleanup --- build.sbt | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/build.sbt b/build.sbt index 51172677..ba0fea4e 100644 --- a/build.sbt +++ b/build.sbt @@ -1,12 +1,12 @@ import Tests._ -// This gives us a nicer handle to the root project instead of using the +// This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", - version := "1.0", + version := "1.3", scalaVersion := "2.12.10", traceLevel := 15, test in assembly := {}, @@ -14,17 +14,19 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.2" % "test", - libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", - libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", - libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1", - libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", - libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", - libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", - libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", - libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.10", - libraryDependencies += "junit" % "junit" % "4.13", + libraryDependencies ++= Seq( + "org.scalatest" %% "scalatest" % "3.2.2" % "test", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", + "org.json4s" %% "json4s-jackson" % "3.6.10", + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "com.github.scopt" %% "scopt" % "3.7.1", + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + "com.typesafe.play" %% "play-json" % "2.6.10", + "org.typelevel" %% "spire" % "0.16.2", + "org.scalanlp" %% "breeze" % "1.0", + "org.json4s" %% "json4s-native" % "3.6.10", + "junit" % "junit" % "4.13" + ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), From c6e49e0716ba21e34f83447c6f2156d0d3946fa9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 15:05:00 -0800 Subject: [PATCH 366/457] Follow RC's SBT sriracha use | Bump FIRRTL plugin --- build.sbt | 21 ++++++++++++++++----- project/plugins.sbt | 2 +- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/build.sbt b/build.sbt index ba0fea4e..6ac4c85e 100644 --- a/build.sbt +++ b/build.sbt @@ -83,19 +83,27 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin +val chiselVersion = "3.4.0" lazy val chisel = (project in file("tools/chisel3")) +lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +// While not built from source, *must* be in sync with the chisel3 git submodule +// Building from source requires extending sbt-sriracha or a similar plugin and +// keeping scalaVersion in sync with chisel3 to the minor version +lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .dependsOn(firrtl) + .dependsOn(firrtlRef) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(chisel, firrtl_interpreter, treadle) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -122,7 +130,9 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) .settings( // Settings for scalafix semanticdbEnabled := true, @@ -135,7 +145,8 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .dependsOn(chisel) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) diff --git a/project/plugins.sbt b/project/plugins.sbt index b6fe132a..496deb8d 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -19,4 +19,4 @@ addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) -libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" +libraryDependencies += "com.github.os72" % "protoc-jar" % "3.11.4" From 6f827456c8403e2809e0ae1d28ed4342cbb0102b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 16:09:07 -0800 Subject: [PATCH 367/457] Helper make target to launch SBT | Move SBT_OPTS to SBT variable --- common.mk | 8 ++++++++ variables.mk | 9 +++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/common.mk b/common.mk index d0b11fe3..80565a37 100644 --- a/common.mk +++ b/common.mk @@ -218,6 +218,14 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) +####################################### +# Helper to run SBT # +####################################### + +.PHONY: launch-sbt +launch-sbt: + cd $(base_dir) && $(SBT) + ######################################################################################### # print help text ######################################################################################### diff --git a/variables.mk b/variables.mk index 2828366c..42dc48c5 100644 --- a/variables.mk +++ b/variables.mk @@ -151,9 +151,6 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M ######################################################################################### # default sbt launch command ######################################################################################### -SCALA_VERSION=2.12.10 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar # Running with sbt-launch.jar doesn't read .sbtopts by default # # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) sbtopts_file := $(base_dir)/.sbtopts @@ -161,6 +158,10 @@ ifneq (,$(wildcard $(sbtopts_file))) SBT_OPTS ?= $(shell cat $(sbtopts_file)) endif +SCALA_VERSION=2.12.10 +SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) +SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) + BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop # This mirrors the bloop default. Set to a system-unique port in a multi-user environment @@ -182,7 +183,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) $(SBT_OPTS) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif From 3dfc03c31de01ec99f3b36d50c74ed4ba397f0e0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 17:02:59 -0800 Subject: [PATCH 368/457] Add more plugins and libdeps --- build.sbt | 7 +++++-- project/plugins.sbt | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index 6ac4c85e..00605b69 100644 --- a/build.sbt +++ b/build.sbt @@ -25,7 +25,9 @@ lazy val commonSettings = Seq( "org.typelevel" %% "spire" % "0.16.2", "org.scalanlp" %% "breeze" % "1.0", "org.json4s" %% "json4s-native" % "3.6.10", - "junit" % "junit" % "4.13" + "junit" % "junit" % "4.13", + "org.apache.commons" % "commons-text" % "1.8", + "net.jcazevedo" %% "moultingyaml" % "0.4.2" ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, @@ -98,12 +100,13 @@ lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) + .dependsOn(firrtlRef) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle) + .dependsOn(firrtl_interpreter, treadle, firrtlRef) .settings( commonSettings, libraryDependencies ++= Seq( diff --git a/project/plugins.sbt b/project/plugins.sbt index 496deb8d..61e69a3d 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -11,7 +11,7 @@ addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") -addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") +addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") From 9545abb65de6490b8a6e9ee760b21d131916f4cc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 21 Nov 2020 10:40:11 -0800 Subject: [PATCH 369/457] Working elaboration (breaks during barstools FIRRTL) --- build.sbt | 45 ++++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/build.sbt b/build.sbt index 00605b69..968b22cd 100644 --- a/build.sbt +++ b/build.sbt @@ -27,7 +27,8 @@ lazy val commonSettings = Seq( "org.json4s" %% "json4s-native" % "3.6.10", "junit" % "junit" % "4.13", "org.apache.commons" % "commons-text" % "1.8", - "net.jcazevedo" %% "moultingyaml" % "0.4.2" + "net.jcazevedo" %% "moultingyaml" % "0.4.2", + "org.antlr" % "antlr4-runtime" % "4.7.1" ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, @@ -47,19 +48,6 @@ lazy val firesimDir = if (firesimAsLibrary) { file("../../sim") } -// Checks for -DROCKET_USE_MAVEN. -// If it's there, use a maven dependency. -// Else, depend on subprojects in git submodules. -def conditionalDependsOn(prj: Project): Project = { - if (sys.props.contains("ROCKET_USE_MAVEN")) { - prj.settings(Seq( - libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT", - )) - } else { - prj.dependsOn(testchipip) - } -} - /** * It has been a struggle for us to override settings in subprojects. * An example would be adding a dependency to rocketchip on midas's targetutils library, @@ -93,20 +81,21 @@ lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlRef = ProjectRef(file("tools/firrtl"), "firrtl") +lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % "1.4-SNAPSHOT" lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .dependsOn(firrtlRef) + .sourceDependency(firrtlRef, firrtlLib) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) - .dependsOn(firrtlRef) + .sourceDependency(firrtlRef, firrtlLib) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle, firrtlRef) + .dependsOn(firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -146,24 +135,28 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) +lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT" lazy val iocell = (project in file("./tools/barstools/iocell/")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) -lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) +lazy val chipyard = (project in file("generators/chipyard")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(commonSettings) -lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) +lazy val tracegen = (project in file("generators/tracegen")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip, sifive_cache, boom, utilities) .settings(commonSettings) -lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) +lazy val utilities = (project in file("generators/utilities")) + .sourceDependency(testchipip, testchipipLib) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) @@ -174,7 +167,8 @@ lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val boom = conditionalDependsOn(project in file("generators/boom")) +lazy val boom = (project in file("generators/boom")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) .settings(commonSettings) @@ -198,8 +192,8 @@ lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, chipyard) +lazy val tapeout = (project in file("./tools/barstools/tapeout/")) + .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources .settings(commonSettings) .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) @@ -238,7 +232,8 @@ lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") -lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) +lazy val firechip = (project in file("generators/firechip")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, From 94c85c70bbe173077d1665190ccf1e3863bfeb4e Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 16 Nov 2020 10:37:23 -0800 Subject: [PATCH 370/457] bump IceNet for input/output tap and checksum fixes --- generators/icenet | 2 +- software/firemarshal | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/icenet b/generators/icenet index 277a9080..c14e5a02 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 +Subproject commit c14e5a02a7e4fee4d59b6cb0c1087976aba3fe14 diff --git a/software/firemarshal b/software/firemarshal index 45aebace..199f23ed 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 45aebace86d3a46c357337a19d4c8e894a5d0ed4 +Subproject commit 199f23ed74f723313b3bf225a9b4cfed8b6f6399 From 661a7701a70d5d776a85b7f7621df23afeeec8f2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 23 Nov 2020 15:46:03 -0800 Subject: [PATCH 371/457] Share DigitalTop/ChipyardSystem | Fix small naming compile error --- fpga/src/main/scala/arty/Configs.scala | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 9 +- fpga/src/main/scala/vcu118/DigitalTop.scala | 106 ------------------ .../main/scala/vcu118/HarnessBinders.scala | 2 +- fpga/src/main/scala/vcu118/IOBinders.scala | 1 + fpga/src/main/scala/vcu118/TestHarness.scala | 4 +- .../scala/vcu118/bringup/DigitalTop.scala | 6 +- .../chipyard/src/main/scala/DigitalTop.scala | 2 + .../chipyard/src/main/scala/System.scala | 48 +++++++- 9 files changed, 63 insertions(+), 117 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/DigitalTop.scala diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 61a6234c..2a78a54c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -31,7 +31,7 @@ class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithArtyResetHarnessBinder ++ - new WithResetPassthrough ++ + new WithDebugResetPassthrough ++ new WithDefaultPeripherals ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 3c52f249..44913ba2 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,7 +17,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem} +import chipyard.{BuildSystem, ExtTLMem} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) @@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) @@ -41,6 +40,11 @@ class WithSystemModifications extends Config((site, here, up) => { case SerialTLKey => None // remove serialized tl port }) +class WithTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None // disable AXI backing memory + case ExtTLMem => up(ExtMem, site) // enable TL backing memory +}) + // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( new WithUART ++ @@ -50,6 +54,7 @@ class WithVCU118Tweaks extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ + new WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala deleted file mode 100644 index d5c747fa..00000000 --- a/fpga/src/main/scala/vcu118/DigitalTop.scala +++ /dev/null @@ -1,106 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.{DontTouch} - -import chipyard.{DigitalTop, DigitalTopModule, ChipyardSubsystem, ChipyardSubsystemModuleImp} - -// ------------------------------------ -// VCU118 DigitalTop -// ------------------------------------ - -class VCU118DigitalTop(implicit p: Parameters) extends VCU118ChipyardSystem - with testchipip.CanHaveTraceIO // Enables optionally adding trace IO - with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad - with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter - with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART - with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs - with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller - with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port - with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim - with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget - with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget - with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget - with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA -{ - override lazy val module = new VCU118DigitalTopModule(this) -} - -class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends VCU118ChipyardSystemModule(l) - with testchipip.CanHaveTraceIOModuleImp - with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp - with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with chipyard.example.CanHavePeripheryGCDModuleImp - with freechips.rocketchip.util.DontTouch - -// ------------------------------------ -// VCU118 Chipyard System -// ------------------------------------ - -class VCU118ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem - with HasAsyncExtInterrupts - with CanHaveMasterTLMemPort // expose a TL port for outer memory (replaces AXI outer port) - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port -{ - - val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } - val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - override lazy val module = new VCU118ChipyardSystemModule(this) -} - -class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) - with HasRTCModuleImp - with HasExtInterruptsModuleImp - with DontTouch - -// ------------------------------------ -// VCU118 Mem Port Mixin -// ------------------------------------ - -/** Adds a port to the system intended to master an TL DRAM controller. */ -trait CanHaveMasterTLMemPort { this: BaseSubsystem => - private val memPortParamsOpt = p(ExtMem) - private val portName = "tl_mem" - private val device = new MemoryDevice - private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) - - val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => - Seq.tabulate(nMemoryChannels) { channel => - val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - - TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = base.flatMap(_.intersect(filter)), - resources = device.reg, - regionType = RegionType.UNCACHED, // cacheable - executable = true, - supportsGet = TransferSizes(1, mbus.blockBytes), - supportsPutFull = TransferSizes(1, mbus.blockBytes), - supportsPutPartial = TransferSizes(1, mbus.blockBytes))), - beatBytes = memPortParams.beatBytes) - } - }).toList.flatten) - - mbus.coupleTo(s"memory_controller_port_named_$portName") { - (memTLNode - :*= TLBuffer() - :*= TLSourceShrinker(1 << idBits) - :*= TLWidthWidget(mbus.beatBytes) - :*= _) - } - - val mem_tl = InModuleBody { memTLNode.makeIOs() } -} diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index 6ba53642..d60af21a 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{HasHarnessSignalReferences} +import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} import chipyard.harness.{OverrideHarnessBinder} /*** UART ***/ diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala index 4c5bb357..a1f67bcd 100644 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} +import chipyard.{CanHaveMasterTLMemPort} import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index cd88ff8e..5002817f 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -17,7 +17,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -79,7 +79,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** DDR ***/ - val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr + val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr // connect 1 mem. channel to the FPGA DDR val inParams = topDesign match { case td: ChipTop => diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index 251ea8e9..5b554f5b 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -9,18 +9,18 @@ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ -import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} +import chipyard.{DigitalTop, DigitalTopModule} // ------------------------------------ // Bringup VCU118 DigitalTop // ------------------------------------ -class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop +class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } -class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) +class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c0ac1ff7..7fd682d2 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -35,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index bd20ddc7..4ab0da3e 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -7,7 +7,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ @@ -23,7 +23,8 @@ import freechips.rocketchip.util.{DontTouch} */ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts - with CanHaveMasterAXI4MemPort + with CanHaveMasterTLMemPort // export TL port for outer memory + with CanHaveMasterAXI4MemPort // expose AXI port for outer mem with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port { @@ -40,3 +41,46 @@ class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubs with HasRTCModuleImp with HasExtInterruptsModuleImp with DontTouch + +// ------------------------------------ +// TL Mem Port Mixin +// ------------------------------------ + +// Similar to ExtMem but instantiates a TL mem port +case object ExtTLMem extends Field[Option[MemoryPortParams]](None) + +/** Adds a port to the system intended to master an TL DRAM controller. */ +trait CanHaveMasterTLMemPort { this: BaseSubsystem => + private val memPortParamsOpt = p(ExtTLMem) + private val portName = "tl_mem" + private val device = new MemoryDevice + private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsGet = TransferSizes(1, mbus.blockBytes), + supportsPutFull = TransferSizes(1, mbus.blockBytes), + supportsPutPartial = TransferSizes(1, mbus.blockBytes))), + beatBytes = memPortParams.beatBytes) + } + }).toList.flatten) + + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) + } + + val mem_tl = InModuleBody { memTLNode.makeIOs() } +} From 8f6de22e72c52de67fbaa5f317173f884ea6cd95 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 23 Nov 2020 16:30:39 -0800 Subject: [PATCH 372/457] Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs --- fpga/src/main/scala/arty/Configs.scala | 5 +---- fpga/src/main/scala/vcu118/Configs.scala | 4 ++-- generators/chipyard/src/main/scala/ConfigFragments.scala | 4 ++++ .../chipyard/src/main/scala/config/RocketConfigs.scala | 8 +++++++- 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 2a78a54c..fa9a47e0 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -33,10 +33,7 @@ class WithArtyTweaks extends Config( new WithArtyResetHarnessBinder ++ new WithDebugResetPassthrough ++ new WithDefaultPeripherals ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory - new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology) + new freechips.rocketchip.subsystem.WithNBreakpoints(2)) class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 44913ba2..5bd21245 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { - case DebugModuleKey => None // disable debug module case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => @@ -55,7 +54,8 @@ class WithVCU118Tweaks extends Config( new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ new WithTLBackingMemory ++ // use TL backing memory - new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top + new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size + new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 68c41724..4bc0b9a2 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -177,6 +177,10 @@ class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None }) +class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => { + case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) +}) + class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 626700a5..40511eef 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -11,7 +11,13 @@ class RocketConfig extends Config( new chipyard.config.AbstractConfig) class TinyRocketConfig extends Config( - new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core + new chipyard.config.WithTLSerialLocation( + freechips.rocketchip.subsystem.FBUS, + freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology + new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory + new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core new chipyard.config.AbstractConfig) class HwachaRocketConfig extends Config( From f1fdab5bd337cc72563100296d54648393049882 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 23 Nov 2020 16:58:34 -0800 Subject: [PATCH 373/457] Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem --- fpga/src/main/scala/vcu118/Configs.scala | 7 +------ generators/chipyard/src/main/scala/ConfigFragments.scala | 5 +++++ generators/chipyard/src/main/scala/System.scala | 4 ++++ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 5bd21245..8b17aa98 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -39,11 +39,6 @@ class WithSystemModifications extends Config((site, here, up) => { case SerialTLKey => None // remove serialized tl port }) -class WithTLBackingMemory extends Config((site, here, up) => { - case ExtMem => None // disable AXI backing memory - case ExtTLMem => up(ExtMem, site) // enable TL backing memory -}) - // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( new WithUART ++ @@ -53,7 +48,7 @@ class WithVCU118Tweaks extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithTLBackingMemory ++ // use TL backing memory + new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 4bc0b9a2..749c75bb 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -181,6 +181,11 @@ class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusW case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) }) +class WithTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None // disable AXI backing memory + case ExtTLMem => up(ExtMem, site) // enable TL backing memory +}) + class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 4ab0da3e..31bedae7 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -51,6 +51,10 @@ case object ExtTLMem extends Field[Option[MemoryPortParams]](None) /** Adds a port to the system intended to master an TL DRAM controller. */ trait CanHaveMasterTLMemPort { this: BaseSubsystem => + + require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty), + "Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.") + private val memPortParamsOpt = p(ExtTLMem) private val portName = "tl_mem" private val device = new MemoryDevice From 71a3ea8abcacd9907b3a1bcc4e2588b6905526fa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 24 Nov 2020 16:44:20 -0800 Subject: [PATCH 374/457] Allow custom verilator optimization flags --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 65e64179..2b250ee9 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -84,7 +84,7 @@ TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) #---------------------------------------------------------------------------------------- # we initially had --noassert for performance, but several modules use # assertions, including dramsim, so we enable --assert by default -VERILATOR_OPT_FLAGS := \ +VERILATOR_OPT_FLAGS ?= \ -O3 \ --x-assign fast \ --x-initial fast \ From c223f18f73f932f26ccba5782a470a09ad94032e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 25 Nov 2020 20:57:17 -0800 Subject: [PATCH 375/457] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 845af06b..9be550e2 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 845af06b1515c69b1d788726134e92b808bf45e4 +Subproject commit 9be550e23d2f6a2968f35719ba55edb8aefaf138 From 8a46d4a1ea7032bf0442d743b77d8e553419c1b7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 27 Nov 2020 17:34:48 -0800 Subject: [PATCH 376/457] Bump BOOM and Barstools --- generators/boom | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 2dfec3d0..f3a30168 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2dfec3d012e61ff07108af6034a86e60979deecd +Subproject commit f3a301689e8ceee54f247a6c0913d28454bd376a diff --git a/tools/barstools b/tools/barstools index 9be550e2..fa699af0 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 9be550e23d2f6a2968f35719ba55edb8aefaf138 +Subproject commit fa699af02635681c8af90f2169a6705fe5e3e37a From 60e834c812b40c2317715f0a4cd6135436c2b448 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 28 Nov 2020 16:01:35 -0800 Subject: [PATCH 377/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index f89d746a..5e64d783 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f89d746aa3c0c35c78a883c22c58679aeb9e2030 +Subproject commit 5e64d78300a2e5316878af862447c84cee9f6c12 From b7ed614b1968de05c49f3c258867211cfe20b3a6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 30 Nov 2020 21:22:55 -0800 Subject: [PATCH 378/457] Attempt at "fixing" build.sbt | Bump sub-projects --- build.sbt | 202 +++++++++++++++++++++++++++++------------- generators/boom | 2 +- generators/cva6 | 2 +- generators/gemmini | 2 +- generators/sha3 | 2 +- generators/testchipip | 2 +- project/plugins.sbt | 6 -- sims/firesim | 2 +- tools/barstools | 2 +- tools/dsptools | 2 +- 10 files changed, 147 insertions(+), 77 deletions(-) diff --git a/build.sbt b/build.sbt index 968b22cd..01655abc 100644 --- a/build.sbt +++ b/build.sbt @@ -14,25 +14,22 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies ++= Seq( - "org.scalatest" %% "scalatest" % "3.2.2" % "test", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", - "org.json4s" %% "json4s-jackson" % "3.6.10", - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "com.github.scopt" %% "scopt" % "3.7.1", - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - "com.typesafe.play" %% "play-json" % "2.6.10", - "org.typelevel" %% "spire" % "0.16.2", - "org.scalanlp" %% "breeze" % "1.0", - "org.json4s" %% "json4s-native" % "3.6.10", - "junit" % "junit" % "4.13", - "org.apache.commons" % "commons-text" % "1.8", - "net.jcazevedo" %% "moultingyaml" % "0.4.2", - "org.antlr" % "antlr4-runtime" % "4.7.1" - ), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), // TODO: Needed for just Rocket? unmanagedBase := (chipyardRoot / unmanagedBase).value, - allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), + allDependencies := { + // drop dependencies (org, name) + val dropDeps = Seq( + ("edu.berkeley.cs", "firrtl"), + ("edu.berkeley.cs", "chisel3"), + ("edu.berkeley.cs", "rocketchip"), + ("edu.berkeley.cs", "chisel-iotesters"), + ("edu.berkeley.cs", "treadle"), + ("edu.berkeley.cs", "firrtl-interpreter")) + + allDependencies.value.filterNot { dep => + dropDeps.contains((dep.organization, dep.name)) + } + }, exportJars := true, resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), @@ -73,86 +70,135 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin +// -- Rocket Chip -- + val chiselVersion = "3.4.0" -lazy val chisel = (project in file("tools/chisel3")) +lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // While not built from source, *must* be in sync with the chisel3 git submodule // Building from source requires extending sbt-sriracha or a similar plugin and // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtlRef = ProjectRef(file("tools/firrtl"), "firrtl") -lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % "1.4-SNAPSHOT" - -lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .sourceDependency(firrtlRef, firrtlLib) - .settings(commonSettings) - -lazy val treadle = (project in file("tools/treadle")) - .sourceDependency(firrtlRef, firrtlLib) - .settings(commonSettings) - -lazy val chisel_testers = (project in file("tools/chisel-testers")) - .sourceDependency(chisel, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.13", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1", - "org.scalacheck" %% "scalacheck" % "1.14.3", - "com.github.scopt" %% "scopt" % "3.7.1" - )) - -// Contains annotations & firrtl passes you may wish to use in rocket-chip without -// introducing a circular dependency between RC and MIDAS -lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") +val firrtlVersion = "1.4-SNAPSHOT" +lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion +//lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin +lazy val firrtlLibDeps = Seq( + "org.scalatest" %% "scalatest" % "3.2.0" % "test", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test", + "com.github.scopt" %% "scopt" % "3.7.1", + "net.jcazevedo" %% "moultingyaml" % "0.4.2", + "org.json4s" %% "json4s-native" % "3.6.9", + "org.apache.commons" % "commons-text" % "1.8", + "org.antlr" % "antlr4-runtime" % "4.7.1" +) // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .dependsOn(midasTargetUtils) .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt") .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .sourceDependency(chisel, chiselLib) + .sourceDependency(chiselRef, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .dependsOn(hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) .settings( // Settings for scalafix semanticdbEnabled := true, semanticdbVersion := scalafixSemanticdb.revision, scalacOptions += "-Ywarn-unused-import" ) +lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) + +// -- "Problematic" Projects -- + +lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) + .sourceDependency(firrtlRef, firrtlLib) + .settings(libraryDependencies ++= firrtlLibDeps) + .settings(commonSettings) +lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies) + +lazy val treadle = (project in file("tools/treadle")) + .sourceDependency(firrtlRef, firrtlLib) + .settings(libraryDependencies ++= firrtlLibDeps) + .settings(commonSettings) +lazy val treadleLibDeps = (treadle / Keys.libraryDependencies) + +lazy val chisel_testers = (project in file("tools/chisel-testers")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) + .dependsOn(firrtl_interpreter, treadle) + .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value) + .settings(libraryDependencies ++= treadleLibDeps.value) + .settings(commonSettings) +lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies) + +// -- UCB-controlled Projects -- + +// Contains annotations & firrtl passes you may wish to use in rocket-chip without +// introducing a circular dependency between RC and MIDAS +lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT" -lazy val iocell = (project in file("./tools/barstools/iocell/")) - .sourceDependency(chisel, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) - .settings(commonSettings) - lazy val chipyard = (project in file("generators/chipyard")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val tracegen = (project in file("generators/tracegen")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip, sifive_cache, boom, utilities) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val utilities = (project in file("generators/utilities")) @@ -160,73 +206,103 @@ lazy val utilities = (project in file("generators/utilities")) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) - .dependsOn(rocketchip, testchipip) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sodor = (project in file("generators/riscv-sodor")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip, chisel_testers, testchipip) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip, chisel_testers) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + +lazy val iocell = (project in file("./tools/barstools/iocell/")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .settings(commonSettings) lazy val tapeout = (project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) - .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) - .dependsOn(firrtl_interpreter, mdf, rocketchip) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) + .dependsOn(firrtl_interpreter, mdf, chisel_testers) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) + .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings( commonSettings, libraryDependencies ++= Seq( + "org.typelevel" %% "spire" % "0.16.2", + "org.scalanlp" %% "breeze" % "1.1", "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" + "org.scalatest" %% "scalatest" % "3.0.+" % "test", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", )) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( +lazy val sifive_cache = (project in file("generators/sifive-cache")) + .settings( commonSettings, - scalaSource in Compile := baseDirectory.value / "design/craft" - ).dependsOn(rocketchip) + scalaSource in Compile := baseDirectory.value / "design/craft") + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) // Library components of FireSim lazy val midas = ProjectRef(firesimDir, "midas") diff --git a/generators/boom b/generators/boom index f3a30168..6198e335 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f3a301689e8ceee54f247a6c0913d28454bd376a +Subproject commit 6198e33545f2ec2c70a6ac9afba78c7023e9605b diff --git a/generators/cva6 b/generators/cva6 index c2b9fc41..d40a8f5c 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit c2b9fc412179a386fb4b662d13e588a9613f41d5 +Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6 diff --git a/generators/gemmini b/generators/gemmini index 371bc330..eb719930 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 371bc33038e633779f52e26eaa0031f2820c2f0d +Subproject commit eb7199307d3adf994c78b02a54859f3e37ac7012 diff --git a/generators/sha3 b/generators/sha3 index a4ea9602..74e41f57 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit a4ea960248fdf8267b515723d472b018b09ac24f +Subproject commit 74e41f579213549501ccf292d101f9db73ee2347 diff --git a/generators/testchipip b/generators/testchipip index 03af7aa5..6fbb1b77 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 03af7aa53988dd96dffd613d1d50a5c6661e0a82 +Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b diff --git a/project/plugins.sbt b/project/plugins.sbt index 61e69a3d..fa2a1a57 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,7 +1,3 @@ -resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) -resolvers += Classpaths.sbtPluginReleases -resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" - addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") @@ -18,5 +14,3 @@ addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) - -libraryDependencies += "com.github.os72" % "protoc-jar" % "3.11.4" diff --git a/sims/firesim b/sims/firesim index 5e64d783..4752009e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 5e64d78300a2e5316878af862447c84cee9f6c12 +Subproject commit 4752009e98fdd0b1848c6a3cde21fee331885939 diff --git a/tools/barstools b/tools/barstools index fa699af0..3a29f535 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit fa699af02635681c8af90f2169a6705fe5e3e37a +Subproject commit 3a29f535726a191d09164470eb1ce1a1ddd5bf9a diff --git a/tools/dsptools b/tools/dsptools index 74612fd7..27304bde 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 74612fd76645bfcfcc1c711ed43025cb8105e539 +Subproject commit 27304bdeae3e4fb969c7cac1e0bda358be7cdb12 From 477be36cef46c5b7b8075885e42d71b8d62b3274 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 30 Nov 2020 22:41:55 -0800 Subject: [PATCH 379/457] Apply suggestions from code review Co-authored-by: Colin Schmidt --- docs/VLSI/Basic-Flow.rst | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index c616ff56..d5bb82e2 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -39,16 +39,16 @@ Next, we define the Hammer environment into the shell: Setting up the Hammer Configuration Files -------------------------------------------- -The first configuration file that needs to be set up is the Hammer environment configuration file ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you need to fill the paths only for the tools that you will be using. +The first configuration file that needs to be set up is the Hammer environment configuration file ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you only need to fill in the paths for the tools that you will be using. If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`Advanced Environment Setup` segment of this documentation page. Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``nangate45`` -OpenRoad example), the generally applicable way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design. +OpenRoad example), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design. The ``vlsi`` directory includes three such example configuration files matching the three concerns: ``example-tools.yml``, ``example-tech.yml``, and ``example-design.yml``. -The ``example-tools.yml`` file configures which EDA tools hammer will use. This example files uses Cadence Innovus, Genus and Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). Note that tool versions are highly sensitive to the process-technology in-use. Hence, tool versions that work with one process technology may not work with another (for example, ASAP7 will not work with an Innovus version newer than 18.1, while other proprietary process technologies will likely require newer versions such as 19.1). +The ``example-tools.yml`` file configures which EDA tools hammer will use. This example files uses Cadence Innovus, Genus and Mentor Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). Note that tool versions are highly sensitive to the process-technology in-use. Hence, tool versions that work with one process technology may not work with another (for example, ASAP7 will not work with an Innovus version newer than 18.1, while other proprietary process technologies will likely require newer versions such as 19.1). -The ``example-design.yml`` file contrain basic build system information (how many cores/threads to use, etc.), as well as configuration that are specific to the design we are working on such as clock signal name and frequency, power modes, floorplan, and additional contraints that we will add later on. +The ``example-design.yml`` file contains basic build system information (how many cores/threads to use, etc.), as well as configurations that are specific to the design we are working on such as clock signal name and frequency, power modes, floorplan, and additional constraints that we will add later on. Finally, the ``example-tech`` file is a template file for a process technology plugin configuration. We will copy this file, and replace its fields with the appropriate process technology details for the tech plugin that we have access to. For example, for the ``asap7`` tech plugin we will replace the field with "asap7", the Node size "N" with "7", and the path to the process technology files installation directory. @@ -68,7 +68,7 @@ By default, the MacroCopmiler will attempt to map memories into the SRAM options We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. -Hence, if we want to monolitically place and route the entire SoC, the relevant command would be +Hence, if we want to monolithically place and route the entire SoC, the relevant command would be .. code-block:: shell make buildfile CONFIG= tech_name= INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" @@ -81,7 +81,7 @@ In a more typical scenario of working on a single module, for example the Gemmin Running the VLSI Flow --------------------- -Running a basic VLSI flow using the Hammer default configurations is fairly simple, and consists of simpele ``Make`` command with the previously mentioned Make variables. +Running a basic VLSI flow using the Hammer default configurations is fairly simple, and consists of simple ``make`` command with the previously mentioned Make variables. Synthesis ^^^^^^^^^ @@ -89,7 +89,7 @@ Synthesis In order to run synthesis, we run ``make syn`` with the matching Make variables. Post-synthesis logs and collateral will be saved in ``build//syn-rundir``. The raw QoR data (area, timing, gate counts, etc.) will be found in ``build//syn-rundir/reports``. -Hence, if we want to monolitically synthesize the entire SoC, the relevant command would be +Hence, if we want to monolithically synthesize the entire SoC, the relevant command would be .. code-block:: shell make syn CONFIG= tech_name= INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" @@ -136,7 +136,7 @@ The relevant ``make`` command would then be Place-and-route generally requires more fine-grained input specifications regarding power nets, clock nets, pin assignments and floorplanning. While the template configuration files provide defaults for automatic tool defaults, these will usually result in very bad QoR, and therefore it is recommended to specify better-informed floorplans, pin assignments and power nets. For more information about cutomizing theses parameters, please refer to the :ref:`Customizing Your VLSI Flow in Hammer` sections or to the Hammer documentation. -Additionally, some Hammer process technology plugins do not provide sufficient default values for requires settings such as power nets and pin assignments (for example, ASAP7). In those cases, these contraint will need to be specified manually in the top-level configuration yml files, as is the case in the ``example-asap7.yml`` configuration file. +Additionally, some Hammer process technology plugins do not provide sufficient default values for requires settings such as power nets and pin assignments (for example, ASAP7). In those cases, these constraints will need to be specified manually in the top-level configuration yml files, as is the case in the ``example-asap7.yml`` configuration file. Place-and-route tools are very sensitive to process technologes (significantly more sensitive than synthesis tools), and different process technologies may work only on specific tool versions. It is recommended to check what is the appropriate tool version for the specific process technology you are working with. @@ -167,7 +167,7 @@ In order to run DRC, the relevant ``make`` command is ``make drc``. As in the pr make drc CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" -DRC does not emit autmated reports, but rather scripts that enable opening the DRC error database within the appropriate tool. These generated scripts can be called from ``./build//drc-rundir/generated-scripts/view_drc``. +DRC does not emit easily audited reports, as the rule names violated can be quite esoteric. It is often more productive to rather use the scripts generated by Hammer to open the DRC error database within the appropriate tool. These generated scripts can be called from ``./build//drc-rundir/generated-scripts/view_drc``. In order to run LVS, the relevant ``make`` command is ``make lvs``. As in the previous stages, the make command should be accompanied by the relevant configuration Make variables: @@ -176,7 +176,7 @@ In order to run LVS, the relevant ``make`` command is ``make lvs``. As in the pr make lvs CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" -LVS does not emit autmated reports, but rather scripts that enable opening the LVS error database within the appropriate tool. These generated scripts can be called from ``./build//lvs-rundir/generated-scripts/view_lvs``. +LVS does not emit easily audited reports, as the violations are often cryptic when seen textually. As a result it is often more productive to visually see the LVS issues using the generated scripts that enable opening the LVS error database within the appropriate tool. These generated scripts can be called from ``./build//lvs-rundir/generated-scripts/view_lvs``. Customizing Your VLSI Flow in Hammer From 5bc7e6cd685428d50a8bd28ee1e97dfda730577c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 1 Dec 2020 22:28:23 -0800 Subject: [PATCH 380/457] Support SBT thin client | Rename JAVA_ARGS -> OPTS | Support env. SBT_OPTS --- .gitignore | 1 + .sbtopts | 2 -- build.sbt | 2 +- common.mk | 14 +++++++++----- project/build.properties | 2 +- variables.mk | 21 +++++++++++---------- 6 files changed, 23 insertions(+), 19 deletions(-) delete mode 100644 .sbtopts diff --git a/.gitignore b/.gitignore index a85d0dd2..153e7275 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,4 @@ tags env-riscv-tools.sh env-esp-tools.sh .bloop/ +.bsp/ diff --git a/.sbtopts b/.sbtopts deleted file mode 100644 index 2358d787..00000000 --- a/.sbtopts +++ /dev/null @@ -1,2 +0,0 @@ --Dsbt.sourcemode=true --Dsbt.workspace=$PWD/tools diff --git a/build.sbt b/build.sbt index 01655abc..1132dde1 100644 --- a/build.sbt +++ b/build.sbt @@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -val firrtlVersion = "1.4-SNAPSHOT" +val firrtlVersion = "1.4.+" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion //lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin diff --git a/common.mk b/common.mk index 80565a37..4f632a26 100644 --- a/common.mk +++ b/common.mk @@ -63,7 +63,7 @@ SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) -SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt +SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### # Bloop Project Definitions @@ -209,7 +209,7 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) endif ####################################### -# Rules for building DRAMSim2 library # +# Rules for building DRAMSim2 library ####################################### dramsim_dir = $(base_dir)/tools/DRAMSim2 @@ -218,14 +218,18 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) -####################################### -# Helper to run SBT # -####################################### +################################################ +# Helper to run SBT or shutdown the SBT server +################################################ .PHONY: launch-sbt launch-sbt: cd $(base_dir) && $(SBT) +.PHONY: launch-sbt +shutdown-sbt: + cd $(base_dir) && $(SBT) shutdown + ######################################################################################### # print help text ######################################################################################### diff --git a/project/build.properties b/project/build.properties index 0837f7a1..7de0a938 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.3.13 +sbt.version=1.4.4 diff --git a/variables.mk b/variables.mk index 42dc48c5..73918376 100644 --- a/variables.mk +++ b/variables.mk @@ -146,21 +146,22 @@ sim_common_files ?= $(build_dir)/sim_files.common.f # java arguments used in sbt ######################################################################################### JAVA_HEAP_SIZE ?= 8G -JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M +JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M ######################################################################################### # default sbt launch command ######################################################################################### -# Running with sbt-launch.jar doesn't read .sbtopts by default -# # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) -sbtopts_file := $(base_dir)/.sbtopts -ifneq (,$(wildcard $(sbtopts_file))) - SBT_OPTS ?= $(shell cat $(sbtopts_file)) +# by default build chisel3/firrtl and other subprojects from source +override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools + +ifdef ENABLE_SBT_THIN_CLIENT +# enabling speeds up sbt loading +# however if build.sbt changes are done you need to +# "shutdown" the server (shutdown-sbt target) to reload build.sbt changes +SBT_CLIENT_FLAG = --client endif -SCALA_VERSION=2.12.10 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) +SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop @@ -183,7 +184,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef endif From 4e53dc1e663560131f5b12fb0dcd7079a0dd0bdc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 12:18:12 -0800 Subject: [PATCH 381/457] Cleanly reload proj. defs. with thin client support --- .gitignore | 1 + common.mk | 18 +++++++++++++++--- variables.mk | 7 +++++-- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 153e7275..77b9eb6c 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,4 @@ env-riscv-tools.sh env-esp-tools.sh .bloop/ .bsp/ +*_TIMESTAMP diff --git a/common.mk b/common.mk index 4f632a26..f149d1ae 100644 --- a/common.mk +++ b/common.mk @@ -69,9 +69,20 @@ SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $ # Bloop Project Definitions ######################################################################################### $(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) - cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall" + cd $(base_dir) && $(SBT) ";project chipyardRoot; bloopInstall" touch $@ +######################################################################################### +# SBT Server Setup (needed to rebuild project correctly) +######################################################################################### +$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) +ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) + cd $(base_dir) && $(SBT) "reload" + touch $@ +else + touch $@ +endif + ######################################################################################### # create list of simulation file inputs ######################################################################################### @@ -226,9 +237,10 @@ $(dramsim_lib): launch-sbt: cd $(base_dir) && $(SBT) -.PHONY: launch-sbt +.PHONY: shutdown-sbt shutdown-sbt: - cd $(base_dir) && $(SBT) shutdown + cd $(base_dir) && $(SBT) "shutdown" + rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) ######################################################################################### # print help text diff --git a/variables.mk b/variables.mk index 73918376..731b7e1e 100644 --- a/variables.mk +++ b/variables.mk @@ -154,7 +154,12 @@ JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M # by default build chisel3/firrtl and other subprojects from source override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools +SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) + +SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP + ifdef ENABLE_SBT_THIN_CLIENT +override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) # enabling speeds up sbt loading # however if build.sbt changes are done you need to # "shutdown" the server (shutdown-sbt target) to reload build.sbt changes @@ -168,8 +173,6 @@ BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop # This mirrors the bloop default. Set to a system-unique port in a multi-user environment BLOOP_NAILGUN_PORT ?= 8212 -SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) - ifdef ENABLE_BLOOP override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # Two notes about the bloop invocation: From a0e2dcfc4ecddeaa79c3cb8904b6b2de4e397435 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 14:46:46 -0800 Subject: [PATCH 382/457] Remove support for bloop --- .gitignore | 1 - common.mk | 7 ------- project/plugins.sbt | 1 - variables.mk | 19 ------------------- 4 files changed, 28 deletions(-) diff --git a/.gitignore b/.gitignore index 77b9eb6c..a80f88ab 100644 --- a/.gitignore +++ b/.gitignore @@ -19,6 +19,5 @@ tags *~ env-riscv-tools.sh env-esp-tools.sh -.bloop/ .bsp/ *_TIMESTAMP diff --git a/common.mk b/common.mk index f149d1ae..159e7ea6 100644 --- a/common.mk +++ b/common.mk @@ -65,13 +65,6 @@ VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties -######################################################################################### -# Bloop Project Definitions -######################################################################################### -$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) - cd $(base_dir) && $(SBT) ";project chipyardRoot; bloopInstall" - touch $@ - ######################################################################################### # SBT Server Setup (needed to rebuild project correctly) ######################################################################################### diff --git a/project/plugins.sbt b/project/plugins.sbt index fa2a1a57..7e6f3aa8 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -11,6 +11,5 @@ addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) diff --git a/variables.mk b/variables.mk index 731b7e1e..6cc87bfc 100644 --- a/variables.mk +++ b/variables.mk @@ -168,28 +168,9 @@ endif SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) -BLOOP ?= bloop -BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop -# This mirrors the bloop default. Set to a system-unique port in a multi-user environment -BLOOP_NAILGUN_PORT ?= 8212 - -ifdef ENABLE_BLOOP -override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP -# Two notes about the bloop invocation: -# 1) the sed removes a leading {file:} that sometimes needs to be -# provided to SBT when a project but not for bloop. -# 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the -# --nailgun-port argument to be lost in this case. Workaround this by prefixing -# every main-destined argument with "--args" -define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) -endef -else define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef -endif FIRRTL_LOGLEVEL ?= error From 08f3dbc1d07580af3c94bb1f59290a866abb1fc0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 14:51:49 -0800 Subject: [PATCH 383/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4752009e..bf05870d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4752009e98fdd0b1848c6a3cde21fee331885939 +Subproject commit bf05870d225564772c44cf5505a40b1a742aa5f7 From 145885390f4a6cdbe9a5cf76bc35aa92c1458d71 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:08:06 -0800 Subject: [PATCH 384/457] Bump Hwacha --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index e0109674..b67d8ed0 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e0109674572f4b40641a89db9e0429e51b5cb73a +Subproject commit b67d8ed06172c2ecd76807d3ef2bd5c79903f182 From 3bc1bdb841b55b4d97ebba8fc6abd588c7ddab47 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:49:35 -0800 Subject: [PATCH 385/457] Bump BOOM | Split JAVA/SBT options in CI --- .circleci/defaults.sh | 3 ++- .circleci/do-rtl-build.sh | 2 +- .circleci/run-firesim-scala-tests.sh | 2 +- generators/boom | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e9ccdfb5..02558101 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,8 +33,9 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim +REMOTE_JAVA_OPTS="-Xmx9G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 784dbc04..1e065437 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -63,7 +63,7 @@ do export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}" done run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh index 8080a484..a2525297 100755 --- a/.circleci/run-firesim-scala-tests.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -49,4 +49,4 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}" + make -C $REMOTE_FIRESIM_DIR JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" testOnly ${mapping[$1]}" diff --git a/generators/boom b/generators/boom index 6198e335..a53372fc 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 6198e33545f2ec2c70a6ac9afba78c7023e9605b +Subproject commit a53372fcff4c1095a513eb8bb6e8a2b9cdb971a0 From eee0d58b5d6a8b368457873bd0fbc8b8f4b63d72 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:53:11 -0800 Subject: [PATCH 386/457] Cleanup comment --- variables.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/variables.mk b/variables.mk index 6cc87bfc..c8f72b3f 100644 --- a/variables.mk +++ b/variables.mk @@ -161,8 +161,6 @@ SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP ifdef ENABLE_SBT_THIN_CLIENT override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) # enabling speeds up sbt loading -# however if build.sbt changes are done you need to -# "shutdown" the server (shutdown-sbt target) to reload build.sbt changes SBT_CLIENT_FLAG = --client endif From 41c710b6c8c4391381caffdea8509f7dcfdc77ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 16:11:09 -0800 Subject: [PATCH 387/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index bf05870d..10f9e7ef 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit bf05870d225564772c44cf5505a40b1a742aa5f7 +Subproject commit 10f9e7efe0b4f532037575e114b8b5fbfb47d211 From d19bcaa765e4e0cf246fa4065ffbc70bacad0d25 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 16:42:52 -0800 Subject: [PATCH 388/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 10f9e7ef..593596c5 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 10f9e7efe0b4f532037575e114b8b5fbfb47d211 +Subproject commit 593596c5a854f69d28d0c3b9389175a03fa4c696 From 7f9cd0f012e143229fc5022dd4f380b9ba772583 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 21:51:58 -0800 Subject: [PATCH 389/457] Bump FireSim | CI Fix Attempt: Increase heap --- .circleci/defaults.sh | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 02558101..015aaee7 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,7 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim -REMOTE_JAVA_OPTS="-Xmx9G -Xss8M" +REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install diff --git a/sims/firesim b/sims/firesim index 593596c5..f9ca2f49 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 593596c5a854f69d28d0c3b9389175a03fa4c696 +Subproject commit f9ca2f49f95e2b51cf0e966ac13b1f285db341cf From f1df2ec69e1dab0666f8a2fb66849886a25717f1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 12:51:24 -0800 Subject: [PATCH 390/457] Bump FireSim/Hwacha | Cleanup linting --- build.sbt | 3 +++ generators/hwacha | 2 +- sims/firesim | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 1132dde1..b50bc200 100644 --- a/build.sbt +++ b/build.sbt @@ -1,5 +1,8 @@ import Tests._ +// Ignore linting for traceLevel +Global / excludeLintKeys += traceLevel + // This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) diff --git a/generators/hwacha b/generators/hwacha index b67d8ed0..27e03b7e 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit b67d8ed06172c2ecd76807d3ef2bd5c79903f182 +Subproject commit 27e03b7e2694b4389c64c92a3518b1dba5304905 diff --git a/sims/firesim b/sims/firesim index f9ca2f49..515ac120 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f9ca2f49f95e2b51cf0e966ac13b1f285db341cf +Subproject commit 515ac12059a347f34b13833888ace941a9629be5 From d0079a96599f2fa545e37e10ea459ba4e30fb672 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 14:06:55 -0800 Subject: [PATCH 391/457] Cleanup helper sbt targets | Use project/target/active.json for SBT timestamp --- .gitignore | 1 - common.mk | 17 +++++++++++------ sims/firesim | 2 +- variables.mk | 3 ++- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/.gitignore b/.gitignore index a80f88ab..257d2c58 100644 --- a/.gitignore +++ b/.gitignore @@ -20,4 +20,3 @@ tags env-riscv-tools.sh env-esp-tools.sh .bsp/ -*_TIMESTAMP diff --git a/common.mk b/common.mk index 159e7ea6..a474454a 100644 --- a/common.mk +++ b/common.mk @@ -66,14 +66,14 @@ SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### -# SBT Server Setup (needed to rebuild project correctly) +# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change) ######################################################################################### $(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) cd $(base_dir) && $(SBT) "reload" touch $@ else - touch $@ + cd $(base_dir) && $(SBT) "exit" endif ######################################################################################### @@ -223,18 +223,23 @@ $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) ################################################ -# Helper to run SBT or shutdown the SBT server +# Helper to run SBT or manage the SBT server ################################################ +SBT_COMMAND ?= shell .PHONY: launch-sbt launch-sbt: - cd $(base_dir) && $(SBT) + cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)" -.PHONY: shutdown-sbt -shutdown-sbt: +.PHONY: shutdown-sbt-server +shutdown-sbt-server: cd $(base_dir) && $(SBT) "shutdown" rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) +.PHONY: start-sbt-server +start-sbt-server: + cd $(base_dir) && $(SBT) "exit" + ######################################################################################### # print help text ######################################################################################### diff --git a/sims/firesim b/sims/firesim index 515ac120..6dc98f6c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 515ac12059a347f34b13833888ace941a9629be5 +Subproject commit 6dc98f6cff25b348d3e2bf72fa17f2348c816b2f diff --git a/variables.mk b/variables.mk index c8f72b3f..88ba73ee 100644 --- a/variables.mk +++ b/variables.mk @@ -156,7 +156,7 @@ override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) -SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP +SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json ifdef ENABLE_SBT_THIN_CLIENT override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) @@ -165,6 +165,7 @@ SBT_CLIENT_FLAG = --client endif SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) +SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT)) define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" From 70fa0a037dc2857980181592376aeea73223d9db Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 14:57:05 -0800 Subject: [PATCH 392/457] Print full stack traces (default traceLevel = 0) | Bump FireSim --- build.sbt | 4 ---- sims/firesim | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index b50bc200..8856a20c 100644 --- a/build.sbt +++ b/build.sbt @@ -1,8 +1,5 @@ import Tests._ -// Ignore linting for traceLevel -Global / excludeLintKeys += traceLevel - // This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) @@ -11,7 +8,6 @@ lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.3", scalaVersion := "2.12.10", - traceLevel := 15, test in assembly := {}, assemblyMergeStrategy in assembly := { _ match { case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard diff --git a/sims/firesim b/sims/firesim index 6dc98f6c..2addd725 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6dc98f6cff25b348d3e2bf72fa17f2348c816b2f +Subproject commit 2addd72598212424d8a4832b2d78b11c95d74337 From 714687c9622ff920e1b1e0eb542c63592572f2ef Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 4 Dec 2020 14:18:51 -0800 Subject: [PATCH 393/457] Add to help target | Cleanup build.sbt a bit more --- build.sbt | 21 ++++++++------------- common.mk | 7 +++++-- sims/firesim | 2 +- 3 files changed, 14 insertions(+), 16 deletions(-) diff --git a/build.sbt b/build.sbt index 8856a20c..b24fa748 100644 --- a/build.sbt +++ b/build.sbt @@ -13,7 +13,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), // TODO: Needed for just Rocket? + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { // drop dependencies (org, name) @@ -71,6 +71,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // -- Rocket Chip -- +// This needs to stay in sync with the chisel3 and firrtl git submodules val chiselVersion = "3.4.0" lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion @@ -83,16 +84,10 @@ lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion val firrtlVersion = "1.4.+" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion -//lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin -lazy val firrtlLibDeps = Seq( - "org.scalatest" %% "scalatest" % "3.2.0" % "test", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test", - "com.github.scopt" %% "scopt" % "3.7.1", - "net.jcazevedo" %% "moultingyaml" % "0.4.2", - "org.json4s" %% "json4s-native" % "3.6.9", - "org.apache.commons" % "commons-text" % "1.8", - "org.antlr" % "antlr4-runtime" % "4.7.1" -) +val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") +Global / firrtlLibDeps := { + (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4") +} // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") @@ -153,14 +148,14 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .sourceDependency(firrtlRef, firrtlLib) - .settings(libraryDependencies ++= firrtlLibDeps) .settings(commonSettings) + .settings(libraryDependencies ++= (Global / firrtlLibDeps).value) lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies) lazy val treadle = (project in file("tools/treadle")) .sourceDependency(firrtlRef, firrtlLib) - .settings(libraryDependencies ++= firrtlLibDeps) .settings(commonSettings) + .settings(libraryDependencies ++= (Global / firrtlLibDeps).value) lazy val treadleLibDeps = (treadle / Keys.libraryDependencies) lazy val chisel_testers = (project in file("tools/chisel-testers")) diff --git a/common.mk b/common.mk index a474454a..33c0137c 100644 --- a/common.mk +++ b/common.mk @@ -17,7 +17,8 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ " EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ -" EXTRA_SIM_REQS = additional make requirements to build the simulator" +" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ +" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client" EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= @@ -41,7 +42,9 @@ HELP_COMMANDS += \ " run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ " run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ " verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" \ -" run-tests = run all assembly and benchmark tests" +" firrtl = generate intermediate firrtl files from chisel elaboration" \ +" run-tests = run all assembly and benchmark tests" \ +" launch-sbt = start sbt terminal" ######################################################################################### # include additional subproject make fragments diff --git a/sims/firesim b/sims/firesim index 2addd725..7ab7bc4a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2addd72598212424d8a4832b2d78b11c95d74337 +Subproject commit 7ab7bc4a2baaf04f5d8c03094c976e43dc1b2344 From d8fd94d57cd4b9030ade342b6f351810a3f87b5c Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 7 Dec 2020 00:16:05 -0800 Subject: [PATCH 394/457] [skip ci] address some PR comments --- docs/VLSI/Basic-Flow.rst | 22 +++++++++++++++------- vlsi/example-design.yml | 3 +-- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index d5bb82e2..1af4f588 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -34,7 +34,7 @@ Next, we define the Hammer environment into the shell: source $HAMMER_HOME/sourceme.sh -.. Note:: Some VLSI EDA tools are supported only on RHEL-based operating systems. We recommend using Chipyard on RHEL7 and above. However, many VLSI server still have old operating systems such as RHEL6, which have software packages older than the basic chipyard requirements. In order to build Chipyard on RHEL6, you will likely need to build from source gcc, git, gmake, make, dtc, cc, bison, libexpat and liby. +.. Note:: Some VLSI EDA tools are supported only on RHEL-based operating systems. We recommend using Chipyard on RHEL7 and above. However, many VLSI server still have old operating systems such as RHEL6, which have software packages older than the basic chipyard requirements. In order to build Chipyard on RHEL6, you will likely need to use tool packages such as devtoolset (for example, devtoolset-8) and/or build from source gcc, git, gmake, make, dtc, cc, bison, libexpat and liby. Setting up the Hammer Configuration Files -------------------------------------------- @@ -52,7 +52,7 @@ The ``example-design.yml`` file contains basic build system information (how man Finally, the ``example-tech`` file is a template file for a process technology plugin configuration. We will copy this file, and replace its fields with the appropriate process technology details for the tech plugin that we have access to. For example, for the ``asap7`` tech plugin we will replace the field with "asap7", the Node size "N" with "7", and the path to the process technology files installation directory. -We recommend copying these example configuration files and customizing them with a different name, so you can have different configuration files for different process technologies and designs. +We recommend copying these example configuration files and customizing them with a different name, so you can have different configuration files for different process technologies and designs (e.g. create tech-tsmintel3.yml from example-tech.yml) Building the Design @@ -64,7 +64,7 @@ As in the rest of the Chipyard flows, we specify our SoC configuration using the However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module. Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on. The makefile will automatically call tools such as Barstools and the MacroCopmiler (:ref:`barstools`) in order to make the generated Verilog more VLSI friendly. -By default, the MacroCopmiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are wokring with a new process technology are prefer to work with flipflop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, the ASAP7 process technology does not have associated SRAMs, and therefore the ASAP7 Hammer tutorial (:ref:`tutorial`) uses the ``MACROCOMPILER_MODE='--mode synflops'`` option. +By default, the MacroCopmiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are wokring with a new process technology are prefer to work with flipflop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, the ASAP7 process technology does not have associated SRAMs, and therefore the ASAP7 Hammer tutorial (:ref:`tutorial`) uses the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. @@ -134,7 +134,7 @@ The relevant ``make`` command would then be make par CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" - +Note that the width and height specification can vary widely between different modulesi and level of the module hierarchy. Make sure to set sane width and height values. Place-and-route generally requires more fine-grained input specifications regarding power nets, clock nets, pin assignments and floorplanning. While the template configuration files provide defaults for automatic tool defaults, these will usually result in very bad QoR, and therefore it is recommended to specify better-informed floorplans, pin assignments and power nets. For more information about cutomizing theses parameters, please refer to the :ref:`Customizing Your VLSI Flow in Hammer` sections or to the Hammer documentation. Additionally, some Hammer process technology plugins do not provide sufficient default values for requires settings such as power nets and pin assignments (for example, ASAP7). In those cases, these constraints will need to be specified manually in the top-level configuration yml files, as is the case in the ``example-asap7.yml`` configuration file. @@ -147,16 +147,24 @@ Place-and-route tools are very sensitive to process technologes (significantly m Power Estimation ^^^^^^^^^^^^^^^^^^^^ +Power estimation in Hammer can be performed in one of two stages: post-synthesis (post-syn) or post-place-and-route (post-par). The most accurate power estimation is post-par, and it includes finer grained details of the places instances and wire lengths. +Post-par power estimation can be based on static average signal toggles rates (also known as "static power estimation"), or based on simulation-extracted signal toggle data (also known as "dynamic power estimation"). +In order to run post-par power estimation, make sure that a power estimation tool (such as Cadence Voltus) has been defined in your ``example-tools.yml`` file. +Simulation-exacted power estimation often requires a dedicated testharness for the block under evalution (DUT). While the Hammer flow supports such configurations (further details can be found in the Hammer documentation), Chipyard's integrated flows support an automated full digital SoC simulation-extracted post-par power estimation through the integration of software RTL simulation flows with the Hammer VLSI flow. As such, full digital SoC simulation-extracted power estimation can be performed by specifying a simple binary executable with the associated ``make`` command. + +.. code-block:: shell + + make power-par BINARY=/path/to/baremetal/binary/rv64ui-p-addi.riscv CONFIG= tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" Signoff ^^^^^^^^^ During chip tapeout, you will need to perform sign-off check to make sure the generated GDSII can be fabricated as intended. This is done using dedicated signoff tools that perform design rule checking (DRC) and layout versus schematic (LVS) verification. -In most cases, placed-and-routed designs will not pass DRC and LVS on first attempts due to nuanced design rules and silent failures of the place-and-route tools. Passing DRC and LVS will often requires adding manual placement constraints to "force" the EDA tools into certain patterns. +In most cases, placed-and-routed designs will not pass DRC and LVS on first attempts due to nuanced design rules and subtle/silent failures of the place-and-route tools. Passing DRC and LVS will often requires adding manual placement constraints to "force" the EDA tools into certain patterns. If you have placed-and-routed a design with the goal of getting area and power estimates, DRC and LVS are not strictly neccessary and the results will likely be quite similar. If you are intending to tapeout and fabricate a chip, DRC and LVS are mandatory and will likely requires multiple-iterations of refining manual placement constraints. - +Having a large number of DRC/LVS violations can have a significant impact on the runtime of the place-and-route procedure (since the tools will try to fix each of them several times). A large number of DRC/LVS violations may also be an indication that the design is not necessarily realistic for this particular process technology, which may have power/area implications. Since signoff checks are required only for a complete chip tapeout, they are currently not fully automated in Hammer, and often require some additional manual inclusion of custom Makefiles associated with specific process technologies. However, the general steps from running signoff within Hammer (under the assumption of a fully automated tech plug-in) are Make commands similar to the previous steps. @@ -214,4 +222,4 @@ Composing a Hierarchical Design Customizing Generated Tcl Scripts ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The ``example-vlsi`` python script is the Hammer entry script with placeholders for hooks. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in the ``example-vlsi`` entry script example. In this particular example, a list of hooks is paased in the ``get_extra_par_hooks`` function in the ``ExampleDriver`` class. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. +The ``example-vlsi`` python script is the Hammer entry script with placeholders for hooks. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in the ``example-vlsi`` entry script example. In this particular example, a list of hooks is paased in the ``get_extra_par_hooks`` function in the ``ExampleDriver`` class. Refer to the `Hammer documentation on hooks `__ for a detailed description of how these are injected into the VLSI flow. diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index 49439de7..43f54997 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -24,8 +24,7 @@ vlsi.inputs.pin.generate_mode: semi_auto # The path name should match the VLSI_TOP makefile parameter if it is set par.innovus.floorplan_mode: "auto" vlsi.inputs.placement_constraints: -# - path: "ChipTop" - - path: "Gemmini" + - path: "ChipTop" type: toplevel x: 0 y: 0 From db1543c4ed6aafeb551b218f910bc809babbc4c3 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 7 Dec 2020 00:23:52 -0800 Subject: [PATCH 395/457] [skip ci] hammer request message --- docs/VLSI/Basic-Flow.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 1af4f588..0338a46f 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -3,7 +3,7 @@ Using Hammer To Place and Route a Custom Block ================================================= -.. IMPORTANT:: In order to use the Hammer VLSI flow, you need access to Hammer tools and technology plugins. You can obtain these by emailing hammer-plugins-access@lists.berkeley.edu with a request for which plugin(s) you would like access to. +.. IMPORTANT:: In order to use the Hammer VLSI flow, you need access to Hammer tools and technology plugins. You can obtain these by emailing hammer-plugins-access@lists.berkeley.edu with a request for which plugin(s) you would like access to. Make sure your email includes your github ID and proof (through affiliation or otherwise) that you have licensed access to relevant tools. Initialize the Hammer Plug-ins ---------------------------------- From d6037946a656df1b0eb222b9f3d6c805cee8fec4 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 7 Dec 2020 00:30:12 -0800 Subject: [PATCH 396/457] [skip ci] remove vlsi.core.node from example --- vlsi/example-tech.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/vlsi/example-tech.yml b/vlsi/example-tech.yml index a5de62f9..c6e21a7d 100644 --- a/vlsi/example-tech.yml +++ b/vlsi/example-tech.yml @@ -3,8 +3,5 @@ vlsi.core.technology: vlsi.core.technology_path: ["hammer--plugin"] vlsi.core.technology_path_meta: append -# tech node measured in nm (required because of licensing) -vlsi.core.node: - # technology files installation directory technology..install_dir: "" From 76ba68b02f6cc925772f7ac75925e21995b07caa Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 06:34:30 +0000 Subject: [PATCH 397/457] Bump hwacha --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index 27e03b7e..a354150c 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 27e03b7e2694b4389c64c92a3518b1dba5304905 +Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588 From 1787fda8c3ef936b59d50e040a93afe6355ab613 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 06:34:39 +0000 Subject: [PATCH 398/457] Bump icenet --- generators/icenet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/icenet b/generators/icenet index 277a9080..084ca507 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 +Subproject commit 084ca5070605ea7919358f917289cca240d0289a From ee436c9b3f73c239ce3b80726a3094225f3e3b56 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 07:18:12 +0000 Subject: [PATCH 399/457] [firechip] Fix a uart multiclock bug --- generators/firechip/src/main/scala/BridgeBinders.scala | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 0572fabd..cdb026e1 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -4,12 +4,13 @@ package firesim.firesim import chisel3._ import chisel3.experimental.annotate +import chisel3.util.experimental.BoringUtils import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} import freechips.rocketchip.amba.axi4.{AXI4Bundle} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart._ @@ -86,7 +87,12 @@ class WithNICBridge extends OverrideHarnessBinder({ class WithUARTBridge extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => - ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil + val uartSyncClock = Wire(Clock()) + uartSyncClock := false.B.asClock + val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode + val pbusClock = pbusClockNode.in.head._1.clock + BoringUtils.bore(pbusClock, Seq(uartSyncClock)) + ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ From f1f479912c85d1938d47b3f63d52647e1e365f6b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 11 Dec 2020 03:22:59 +0000 Subject: [PATCH 400/457] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7ab7bc4a..e43828a1 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7ab7bc4a2baaf04f5d8c03094c976e43dc1b2344 +Subproject commit e43828a1fc9608123ae94abc40dfe813ccf23860 From db15419e1092e4475cd7b0b921b9b690b2644838 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 11 Dec 2020 03:55:49 +0000 Subject: [PATCH 401/457] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 3a29f535..15fa68b3 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 3a29f535726a191d09164470eb1ce1a1ddd5bf9a +Subproject commit 15fa68b3a40addc5ac77a78ced37497dbce3f687 From d4d483c081869185f4e24063f17430b31ac98add Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 10:19:02 -0800 Subject: [PATCH 402/457] Bump BOOM | Use ucb-bar fork chisel-testers --- .gitmodules | 2 +- generators/boom | 2 +- tools/chisel-testers | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 55b4be56..bb803d98 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/abejgonzalez/chisel-testers.git + url = https://github.com/ucb-bar/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/generators/boom b/generators/boom index a53372fc..eab35947 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit a53372fcff4c1095a513eb8bb6e8a2b9cdb971a0 +Subproject commit eab359478622cb089ac3164e8efc158a9b0b5028 diff --git a/tools/chisel-testers b/tools/chisel-testers index 5b9cc56d..461e8d3a 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 5b9cc56dd80c8d3bce67d54385d769037e2481d8 +Subproject commit 461e8d3a3e2f2e4c78d60c239428214cf8c7d773 From 5c7c1295a1ea5f1184121944c61be090260682b1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 11:37:25 -0800 Subject: [PATCH 403/457] Bump Gemmini+Dsptools | Fix SBT_OPTs in CI --- .circleci/defaults.sh | 2 +- generators/gemmini | 2 +- tools/dsptools | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 015aaee7..12c4531f 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -35,7 +35,7 @@ REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) diff --git a/generators/gemmini b/generators/gemmini index eb719930..70517c52 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit eb7199307d3adf994c78b02a54859f3e37ac7012 +Subproject commit 70517c52f2d36c0fc1370b3b9836297646a70289 diff --git a/tools/dsptools b/tools/dsptools index 27304bde..aad6a3db 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 27304bdeae3e4fb969c7cac1e0bda358be7cdb12 +Subproject commit aad6a3db1520a05ae668681941a19bdcc40aec03 From 939e3a9f94d5bfef9671f49c37cd3acd5fc26128 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 14:18:18 -0800 Subject: [PATCH 404/457] Bump paradise plugin | Remove extra rm for SBT-server timestamp | Small bump for barstools --- build.sbt | 2 +- common.mk | 1 - sims/firesim | 2 +- tools/barstools | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index b24fa748..e984de86 100644 --- a/build.sbt +++ b/build.sbt @@ -13,7 +13,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { // drop dependencies (org, name) diff --git a/common.mk b/common.mk index 33c0137c..24ab5687 100644 --- a/common.mk +++ b/common.mk @@ -237,7 +237,6 @@ launch-sbt: .PHONY: shutdown-sbt-server shutdown-sbt-server: cd $(base_dir) && $(SBT) "shutdown" - rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) .PHONY: start-sbt-server start-sbt-server: diff --git a/sims/firesim b/sims/firesim index e43828a1..52a9d0fd 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e43828a1fc9608123ae94abc40dfe813ccf23860 +Subproject commit 52a9d0fd2fd3f4ef32337ebd07e36e7ec16d906a diff --git a/tools/barstools b/tools/barstools index 15fa68b3..62f31165 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 15fa68b3a40addc5ac77a78ced37497dbce3f687 +Subproject commit 62f311654a4b31ccbc2839beaee64cd770ecd4a0 From fe4aa6cade03840b80c32911873c9586cce224f4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 14:20:09 -0800 Subject: [PATCH 405/457] Bump BOOM/Gemmini --- generators/boom | 2 +- generators/gemmini | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index eab35947..4bb6464f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit eab359478622cb089ac3164e8efc158a9b0b5028 +Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28 diff --git a/generators/gemmini b/generators/gemmini index 70517c52..e6e14f71 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 70517c52f2d36c0fc1370b3b9836297646a70289 +Subproject commit e6e14f711760b976d8eb00c32d0fe2423aeda211 From f1e3117ae38f1f41d56a696d5c7bd89c4d93d146 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 15:02:43 -0800 Subject: [PATCH 406/457] Bump barstools for test fixes | Small bump FireSim --- sims/firesim | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/firesim b/sims/firesim index 52a9d0fd..f1dafa1b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52a9d0fd2fd3f4ef32337ebd07e36e7ec16d906a +Subproject commit f1dafa1bae05b8e4d752843ab489fd85e6df75bc diff --git a/tools/barstools b/tools/barstools index 62f31165..689ebdc0 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 62f311654a4b31ccbc2839beaee64cd770ecd4a0 +Subproject commit 689ebdc06e29028861f3282d9af6f2304541c9db From 8f1e20936fbc515875b24c11367343aed9748dba Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 12 Dec 2020 13:41:32 -0800 Subject: [PATCH 407/457] Update FireSim CI. Push threading into test context --- .../src/test/scala/ScalaTestSuite.scala | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 64b9b4ba..51695690 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -42,10 +42,9 @@ abstract class FireSimTestSuite( } def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { - behavior of s"${name} running on ${backend} in MIDAS-level simulation" compileMlSimulator(backend, debug) if (isCmdAvailable(backend)) { - it should s"pass" in { + it should s"pass in ML simualtion on ${backend}" in { assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0) } } @@ -59,13 +58,15 @@ abstract class FireSimTestSuite( case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv" case _ => "" } - val results = suite.names.toSeq sliding (N, N) map { t => - val subresults = t map (name => - Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) - Await result (Future sequence subresults, Duration.Inf) - } - results.flatten foreach { case (name, exitcode) => - it should s"pass $name" in { assert(exitcode == 0) } + it should s"pass all tests in ${suite.makeTargetName}" in { + val results = suite.names.toSeq sliding (N, N) map { t => + val subresults = t map (name => + Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) + Await result (Future sequence subresults, Duration.Inf) + } + results.flatten foreach { case (name, exitcode) => + assert(exitcode == 0, "Failed $name") + } } } else { ignore should s"pass $backend" @@ -96,7 +97,9 @@ abstract class FireSimTestSuite( } } - clean + mkdirs + behavior of s"Tuple: ${targetTuple}" + elaborateAndCompile() runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) runSuite("verilator")(benchmarks) } From 558cff7469b6a976d4616b82d90ede4e3212bd77 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 12 Dec 2020 23:04:40 -0800 Subject: [PATCH 408/457] update partial power flow --- docs/VLSI/Basic-Flow.rst | 11 +++++++++-- vlsi/example-tools.yml | 9 +++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 0338a46f..fbe966a6 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -46,7 +46,7 @@ Hammer relies on YAML-based configuration files. While these configuration can b OpenRoad example), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design. The ``vlsi`` directory includes three such example configuration files matching the three concerns: ``example-tools.yml``, ``example-tech.yml``, and ``example-design.yml``. -The ``example-tools.yml`` file configures which EDA tools hammer will use. This example files uses Cadence Innovus, Genus and Mentor Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). Note that tool versions are highly sensitive to the process-technology in-use. Hence, tool versions that work with one process technology may not work with another (for example, ASAP7 will not work with an Innovus version newer than 18.1, while other proprietary process technologies will likely require newer versions such as 19.1). +The ``example-tools.yml`` file configures which EDA tools hammer will use. This example file uses Cadence Innovus, Genus and Voltus, Synopsys VCS, and Mentor Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). Note that tool versions are highly sensitive to the process-technology in-use. Hence, tool versions that work with one process technology may not work with another (for example, ASAP7 will not work with an Innovus version newer than 18.1, while other proprietary process technologies will likely require newer versions such as 19.1). The ``example-design.yml`` file contains basic build system information (how many cores/threads to use, etc.), as well as configurations that are specific to the design we are working on such as clock signal name and frequency, power modes, floorplan, and additional constraints that we will add later on. @@ -150,7 +150,8 @@ Power Estimation Power estimation in Hammer can be performed in one of two stages: post-synthesis (post-syn) or post-place-and-route (post-par). The most accurate power estimation is post-par, and it includes finer grained details of the places instances and wire lengths. Post-par power estimation can be based on static average signal toggles rates (also known as "static power estimation"), or based on simulation-extracted signal toggle data (also known as "dynamic power estimation"). -In order to run post-par power estimation, make sure that a power estimation tool (such as Cadence Voltus) has been defined in your ``example-tools.yml`` file. +.. Warning:: In order to run post-par power estimation, make sure that a power estimation tool (such as Cadence Voltus) has been defined in your ``example-tools.yml`` file. Make sure that the power estimation tool (for example, Cadence Voltus) version matches the physical design tool (for example, Cadence Innovus) version, otherwise you will encounter a database mismatch error. + Simulation-exacted power estimation often requires a dedicated testharness for the block under evalution (DUT). While the Hammer flow supports such configurations (further details can be found in the Hammer documentation), Chipyard's integrated flows support an automated full digital SoC simulation-extracted post-par power estimation through the integration of software RTL simulation flows with the Hammer VLSI flow. As such, full digital SoC simulation-extracted power estimation can be performed by specifying a simple binary executable with the associated ``make`` command. .. code-block:: shell @@ -158,6 +159,12 @@ Simulation-exacted power estimation often requires a dedicated testharness for t make power-par BINARY=/path/to/baremetal/binary/rv64ui-p-addi.riscv CONFIG= tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" +The simulation-extracted power estimation flow implicitly uses Hammer's gate-level simulation flow (in order to generate the ``saif`` activity data file). This gate-level simulation flow can also be run independantly from the power estimation flow using the ``make sim-par`` command. + + +.. Note:: The gate-level simulation flow (and there the simulation-extracted power-estimation) is currently integrated only with the Synopsys VCS simulation (Verilator does not support gate-level simulation. Support for Cadence Incisive is work-in-progress) + + Signoff ^^^^^^^^^ diff --git a/vlsi/example-tools.yml b/vlsi/example-tools.yml index 1f86913f..338481ec 100644 --- a/vlsi/example-tools.yml +++ b/vlsi/example-tools.yml @@ -22,3 +22,12 @@ vlsi.core.drc_tool: "calibre" vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] vlsi.core.lvs_tool: "calibre" vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] +# VCS options +vlsi.core.sim_tool: "vcs" +vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"] +sim.vcs.version: "P-2019.06-SP2-5" +# # Voltus options +vlsi.core.power_tool: "voltus" +vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"] +vlsi.core.power_tool_path_meta: "append" +power.voltus.version: "191_ISR3" From 1bd51447fe890cd0a6450bb655dc6d84c79fe851 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Dec 2020 10:45:51 -0500 Subject: [PATCH 409/457] [ci skip] Fix Typo in firechip/src/test/scala/ScalaTestSuite.scala Co-authored-by: Abraham Gonzalez --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 51695690..64b217b8 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -44,7 +44,7 @@ abstract class FireSimTestSuite( def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { compileMlSimulator(backend, debug) if (isCmdAvailable(backend)) { - it should s"pass in ML simualtion on ${backend}" in { + it should s"pass in ML simulation on ${backend}" in { assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0) } } From a8d6daef93a6e17dab181de3f8875743e93ef58f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Dec 2020 09:32:44 -0800 Subject: [PATCH 410/457] Small build.sbt comments --- build.sbt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index e984de86..e80b2a5e 100644 --- a/build.sbt +++ b/build.sbt @@ -16,7 +16,7 @@ lazy val commonSettings = Seq( addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { - // drop dependencies (org, name) + // drop specific maven dependencies in subprojects in favor of Chipyard's version val dropDeps = Seq( ("edu.berkeley.cs", "firrtl"), ("edu.berkeley.cs", "chisel3"), @@ -86,6 +86,7 @@ lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") Global / firrtlLibDeps := { + // drop antlr4 compile dep. but keep antlr4-runtime dep. (compile needs the plugin to be setup) (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4") } @@ -144,7 +145,7 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) ) lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) -// -- "Problematic" Projects -- +// -- Chipyard-managed External Projects -- lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .sourceDependency(firrtlRef, firrtlLib) @@ -168,7 +169,7 @@ lazy val chisel_testers = (project in file("tools/chisel-testers")) .settings(commonSettings) lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies) -// -- UCB-controlled Projects -- +// -- Normal Projects -- // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS From 02f22e0061ee475103d8b34a2ad6da26dad072ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Dec 2020 09:37:48 -0800 Subject: [PATCH 411/457] Bump build.sbt.patch [ci skip] --- scripts/tutorial-patches/build.sbt.patch | 26 ++++++++++++++---------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index cb289b6f..62cecb8d 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,26 +1,30 @@ diff --git a/build.sbt b/build.sbt -index 5d642c1..56f6fda 100644 +index e80b2a5..b1989d9 100644 --- a/build.sbt +++ b/build.sbt -@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) - - lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, +@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO + lazy val chipyard = (project in file("generators/chipyard")) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) + .settings(libraryDependencies ++= rocketLibDeps.value) +@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6")) - .dependsOn(rocketchip) - .settings(commonSettings) - + -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +- .settings(libraryDependencies ++= rocketLibDeps.value) +- .settings(libraryDependencies ++= chiselTestersLibDeps.value) - .settings(commonSettings) +//lazy val sha3 = (project in file("generators/sha3")) +// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .settings(libraryDependencies ++= rocketLibDeps.value) ++// .settings(libraryDependencies ++= chiselTestersLibDeps.value) +// .settings(commonSettings) - + lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip, chisel_testers, testchipip) + .sourceDependency(testchipip, testchipipLib) From 0754c1e52b73cae7d79a429384a771bbd94a2397 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Mon, 14 Dec 2020 15:10:24 -0800 Subject: [PATCH 412/457] toolchains: Disable CC and CXX overrides for libgloss build --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 1897d157..92cd24dc 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -135,7 +135,7 @@ module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" # Common tools (not in any particular toolchain dir) -SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf +CC= CXX= SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf if [ -z "$IGNOREQEMU" ] ; then SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu From 8836f84c79772e2cf9b8fc9118fb862ed2cce9a7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 15 Dec 2020 16:49:01 -0800 Subject: [PATCH 413/457] [vlsi] Add USE_SRAM_COMPILER Makefile flag to use memory compiler defined in tech library (#740) --- vlsi/Makefile | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 0e1989dd..06f1a1b4 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -25,9 +25,15 @@ tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ - --mode synflops,\ - -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) + +ifeq ($(tech_name),asap7) + MACROCOMPILER_MODE ?= --mode synflops +else ifdef USE_SRAM_COMPILER + MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict +else + MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict +endif + ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ example-nangate45.yml,\ From f693972e1249aaac5d882d6e55e4eb5a81a99bd0 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:56:01 +0000 Subject: [PATCH 414/457] Start RC bump Bump to pre-merge chipsalliance/rocket-chip#2764 to get it going while picking up the chisel/firrtl bugfixes in 3/1.4.1+ --- build.sbt | 4 ++-- generators/rocket-chip | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index e80b2a5e..c3aa9515 100644 --- a/build.sbt +++ b/build.sbt @@ -72,7 +72,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // -- Rocket Chip -- // This needs to stay in sync with the chisel3 and firrtl git submodules -val chiselVersion = "3.4.0" +val chiselVersion = "3.4.1" lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) @@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -val firrtlVersion = "1.4.+" +val firrtlVersion = "1.4.1" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") diff --git a/generators/rocket-chip b/generators/rocket-chip index 577994e3..a7b016e4 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e +Subproject commit a7b016e46e22e4fdc013357051e30511f80df082 diff --git a/tools/chisel3 b/tools/chisel3 index d379dca4..58d38f96 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9 +Subproject commit 58d38f9620e7e91e4668266686484073c0ba7d2e diff --git a/tools/firrtl b/tools/firrtl index 05d047a9..7756f8f9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9 +Subproject commit 7756f8f9634b68a1375d2c2ca13abc5742234201 From 95420baccfd1ce26354d6af70a09c7f3b50d448b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:57:05 +0000 Subject: [PATCH 415/457] Bump boom for riscv-boom/riscv-boom#508 non-master pre-merge bump --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4bb6464f..1899670a 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28 +Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 From c6dfa1d8c5de36bedfc6e3119ae2394fae2ded86 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 18:03:51 +0000 Subject: [PATCH 416/457] Bump testchipip for ucb-bar/testchipip#111 --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 6fbb1b77..ca67a843 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b +Subproject commit ca67a843bd8f568e205981380c11d321d1bad677 From 5ff5b4e8b7601b461e5d222856ea1a2aaabdab0b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:05:29 +0000 Subject: [PATCH 417/457] Bump sifive-cache for sifive/block-inclusivecache-sifive#18 --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index d4db623f..b1160adc 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0 +Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 From f7a372153acf34416f9c6f9c6a10afb95675ab43 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:00 +0000 Subject: [PATCH 418/457] Bump hwacha for ucb-bar/hwacha#24 --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index a354150c..62c01f5a 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588 +Subproject commit 62c01f5a8858aa1b827f0f9372a4392d7b596fca From 022dbf976ff6f389b40a9e058a2406945b88670e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:30 +0000 Subject: [PATCH 419/457] Bump boom along in the same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 1899670a..ad27160f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 +Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 From 2ce5f6a40723200761506be0c23042597d1a0045 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:54:31 +0000 Subject: [PATCH 420/457] Bump cva6 for ucb-bar/cva6-wrapper#11 --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index d40a8f5c..139741a5 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6 +Subproject commit 139741a584d7e3c0446db592b5d99529bd6cf9fa From a2ce14f8d3528cb2e86c990a35d82655c3f4cc9e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 21:03:12 +0000 Subject: [PATCH 421/457] Bump sodor for ucb-bar/riscv-sodor#60 --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index cca8a7aa..8fc51640 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc +Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485 From cb558b59529a328164e7f96bbcba21629df4fc11 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:20:31 +0000 Subject: [PATCH 422/457] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index ad27160f..e250c70f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 +Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e From a7e6de835ad5c641c516dc310269a0b921e24452 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:22:03 +0000 Subject: [PATCH 423/457] rm *XTypeKey. upstreamed to RC --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 8 -------- 1 file changed, 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index ee694d22..0a5c1c30 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -13,14 +13,6 @@ import freechips.rocketchip.subsystem._ // For subsystem/BusTopology.scala -/** - * Keys that serve as a means to define crossing types from a Parameters instance - */ -case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) -case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) - // Biancolin: This, modified from Henry's email /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ case class CoherentMulticlockBusTopologyParams( From 72d084da8f8244e29420dfff0a95494d06489562 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:24:19 +0000 Subject: [PATCH 424/457] update parameter classes for RC additions --- generators/chipyard/src/main/scala/example/TutorialTile.scala | 4 ++++ generators/tracegen/src/main/scala/Tile.scala | 2 ++ 2 files changed, 6 insertions(+) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 23b05f76..fad51c01 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.prci.ClockSinkParameters // Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure @@ -39,6 +40,7 @@ case class MyCoreParams( val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket val nLocalInterrupts: Int = 0 + val useNMI: Boolean = false val nPMPs: Int = 0 // TODO: Check val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check @@ -51,6 +53,7 @@ case class MyCoreParams( val misaWritable: Boolean = false val haveCFlush: Boolean = false val nL2TLBEntries: Int = 512 // copied from Rocket + val nL2TLBWays: Int = 1 val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket val mtvecWritable: Boolean = true // copied from Rocket val instBits: Int = if (useCompressed) 16 else 32 @@ -83,6 +86,7 @@ case class MyTileParams( val boundaryBuffers: Boolean = false val dcache: Option[DCacheParams] = Some(DCacheParams()) val icache: Option[ICacheParams] = Some(ICacheParams()) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { new MyTile(this, crossing, lookup) } diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 5ff9af56..712cffc1 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.subsystem._ import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} +import freechips.rocketchip.prci.ClockSinkParameters class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) @@ -190,6 +191,7 @@ case class BoomTraceGenParams( val blockerCtrlAddr = None val name = None val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() } class BoomTraceGenTile private( From 29ab6301e0786def4608f7ad3d6456ae36b93c8f Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:15:49 +0000 Subject: [PATCH 425/457] bump sifive-cache for merged sifive/block-inclusivecache-sifive#15 my previous bump duplicated an earlier PR --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index b1160adc..e3a3000c 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 +Subproject commit e3a3000cc1fd4cdf3a4e638e4d081b8aae94ebf0 From e22350092bdcb11c1f303cf7205eb6caec77efff Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:27:47 +0000 Subject: [PATCH 426/457] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index e250c70f..75399e3c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e +Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 From 36b9bf86ff9b0aec442be5d0f415e5e45924e76b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 22 Dec 2020 22:45:58 -0800 Subject: [PATCH 427/457] Update MINGIT version to 1.8.5 (#745) 1.8.5 is necessary for `git -C` to work. --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c861658d..803e9889 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -11,7 +11,7 @@ case ${MYGIT} in [1-9]*) ;; *) echo 'warning: unknown git version' ;; esac -MINGIT="1.7.8" +MINGIT="1.8.5" if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then echo "This script requires git version $MINGIT or greater. Exiting." false From 0f47d80edb350ec41d96586d57b886f50882af2b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 23 Dec 2020 15:00:57 +0000 Subject: [PATCH 428/457] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 75399e3c..e1a70afe 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 +Subproject commit e1a70afed7de77f6ba9f6e501de71f7f41afc47c From 7a0ca12f599c608381dc2ac5e20f48f30f54e3cc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 27 Dec 2020 21:27:01 -0800 Subject: [PATCH 429/457] Bump build.sbt --- build.sbt | 1 + 1 file changed, 1 insertion(+) diff --git a/build.sbt b/build.sbt index 3cb903ef..f44eeb66 100644 --- a/build.sbt +++ b/build.sbt @@ -313,6 +313,7 @@ lazy val firechip = (project in file("generators/firechip")) ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .dependsOn(rocketchip, sifive_blocks) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val fpga_platforms = (project in file("./fpga")) From b797077334ffefcb5f9ab5c6397fe4c7fd18baf8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 27 Dec 2020 22:00:06 -0800 Subject: [PATCH 430/457] Fix Arty documentation link --- fpga/src/main/scala/arty/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index fa9a47e0..66391b41 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -38,4 +38,4 @@ class WithArtyTweaks extends Config( class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ new chipyard.TinyRocketConfig) -// DOC include start: AbstractArty and Rocket +// DOC include end: AbstractArty and Rocket From cb488b8137bd1edc68e37762e5636b20f92ea046 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 27 Dec 2020 22:49:24 -0800 Subject: [PATCH 431/457] Init fpga-shells submod in CI --- .circleci/do-rtl-build.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index fcc76bfa..ed233df1 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -19,6 +19,7 @@ trap clean EXIT cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh +./scripts/init-fpga.sh # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" From fbb8ad3e61d664173361a1853ee7ef90246acab1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 28 Dec 2020 10:50:10 -0700 Subject: [PATCH 432/457] Fix small documentation errors --- docs/Prototyping/Arty.rst | 4 ++-- docs/Prototyping/General.rst | 2 +- docs/Prototyping/VCU118.rst | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst index d01cc5c2..204eacec 100644 --- a/docs/Prototyping/Arty.rst +++ b/docs/Prototyping/Arty.rst @@ -1,8 +1,8 @@ Running a Design on Arty ======================== -Basic Design ------------- +Basic Arty Design +----------------- The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__. The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC. diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index a653f20a..0221b82b 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -15,7 +15,7 @@ To initialize the ``fpga-shells`` submodule repository, run the included initial ./scripts/init-fpga.sh Generating a Bitstream ------------------- +---------------------- Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation. Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 9deb8739..c12e3714 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -1,8 +1,8 @@ Running a Design on VCU118 ========================== -Basic Design ------------- +Basic VCU118 Design +------------------- The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory. This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). @@ -52,4 +52,4 @@ This example extends the default test harness and creates new ``Overlays`` to co .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. - See :ref:`Making a Bitstream` for information on the various make variables. + See :ref:`Generating a Bitstream` for information on the various make variables. From b1cedf2d61b925b0b44655302f41a1b08b36e885 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 28 Dec 2020 09:55:10 -0800 Subject: [PATCH 433/457] Make TinyRocketConfig work with multi-clock work --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 10 ++++++++++ .../chipyard/src/main/scala/config/RocketConfigs.scala | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index 0a5c1c30..7bbd53f1 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -70,3 +70,13 @@ class WithMulticlockCoherentBusTopology extends Config((site, here, up) => { l2 = site(BankedL2Key), sbusToMbusXType = site(SbusToMbusXTypeKey))) }) + +class WithMulticlockIncoherentBusTopology extends Config((site, here, up) => { + case TLNetworkTopologyLocated(InSubsystem) => List( + JustOneBusTopologyParams(sbus = site(SystemBusKey)), + HierarchicalMulticlockBusTopologyParams( + pbus = site(PeripheryBusKey), + fbus = site(FrontBusKey), + cbus = site(ControlBusKey), + xTypes = SubsystemCrossingParams())) +}) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index fab1a9d5..308ebc39 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -15,7 +15,7 @@ class TinyRocketConfig extends Config( new chipyard.config.WithTLSerialLocation( freechips.rocketchip.subsystem.FBUS, freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology + new chipyard.WithMulticlockIncoherentBusTopology ++ // use incoherent bus topology new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core @@ -189,7 +189,7 @@ class MMIORocketConfig extends Config( class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications - new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency From a6ca3d21ad55e9010ffc8b1cbc9ad3d121396af6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 28 Dec 2020 16:07:57 -0800 Subject: [PATCH 434/457] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 71d04939..0e06d3c0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 71d049390348b273caf74cb90231ea05272322ae +Subproject commit 0e06d3c054ddbc9c3d3fc7681819b52b1d1f40fd From 5099a96a7b943b15e4e9fd56c20cb2dc0ac90541 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 28 Dec 2020 16:09:34 -0800 Subject: [PATCH 435/457] Bump fpga-shells (to sifive/master) --- .gitmodules | 2 +- fpga/fpga-shells | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 69ce8245..17c9a4b4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -133,4 +133,4 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = https://github.com/abejgonzalez/fpga-shells.git + url = https://github.com/sifive/fpga-shells.git diff --git a/fpga/fpga-shells b/fpga/fpga-shells index fcfadb4c..f9fb9fd3 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit fcfadb4cf36dfbcd7cfee525404b56bf661793b9 +Subproject commit f9fb9fd338e5fca2ff5116b1d01506c424280d70 From 2e1aba653a8b3c944b017c2ccb703f5804510261 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 11:04:07 -0800 Subject: [PATCH 436/457] Bump chisel-testers back to freechipsproject --- .gitmodules | 2 +- tools/chisel-testers | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index bb803d98..7054c14f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/ucb-bar/chisel-testers.git + url = https://github.com/freechipsproject/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/tools/chisel-testers b/tools/chisel-testers index 461e8d3a..ce4e027e 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 461e8d3a3e2f2e4c78d60c239428214cf8c7d773 +Subproject commit ce4e027e5f3d871df59236b8471ea3e5be40130e From 06dccdb588d6bd42b2ac337f3fcc2b9985e5df49 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 10:54:05 -0800 Subject: [PATCH 437/457] Organize check commit CI printout | Don't copy .git folder in CI --- .circleci/check-commit.sh | 16 +++++++++++----- .circleci/defaults.sh | 2 +- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 2660fa49..91ee9e80 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -124,19 +124,25 @@ search # turn off verbose printing to make this easier to read set +x -# print all result strings +# print 0's for str in "${all_names[@]}"; do - echo "$str" + if [ 0 = $(echo "$str" | awk '{print$3}') ]; then + echo "$str" + fi done -# check if there was a non-zero return code +echo "" + +# check if there was a non-zero return code and print 1's +EXIT=0 for str in "${all_names[@]}"; do if [ ! 0 = $(echo "$str" | awk '{print$3}') ]; then - exit 1 + echo "$str" + EXIT=1 fi done echo "Done checking all submodules" - +exit $EXIT diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 12c4531f..11053f60 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -1,7 +1,7 @@ #!/bin/bash copy () { - rsync -avzp -e 'ssh' $1 $2 + rsync -avzp -e 'ssh' --exclude '.git' $1 $2 } run () { From 6f9dcf547863db05e4941a33f8ff5917e0611b76 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 20:51:29 -0800 Subject: [PATCH 438/457] Add new SSH key to access build server --- .circleci/config.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index f18f0e62..478ff315 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -49,6 +49,7 @@ commands: - add_ssh_keys: fingerprints: - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" + - "32:d6:89:d2:97:fa:db:de:a8:2d:2a:f2:70:dd:80:89" - checkout setup-tools: From ec1efc150e89e7c17aa0634a7cf32b318aa335a8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 21:26:23 -0800 Subject: [PATCH 439/457] Add small comment --- .circleci/do-rtl-build.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 1e065437..316c9c6d 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -56,6 +56,7 @@ run "export RISCV=\"$TOOLS_DIR\"; \ read -a keys <<< ${grouping[$1]} +# need to set the PATH to use the new verilator (with the new verilator root) for key in "${keys[@]}" do run "export RISCV=\"$TOOLS_DIR\"; \ From c8cbfbe3c50326db5a915f74d72fc855faa27115 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 31 Dec 2020 14:15:24 -0800 Subject: [PATCH 440/457] Small documentation addition on bringup --- docs/Prototyping/VCU118.rst | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index c12e3714..6d759f82 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -47,8 +47,13 @@ After the harness is created, the ``BundleBridgeSource``'s must be connected to This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. -An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. -This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. +Introduction to the Bringup Platform +------------------------------------ + +An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. +This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port). +Extensions include another UART (connected over FMC), I2C (connected over FMC), miscellaneous GPIOS (can be connected to anything), and a TSI Host Widget. +The TSI Host Widget is used to interact with the DUT from the prototype over a SerDes link (sometimes called the Low BandWidth InterFace - LBWIF) and provide access to a channel of the FPGA's DRAM. .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. From 4d3ff26a733e2a5e9b6e86afb89216cbbb8ccece Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 4 Jan 2021 15:36:00 -0800 Subject: [PATCH 441/457] Bump testchipip --- fpga/src/main/scala/vcu118/bringup/Configs.scala | 12 +++++++++--- fpga/src/main/scala/vcu118/bringup/TestHarness.scala | 6 +++--- generators/testchipip | 2 +- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index ec1ea1e3..62c2af31 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem.{MasterPortParams} import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} @@ -39,10 +40,9 @@ class WithBringupPeripherals extends Config((site, here, up) => { case TSIClockMaxFrequencyKey => 100 case PeripheryTSIHostKey => List( TSIHostParams( - serialIfWidth = 4, + offchipSerialIfWidth = 4, mmioBaseAddress = BigInt(0x64006000), mmioSourceId = 1 << 13, // manager source - targetSize = site(VCU118DDR2Size), serdesParams = TSIHostSerdesParams( clientPortParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( @@ -61,7 +61,13 @@ class WithBringupPeripherals extends Config((site, here, up) => { supportsArithmetic = TransferSizes(1, 64), supportsLogical = TransferSizes(1, 64))), endSinkId = 1 << 6, // manager sink - beatBytes = 8)))) + beatBytes = 8)), + targetMasterPortParams = MasterPortParams( + base = BigInt("80000000", 16), + size = site(VCU118DDR2Size), + beatBytes = 8, // comes from test chip + idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG + )) }) class WithBringupVCU118System extends Config((site, here, up) => { diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 2e86e646..2406cb7b 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -72,10 +72,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) - val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetBaseAddress, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr + val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr - val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.serialIfWidth, io_tsi_serial_bb)) + val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth))) + dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb)) // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => diff --git a/generators/testchipip b/generators/testchipip index 0e06d3c0..39ed56be 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 0e06d3c054ddbc9c3d3fc7681819b52b1d1f40fd +Subproject commit 39ed56be3e72ce09f64889b9d63c8b9fd98eb726 From 5505aef30fb455aca2a97dc8b8dae3544bcc6a67 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Jan 2021 10:56:30 -0800 Subject: [PATCH 442/457] Bump sifive-blocks --- .gitmodules | 2 +- generators/sifive-blocks | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 17c9a4b4..d5e9ae73 100644 --- a/.gitmodules +++ b/.gitmodules @@ -21,7 +21,7 @@ url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks - url = https://github.com/abejgonzalez/sifive-blocks.git + url = https://github.com/sifive/sifive-blocks.git [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 6cc6128b..545a396f 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 6cc6128b8aeab1f92d4ef55a0a06809a95eee730 +Subproject commit 545a396f3486132b01ceef3cbce2085608984478 From 7e092c655be71b8ac86651be43a8378f25d15af9 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 8 Jan 2021 20:11:21 -0800 Subject: [PATCH 443/457] docs label disambiguation --- docs/Advanced-Concepts/Chip-Communication.rst | 4 ++-- docs/Advanced-Concepts/Debugging-BOOM.rst | 4 ++-- docs/Advanced-Concepts/Top-Testharness.rst | 2 +- docs/Chipyard-Basics/Chipyard-Components.rst | 24 +++++++++---------- .../Configs-Parameters-Mixins.rst | 4 ++-- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 2 +- docs/Customization/Boot-Process.rst | 2 +- docs/Customization/DMA-Devices.rst | 2 +- docs/Customization/Firrtl-Transforms.rst | 4 ++-- docs/Customization/Memory-Hierarchy.rst | 2 +- docs/Generators/IceNet.rst | 10 ++++---- docs/Generators/Rocket-Chip.rst | 2 +- docs/Generators/TestChipIP.rst | 10 ++++---- docs/Generators/index.rst | 2 +- .../NodeTypes.rst | 10 ++++---- .../Register-Router.rst | 4 ++-- docs/TileLink-Diplomacy-Reference/Widgets.rst | 16 ++++++------- docs/Tools/Barstools.rst | 12 ++++------ docs/Tools/Chisel-Testers.rst | 2 +- docs/Tools/Chisel.rst | 2 +- docs/Tools/Dromajo.rst | 2 +- docs/VLSI/Basic-Flow.rst | 7 +++--- docs/VLSI/Building-A-Chip.rst | 4 ++-- docs/VLSI/Tutorial.rst | 2 +- docs/VLSI/index.rst | 1 + docs/conf.py | 3 +++ docs/index.rst | 2 +- 27 files changed, 72 insertions(+), 69 deletions(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 8d63992a..50c5ac9a 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -54,7 +54,7 @@ sends the TSI command recieved by the simulation stub into the DUT which then co command into a TileLink request. This conversion is done by the ``SerialAdapter`` module (located in the ``generators/testchipip`` project). In simulation, FESVR resets the DUT, writes into memory the test program, and indicates to the DUT to start the program -through an interrupt (see :ref:`Chipyard Boot Process`). Using TSI is currently the fastest +through an interrupt (see :ref:`customization/Boot-Process:Chipyard Boot Process`). Using TSI is currently the fastest mechanism to communicate with the DUT in simulation. In the case of a chip tapeout bringup, TSI commands can be sent over a custom communication @@ -96,7 +96,7 @@ Starting the TSI or DMI Simulation ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ All default Chipyard configurations use TSI to communicate between the simulation and the simulated SoC/DUT. Hence, when running a -software RTL simulation, as is indicated in the :ref:`Software RTL Simulation` section, you are in-fact using TSI to communicate with the DUT. As a +software RTL simulation, as is indicated in the :ref:`simulation/Software-RTL-Simulation:Software RTL Simulation` section, you are in-fact using TSI to communicate with the DUT. As a reminder, to run a software RTL simulation, run: .. code-block:: bash diff --git a/docs/Advanced-Concepts/Debugging-BOOM.rst b/docs/Advanced-Concepts/Debugging-BOOM.rst index fd41a9d7..f4d3b1ff 100644 --- a/docs/Advanced-Concepts/Debugging-BOOM.rst +++ b/docs/Advanced-Concepts/Debugging-BOOM.rst @@ -1,8 +1,8 @@ Debugging BOOM ====================== -In addition to the default debugging techniques specified in :ref:`Debugging RTL`, -single-core BOOM designs can utilize the Dromajo co-simulator (see :ref:`Dromajo`) +In addition to the default debugging techniques specified in :ref:`Advanced-Concepts/Debugging-RTL:Debugging RTL`, +single-core BOOM designs can utilize the Dromajo co-simulator (see :ref:`Tools/Dromajo:Dromajo`) to verify functionality. .. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 43a8a338..103fea91 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -58,7 +58,7 @@ Tops A SoC Top then extends the ``System`` class with traits for custom components. In Chipyard, this includes things like adding a NIC, UART, and GPIO as well as setting up the hardware for the bringup method. -Please refer to :ref:`Communicating with the DUT` for more information on these bringup methods. +Please refer to :ref:`Advanced-Concepts/Chip-Communication:Communicating with the DUT` for more information on these bringup methods. TestHarness ------------------------- diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 398b537d..92c03c2b 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -14,15 +14,15 @@ Processor Cores **Rocket Core** An in-order RISC-V core. - See :ref:`Rocket Core` for more information. + See :ref:`Generators/Rocket:Rocket Core` for more information. **BOOM (Berkeley Out-of-Order Machine)** An out-of-order RISC-V core. - See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. + See :ref:`Generators/BOOM:Berkeley Out-of-Order Machine (BOOM)` for more information. **CVA6 Core** An in-order RISC-V core written in System Verilog. Previously called Ariane. - See :ref:`CVA6 Core` for more information. + See :ref:`Generators/CVA6:CVA6 Core` for more information. Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -31,7 +31,7 @@ Accelerators A decoupled vector architecture co-processor. Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model. Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface. - See :ref:`Hwacha` for more information. + See :ref:`Generators/Hwacha:Hwacha` for more information. **Gemmini** A matrix-multiply accelerator targeting neural-networks @@ -64,24 +64,24 @@ Tools A hardware description library embedded in Scala. Chisel is used to write RTL generators using meta-programming, by embedding hardware generation primitives in the Scala programming language. The Chisel compiler elaborates the generator into a FIRRTL output. - See :ref:`Chisel` for more information. + See :ref:`Tools/Chisel:Chisel` for more information. **FIRRTL** An intermediate representation library for RTL description of digital designs. FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog. FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. - See :ref:`FIRRTL` for more information. + See :ref:`Tools/FIRRTL:FIRRTL` for more information. **Barstools** A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. - See :ref:`Barstools` for more information. + See :ref:`Tools/Barstools:Barstools` for more information. **Dsptools** A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). **Dromajo** A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technologies. - See :ref:`Dromajo` for more information. + See :ref:`Tools/Dromajo:Dromajo` for more information. Toolchains ------------------------------------------- @@ -109,12 +109,12 @@ Sims **verilator (Verilator wrapper)** Verilator is an open source Verilog simulator. The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). - See :ref:`Verilator (Open-Source)` for more information. + See :ref:`Simulation/Software-RTL-Simulation:Verilator (Open-Source)` for more information. **vcs (VCS wrapper)** VCS is a proprietary Verilog simulator. Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). - See :ref:`Synopsys VCS (License Required)` for more information. + See :ref:`Simulation/Software-RTL-Simulation:Synopsys VCS (License Required)` for more information. **FireSim** FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud. @@ -122,7 +122,7 @@ Sims To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others. The use of the elastic public cloud enable FireSim to scale simulations up to thousands of nodes. In order to use FireSim, the repository must be cloned and executed on AWS instances. - See :ref:`FireSim` for more information. + See :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim` for more information. VLSI ------------------------------------------- @@ -132,4 +132,4 @@ VLSI The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical design constraints. The Hammer flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular constraints relating to that process technology (obsolete standard cells, metal layer routing constraints, etc.). The Hammer flow requires access to proprietary EDA tools and process technology libraries. - See :ref:`Core HAMMER` for more information. + See :ref:`VLSI/Hammer:Core HAMMER` for more information. diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index 94067aa1..f55d15be 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -17,7 +17,7 @@ Configs A *config* is a collection of multiple generator parameters being set to specific values. Configs are additive, can override each other, and can be composed of other configs (sometimes referred to as config fragments). The naming convention for an additive config or config fragment is ``With``, while the naming convention for a non-additive config will be ````. -Configs can take arguments which will in-turn set parameters in the design or reference other parameters in the design (see :ref:`Parameters`). +Configs can take arguments which will in-turn set parameters in the design or reference other parameters in the design (see :ref:`Chipyard-Basics/Configs-Parameters-Mixins:Parameters`). This example shows a basic config fragment class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters. In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a set of variables that the generator can use when referencing the ``MyAcceleratorKey`` in the design. @@ -121,7 +121,7 @@ This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial Additional References --------------------------- -Another description of traits/mixins and config fragments is given in :ref:`Keys, Traits, and Configs`. +Another description of traits/mixins and config fragments is given in :ref:`Customization/Keys-Traits-Configs:Keys, Traits, and Configs`. Additionally, a brief explanation of some of these topics (with slightly different naming) is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY. .. Note:: Chipyard uses the name "config fragments" over "config mixins" to avoid confusion between a mixin applying to a config or to the system ``Top`` (even though both are technically Scala mixins). diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 88c8b21e..78301088 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -73,7 +73,7 @@ This depends on what you are planning to do with Chipyard. * If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. -* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. +* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulation/Software-RTL-Simulation:Simulating A Custom Project` and follow the instructions. * If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. diff --git a/docs/Customization/Boot-Process.rst b/docs/Customization/Boot-Process.rst index b6b5e8a3..f52a7afc 100644 --- a/docs/Customization/Boot-Process.rst +++ b/docs/Customization/Boot-Process.rst @@ -34,7 +34,7 @@ FESVR is a program that runs on the host CPU and can read/write arbitrary parts of the target system memory using the Tethered Serial Interface (TSI). FESVR uses TSI to load a baremetal executable or second-stage bootloader into -the SoC memory. In :ref:`Software RTL Simulation`, this will be the binary you +the SoC memory. In :ref:`Simulation/Software-RTL-Simulation:Software RTL Simulation`, this will be the binary you pass to the simulator. Once it is finished loading the program, FESVR will write to the software interrupt register for CPU 0, which will bring CPU 0 out of its WFI loop. Once it receives the interrupt, CPU 0 will write to diff --git a/docs/Customization/DMA-Devices.rst b/docs/Customization/DMA-Devices.rst index 549a1556..876ebd2d 100644 --- a/docs/Customization/DMA-Devices.rst +++ b/docs/Customization/DMA-Devices.rst @@ -22,7 +22,7 @@ that writes zeros to the memory at a configured address. We use ``TLHelper.makeClientNode`` to create a TileLink client node for us. We then connect the client node to the memory system through the front bus (fbus). -For more info on creating TileLink client nodes, take a look at :ref:`Client Node`. +For more info on creating TileLink client nodes, take a look at :ref:`TileLink-Diplomacy-Reference/NodeTypes:Client Node`. Once we've created our top-level module including the DMA widget, we can create a configuration for it as we did before. diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst index 808082e0..de2bfc7c 100644 --- a/docs/Customization/Firrtl-Transforms.rst +++ b/docs/Customization/Firrtl-Transforms.rst @@ -5,7 +5,7 @@ Adding a Firrtl Transform Similar to how LLVM IR passes can perform transformations and optimizations on software, FIRRTL transforms can modify Chisel-elaborated RTL. -As mentioned in Section :ref:`firrtl`, transforms are modifications that happen on the FIRRTL IR that can modify a circuit. +As mentioned in Section :ref:`Tools/FIRRTL:firrtl`, transforms are modifications that happen on the FIRRTL IR that can modify a circuit. Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chisel and run analysis or convert the circuit into a new form. Where to add transforms @@ -24,7 +24,7 @@ If you look inside of the `tools/barstools/tapeout/src/main/scala/transforms/Gen you can see that FIRRTL is invoked twice, once for the "Top" and once for the "Harness". If you want to add transforms to just modify the DUT, you can add them to ``topTransforms``. Otherwise, if you want to add transforms to just modify the test harness, you can add them to ``harnessTransforms``. -For more information on Barstools, please visit the :ref:`Barstools` section. +For more information on Barstools, please visit the :ref:`Tools/Barstools:Barstools` section. Examples of transforms ---------------------- diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 554b6d5f..8664287e 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -13,7 +13,7 @@ if you use the ``WithNMedCores`` or ``WithNSmallCores`` configurations, you can configure 4 KiB direct-mapped caches for L1I and L1D. If you only want to change the size or associativity, there are config -fragments for those too. See :ref:`Config Fragments` for how to add these to a custom ``Config``. +fragments for those too. See :ref:`Customization/Keys-Traits-Configs:Config Fragments` for how to add these to a custom ``Config``. .. code-block:: scala diff --git a/docs/Generators/IceNet.rst b/docs/Generators/IceNet.rst index f7daa71e..3f609d91 100644 --- a/docs/Generators/IceNet.rst +++ b/docs/Generators/IceNet.rst @@ -8,11 +8,11 @@ A diagram of IceNet's microarchitecture is shown below. .. image:: ../_static/images/nic-design.png -There are four basic parts of the NIC: the :ref:`Controller`, which takes requests -from and sends responses to the CPU; the :ref:`Send Path`, which reads data from -memory and sends it out to the network; the :ref:`Receive Path`, which receives +There are four basic parts of the NIC: the :ref:`Generators/IceNet:Controller`, which takes requests +from and sends responses to the CPU; the :ref:`Generators/IceNet:Send Path`, which reads data from +memory and sends it out to the network; the :ref:`Generators/IceNet:Receive Path`, which receives data from the network and writes it to memory; and, optionally, -the :ref:`Pause Handler`, which generates Ethernet pause frames for the purpose +the :ref:`Generators/IceNet:Pause Handler`, which generates Ethernet pause frames for the purpose of flow control. Controller @@ -78,7 +78,7 @@ Configuration To add IceNIC to your design, add ``HasPeripheryIceNIC`` to your lazy module and ``HasPeripheryIceNICModuleImp`` to the module implementation. If you are confused about the distinction between lazy module and module -implementation, refer to :ref:`Cake Pattern / Mixin`. +implementation, refer to :ref:`Chipyard-Basics/Configs-Parameters-Mixins:Cake Pattern / Mixin`. Then add the ``WithIceNIC`` config fragment to your configuration. This will define ``NICKey``, which IceNIC uses to determine its parameters. The config fragment diff --git a/docs/Generators/Rocket-Chip.rst b/docs/Generators/Rocket-Chip.rst index 084a5634..856d01e1 100644 --- a/docs/Generators/Rocket-Chip.rst +++ b/docs/Generators/Rocket-Chip.rst @@ -30,7 +30,7 @@ The tiles connect to the ``SystemBus``, which connect it to the L2 cache banks. The L2 cache banks then connect to the ``MemoryBus``, which connects to the DRAM controller through a TileLink to AXI converter. -To learn more about the memory hierarchy, see :ref:`Memory Hierarchy`. +To learn more about the memory hierarchy, see :ref:`Customization/Memory-Hierarchy:Memory Hierarchy`. MMIO ---- diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 363e3245..24e9d956 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -2,9 +2,9 @@ Test Chip IP ============ Chipyard includes a Test Chip IP library which provides various hardware -widgets that may be useful when designing SoCs. This includes a :ref:`Serial Adapter`, -:ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`, -:ref:`TileLink Ring Network`, and :ref:`UART Adapter`. +widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:Serial Adapter`, +:ref:`Generators/TestChipIP:Block Device Controller`, :ref:`Generators/TestChipIP:TileLink SERDES`, :ref:`Generators/TestChipIP:TileLink Switcher`, +:ref:`Generators/TestChipIP:TileLink Ring Network`, and :ref:`Generators/TestChipIP:UART Adapter`. Serial Adapter -------------- @@ -14,7 +14,7 @@ processor. An instance of RISC-V frontend server running on the host CPU can send commands to the serial adapter to read and write data from the memory system. The frontend server uses this functionality to load the test program into memory and to poll for completion of the program. More information on -this can be found in :ref:`Chipyard Boot Process`. +this can be found in :ref:`Customization/Boot-Process:Chipyard Boot Process`. Block Device Controller ----------------------- @@ -69,7 +69,7 @@ to the TLXbar provided by RocketChip, but uses ring networks internally rather than crossbars. This can be useful for chips with very wide TileLink networks (many cores and L2 banks) that can sacrifice cross-section bandwidth to relieve wire routing congestion. Documentation on how to use the ring network can be -found in :ref:`The System Bus`. The implementation itself can be found +found in :ref:`Customization/Memory-Hierarchy:The System Bus`. The implementation itself can be found `here `_, and may serve as an example of how to implement your own TileLink network with a different topology. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index cfc7d601..6f11c875 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -4,7 +4,7 @@ Included RTL Generators ============================ A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. -This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`). +This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Tools/Chisel:Chisel`). A standard RTL design is essentially just a single instance of a design coming from a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the Chipyard framework. diff --git a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst index 32953944..74fe7854 100644 --- a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst +++ b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst @@ -59,7 +59,7 @@ TileLink messages. The ``edge`` object represents the edge of the Diplomacy graph. It contains some useful helper functions which will be documented in -:ref:`TileLink Edge Object Methods`. +:ref:`TileLink-Diplomacy-Reference/EdgeFunctions:TileLink Edge Object Methods`. Manager Node ------------ @@ -116,7 +116,7 @@ most MMIO peripherals should set it to. The next six arguments start with ``support`` and determine the different A channel message types that the manager can accept. The definitions of the -message types are explained in :ref:`TileLink Edge Object Methods`. +message types are explained in :ref:`TileLink-Diplomacy-Reference/EdgeFunctions:TileLink Edge Object Methods`. The ``TransferSizes`` case class specifies the range of logical sizes (in bytes) that the manager can accept for the particular message type. This is an inclusive range and all logical sizes must be powers of two. So in this case, the manager @@ -137,7 +137,7 @@ to handle TileLink requests, it is usually much easier to use a register node. This type of node provides a ``regmap`` method that allows you to specify control/status registers and automatically generates the logic to handle the TileLink protocol. More information about how to use register nodes can be -found in :ref:`Register Router`. +found in :ref:`TileLink-Diplomacy-Reference/Register-Router:Register Router`. Identity Node ------------- @@ -176,7 +176,7 @@ If we want to connect the client and manager groups together, we can now do this :end-before: DOC include end: MyClientManagerComplex The meaning of the ``:=*`` operator is explained in more detail in the -:ref:`Diplomacy Connectors` section. In summary, it connects two nodes together +:ref:`TileLink-Diplomacy-Reference/Diplomacy-Connectors:Diplomacy Connectors` section. In summary, it connects two nodes together using multiple edges. The edges in the identity node are assigned in order, so in this case ``client1.node`` will eventually connect to ``manager1.node`` and ``client2.node`` will connect to ``manager2.node``. @@ -192,7 +192,7 @@ produces the same number of outputs. However, unlike the identity node, the adapter node does not simply pass the connections through unchanged. It can change the logical and physical interfaces between input and output and rewrite messages going through. RocketChip provides a library of adapters, -which are catalogued in :ref:`Diplomatic Widgets`. +which are catalogued in :ref:`TileLink-Diplomacy-Reference/Widgets:Diplomatic Widgets`. You will rarely need to create an adapter node yourself, but the invocation is as follows. diff --git a/docs/TileLink-Diplomacy-Reference/Register-Router.rst b/docs/TileLink-Diplomacy-Reference/Register-Router.rst index 6f5e1aa0..5e01275d 100644 --- a/docs/TileLink-Diplomacy-Reference/Register-Router.rst +++ b/docs/TileLink-Diplomacy-Reference/Register-Router.rst @@ -32,7 +32,7 @@ The default value is 4 bytes. The ``concurrency`` argument is the size of the internal queue for TileLink requests. By default, this value is 0, which means there will be no queue. This value must be greater than 0 if you wish to decoupled requests and responses for register accesses. This is discussed -in :ref:`Using Functions`. +in :ref:`TileLink-Diplomacy-Reference/Register-Router:Using Functions`. The main way to interact with the node is to call the ``regmap`` method, which takes a sequence of pairs. The first element of the pair is an offset from the @@ -128,7 +128,7 @@ Register Routers for Other Protocols One useful feature of the register router interface is that you can easily change the protocol being used. For instance, in the first example in -:ref:`Basic Usage`, you could simply change the ``TLRegisterNode`` to +:ref:`TileLink-Diplomacy-Reference/Register-Router:Basic Usage`, you could simply change the ``TLRegisterNode`` to and ``AXI4RegisterNode``. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala diff --git a/docs/TileLink-Diplomacy-Reference/Widgets.rst b/docs/TileLink-Diplomacy-Reference/Widgets.rst index 791c1b9b..12086778 100644 --- a/docs/TileLink-Diplomacy-Reference/Widgets.rst +++ b/docs/TileLink-Diplomacy-Reference/Widgets.rst @@ -81,7 +81,7 @@ The arguments for the five-argument constructor are AXI4Buffer ---------- -Similar to the :ref:`TLBuffer`, but for AXI4. It also takes ``BufferParams`` objects +Similar to the :ref:`TileLink-Diplomacy-Reference/Widgets:TLBuffer`, but for AXI4. It also takes ``BufferParams`` objects as arguments. **Arguments:** @@ -200,7 +200,7 @@ transactions. AXI4Fragmenter -------------- -The AXI4Fragmenter is similar to the :ref:`TLFragmenter`, except it can only +The AXI4Fragmenter is similar to the :ref:`TileLink-Diplomacy-Reference/Widgets:TLFragmenter`, except it can only break multi-beat AXI4 transactions into single-beat transactions. This effectively serves as an AXI4 to AXI4-Lite converter. The constructor for this widget does not take any arguments. @@ -237,7 +237,7 @@ you will want to use a TLSourceShrinker. AXI4IdIndexer ------------- -The AXI4 equivalent of :ref:`TLSourceShrinker`. This limits the number of +The AXI4 equivalent of :ref:`TileLink-Diplomacy-Reference/Widgets:TLSourceShrinker`. This limits the number of AWID/ARID bits in the slave AXI4 interface. Useful for connecting to external or black box AXI4 ports. @@ -257,7 +257,7 @@ or black box AXI4 ports. The AXI4IdIndexer will create a ``user`` field on the slave interface, as it stores the ID of the master requests in this field. If connecting to an AXI4 -interface that doesn't have a ``user`` field, you'll need to use the :ref:`AXI4UserYanker`. +interface that doesn't have a ``user`` field, you'll need to use the :ref:`TileLink-Diplomacy-Reference/Widgets:AXI4UserYanker`. TLWidthWidget ------------- @@ -301,7 +301,7 @@ The possible values of ``policy`` are: ordering guaranteed - ``TLFIFOFixer.allVolatile`` - All managers that have a RegionType of ``VOLATILE``, ``PUT_EFFECTS``, or ``GET_EFFECTS`` will have ordering - guaranteed (see :ref:`Manager Node` for explanation of region types). + guaranteed (see :ref:`TileLink-Diplomacy-Reference/NodeTypes:Manager Node` for explanation of region types). TLXbar and AXI4Xbar ------------------- @@ -377,14 +377,14 @@ override the default arguments of the constructors for these widgets. AXI4Fragmenter() := axi4master.node -You will need to add an :ref:`AXI4Deinterleaver` after the TLToAXI4 converter +You will need to add an :ref:`TileLink-Diplomacy-Reference/Widgets:AXI4Deinterleaver` after the TLToAXI4 converter because it cannot deal with interleaved read responses. The TLToAXI4 converter also uses the AXI4 user field to store some information, so you will need an -:ref:`AXI4UserYanker` if you want to connect to an AXI4 port without user +:ref:`TileLink-Diplomacy-Reference/Widgets:AXI4UserYanker` if you want to connect to an AXI4 port without user fields. Before you connect an AXI4 port to the AXI4ToTL widget, you will need to -add an :ref:`AXI4Fragmenter` and :ref:`AXI4UserYanker` because the converter cannot +add an :ref:`TileLink-Diplomacy-Reference/Widgets:AXI4Fragmenter` and :ref:`TileLink-Diplomacy-Reference/Widgets:AXI4UserYanker` because the converter cannot deal with multi-beat transactions or user fields. TLROM diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index e2fbac70..6bd8f036 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -1,5 +1,3 @@ -.. _barstools: - Barstools =============================== @@ -25,15 +23,15 @@ An external module reference is a FIRRTL construct that enables a design to refe A list of unique SRAM configurations is output to a ``.conf`` file by FIRRTL, which is used to map technology SRAMs. Without this transform, FIRRTL will map all ``SeqMem`` s to flip-flop arrays with equivalent behavior, which may lead to a design that is difficult to route. -The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Barstools` scala package. +The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Tools/Barstools:Barstools` scala package. MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. -Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`SRAM MDF Fields`). +Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`Tools/Barstools:SRAM MDF Fields`). Using a user-customizable cost function, MacroCompiler will select the SRAMs that are the best fit for each dimensionality in the ``.conf`` file. This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60x1024, if the latter is not available) or arraying. Arraying can be done in both width and depth, as well as to solve masking constraints. For example, a 128x2048 array could be composed of four 64x1024 arrays, with two macros in parallel to create two 128x1024 virtual SRAMs which are combinationally muxed to add depth. If this macro requires byte-granularity write masking, but no technology SRAMs support masking, then the tool may choose to use thirty-two 8x1024 arrays in a similar configuration. -For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`SRAM MDF Fields` section. +For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`Tools/Barstools:SRAM MDF Fields` section. The output of MacroCompiler is a Verilog file containing modules that wrap the technology SRAMs into the specified interface names from the ``.conf``. If the technology supports an SRAM compiler, then MacroCompiler will also emit HammerIR that can be passed to Hammer to run the compiler itself and generate design collateral. @@ -105,7 +103,7 @@ This is necessary to facilitate post-synthesis and post-place-and-route simulati Simulations after you the design goes through a VLSI flow will use the verilog netlist generated from the flow and will need an untouched test harness to drive it. Separating these components into separate files makes this straightforward. Without the separation the file that included the test harness would also redefine the DUT which is often disallowed in simulation tools. -To do this, there is a FIRRTL ``App`` in :ref:`Barstools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately. +To do this, there is a FIRRTL ``App`` in :ref:`Tools/Barstools:Barstools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately. This also renames modules in the test harness so that any modules that are instantiated in both the test harness and the chip are uniquified. .. Note:: For VLSI projects, this ``App`` is run instead of the normal FIRRTL ``App`` to elaborate Verilog. @@ -133,5 +131,5 @@ This, unfortunately, breaks the process-agnostic RTL abstraction, so it is recom The simplest way to do this is to have a config fragment that when included updates instantiates the IO cells and connects them in the test harness. When simulating chip-specific designs, it is important to include the IO cells. The IO cell behavioral models will often assert if they are connected incorrectly, which is a useful runtime check. -They also keep the IO interface at the chip and test harness boundary (see :ref:`Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route, +They also keep the IO interface at the chip and test harness boundary (see :ref:`Tools/Barstools:Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route, which allows the RTL simulation test harness to be reused. diff --git a/docs/Tools/Chisel-Testers.rst b/docs/Tools/Chisel-Testers.rst index 2ed84ed9..9570dd61 100644 --- a/docs/Tools/Chisel-Testers.rst +++ b/docs/Tools/Chisel-Testers.rst @@ -4,4 +4,4 @@ Chisel Testers `Chisel Testers `__ is a library for writing tests for Chisel designs. It provides a Scala API for interacting with a DUT. It can use multiple backends, including things such as Treadle and Verilator. -See :ref:`Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods. +See :ref:`Tools/Treadle:Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods. diff --git a/docs/Tools/Chisel.rst b/docs/Tools/Chisel.rst index 1604fd36..3982e47b 100644 --- a/docs/Tools/Chisel.rst +++ b/docs/Tools/Chisel.rst @@ -13,7 +13,7 @@ The Chisel generator starts elaboration using the module and configuration class This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code. If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library". However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral! -See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog. +See :ref:`Tools/FIRRTL:FIRRTL` for more information on how to get a FIRRTL file to Verilog. For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp `__. Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website `__. diff --git a/docs/Tools/Dromajo.rst b/docs/Tools/Dromajo.rst index 2266bac1..6c25df78 100644 --- a/docs/Tools/Dromajo.rst +++ b/docs/Tools/Dromajo.rst @@ -19,4 +19,4 @@ An example of a divergence and Dromajo's printout is shown below. Dromajo shows the divergence compared to simulation (PC, inst, inst-bits, write data, etc) and also provides the register state on failure. It is useful to catch bugs that affect architectural state before a simulation hangs or crashes. -To use Dromajo with BOOM, refer to :ref:`Debugging RTL` section on Dromajo. +To use Dromajo with BOOM, refer to :ref:`Advanced-Concepts/Debugging-RTL:Debugging RTL` section on Dromajo. diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index fbe966a6..d47e703c 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -40,7 +40,7 @@ Setting up the Hammer Configuration Files -------------------------------------------- The first configuration file that needs to be set up is the Hammer environment configuration file ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you only need to fill in the paths for the tools that you will be using. -If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`Advanced Environment Setup` segment of this documentation page. +If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`VLSI/Basic-Flow:Advanced Environment Setup` segment of this documentation page. Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``nangate45`` OpenRoad example), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design. @@ -63,7 +63,7 @@ We will do so by calling ``make buildfile`` with appropriate Chipyard configurat As in the rest of the Chipyard flows, we specify our SoC configuration using the ``CONFIG`` make variable. However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module. Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on. -The makefile will automatically call tools such as Barstools and the MacroCopmiler (:ref:`barstools`) in order to make the generated Verilog more VLSI friendly. +The makefile will automatically call tools such as Barstools and the MacroCopmiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly. By default, the MacroCopmiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are wokring with a new process technology are prefer to work with flipflop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, the ASAP7 process technology does not have associated SRAMs, and therefore the ASAP7 Hammer tutorial (:ref:`tutorial`) uses the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. @@ -116,6 +116,7 @@ Hence, if we want to monolitically place-and-route the entire SoC with the defau In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, .. code-block:: shell + vlsi.inputs.placement_constraints: - path: "Gemmini" type: toplevel @@ -135,7 +136,7 @@ The relevant ``make`` command would then be make par CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml" Note that the width and height specification can vary widely between different modulesi and level of the module hierarchy. Make sure to set sane width and height values. -Place-and-route generally requires more fine-grained input specifications regarding power nets, clock nets, pin assignments and floorplanning. While the template configuration files provide defaults for automatic tool defaults, these will usually result in very bad QoR, and therefore it is recommended to specify better-informed floorplans, pin assignments and power nets. For more information about cutomizing theses parameters, please refer to the :ref:`Customizing Your VLSI Flow in Hammer` sections or to the Hammer documentation. +Place-and-route generally requires more fine-grained input specifications regarding power nets, clock nets, pin assignments and floorplanning. While the template configuration files provide defaults for automatic tool defaults, these will usually result in very bad QoR, and therefore it is recommended to specify better-informed floorplans, pin assignments and power nets. For more information about cutomizing theses parameters, please refer to the :ref:`VLSI/Basic-Flow:Customizing Your VLSI Flow in Hammer` sections or to the Hammer documentation. Additionally, some Hammer process technology plugins do not provide sufficient default values for requires settings such as power nets and pin assignments (for example, ASAP7). In those cases, these constraints will need to be specified manually in the top-level configuration yml files, as is the case in the ``example-asap7.yml`` configuration file. Place-and-route tools are very sensitive to process technologes (significantly more sensitive than synthesis tools), and different process technologies may work only on specific tool versions. It is recommended to check what is the appropriate tool version for the specific process technology you are working with. diff --git a/docs/VLSI/Building-A-Chip.rst b/docs/VLSI/Building-A-Chip.rst index 9ce283eb..3cd6273e 100644 --- a/docs/VLSI/Building-A-Chip.rst +++ b/docs/VLSI/Building-A-Chip.rst @@ -10,7 +10,7 @@ Transforming the RTL -------------------- Building a chip requires specializing the generic verilog emitted by FIRRTL to adhere to the constraints imposed by the technology used for fabrication. -This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Barstools`. +This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Tools/Barstools:Barstools`. In addition to these required transformations, it may also be beneficial to transform the RTL to make it more amenable to hierarchical physical design easier. This often includes modifying the logical hierarchy to match the physical hierarchy through grouping components together or flattening components into a single larger module. @@ -49,6 +49,6 @@ Running the VLSI tool flow -------------------------- For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. -For an example of how to use the VLSI in the context of Chipyard, see :ref:`ASAP7 Tutorial`. +For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/Tutorial:ASAP7 Tutorial`. diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 7e44ebb7..27e3a039 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -77,7 +77,7 @@ Pull the Hammer environment into the shell: source $HAMMER_HOME/sourceme.sh Building the Design -------------------- +-------------------- To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow: .. code-block:: shell diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 0f5d32d5..56e807e8 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -10,5 +10,6 @@ In particular, we aim to support the Hammer physical design generator flow. Building-A-Chip Hammer + Basic-Flow Tutorial Advanced-Usage diff --git a/docs/conf.py b/docs/conf.py index e0accb5e..f78001c8 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -190,3 +190,6 @@ texinfo_documents = [ intersphinx_mapping = {'python' : ('https://docs.python.org/', None), 'boom' : ('https://docs.boom-core.org/en/latest/', None), 'firesim' : ('http://docs.fires.im/en/latest/', None) } + +# resolve label conflict between documents +autosectionlabel_prefix_document = True diff --git a/docs/index.rst b/docs/index.rst index d776b353..58d29241 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -11,7 +11,7 @@ Welcome to Chipyard's documentation! Chipyard is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. -.. IMPORTANT:: **New to Chipyard?** Jump to the :ref:`Initial Repository Setup` page for setup instructions. +.. IMPORTANT:: **New to Chipyard?** Jump to the :ref:`Chipyard-Basics/Initial-Repo-Setup:Initial Repository Setup` page for setup instructions. Getting Help ------------ From d12c5f1923678d3984bd339c569c5ff4ba0b36ee Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 8 Jan 2021 20:18:52 -0800 Subject: [PATCH 444/457] resolve docs merge conflict --- docs/Chipyard-Basics/Chipyard-Components.rst | 4 ++-- docs/Prototyping/General.rst | 4 ++-- docs/Prototyping/VCU118.rst | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 5d9633d5..126766c4 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -130,8 +130,8 @@ Prototyping **FPGA Prototyping** FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards. - For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. - See :ref:`Prototyping Flow` for more information on FPGA prototypes. + For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim` platform. + See :ref:`Prototyping/index:Prototyping Flow` for more information on FPGA prototypes. VLSI ------------------------------------------- diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index 0221b82b..89c0b512 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -18,7 +18,7 @@ Generating a Bitstream ---------------------- Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation. -Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: +Similar to a software RTL simulation (:ref:`Simulation/Software-RTL-Simulation:Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: .. code-block:: shell @@ -67,4 +67,4 @@ For example, running the bitstream build for an added ILA for a BOOM config.: make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream -.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. +.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim` platform. diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 6d759f82..7f8f2cb9 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -45,7 +45,7 @@ For ease of use, you can change the ``FPGAFrequencyKey`` to change the default c After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). -For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. +For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`. Introduction to the Bringup Platform ------------------------------------ @@ -57,4 +57,4 @@ The TSI Host Widget is used to interact with the DUT from the prototype over a S .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. - See :ref:`Generating a Bitstream` for information on the various make variables. + See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables. From 06cee8fa42d0a56f2cf713d0c56762d658c972e8 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 9 Jan 2021 00:39:01 -0800 Subject: [PATCH 445/457] add hierarchical --- docs/VLSI/Basic-Flow.rst | 83 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 4 deletions(-) diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index d47e703c..27178a54 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -218,14 +218,89 @@ If you have access to a shared LSF cluster and you would like Hammer to submit i settings_meta: "append" -Specifying a Custom Floorplan -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - Composing a Hierarchical Design ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +For large designs, a monolithic VLSI flow may take the EDA tools a very long time to process and optimize, to the extent that it may not be feasable sometimes. +Hammer supports a hierarchical physical design flow, which decomposes the design into several specified sub-components and runs the flow on each sub-components separetly. Hammer is then able to assemble these blocks together into a top-level design. This hierarchical approach speeds up the VLSI flow for large designs, especially designs in which there may me multiple instantiations of the same sub-components(since the sub-component can simply be replicated in the layout). +While hierarchical physical design can be performed in multiple ways (top-down, bottom-up, abutment etc.), Hammer currently supports only the bottom-up approach. +The bottom-up approach traverses a tree representing the hierarchy starting from the leaves and towards the direction of the root (the "top level"), and runs the physical design flow on each node of the hierarchy tree using the previously layed-out children nodes. +As nodes get closer to the root (or "top level") of the hierarchy, largers sections of the design get layed-out. + +The Hammer hierarchical flow relies on a manually-specified descrition of the desired heirarchy tree. The specification of the heirarchy tree is defined based on the instance names in the generated Verilog, which sometime make this specification challenging due to inconsisent instance names. Additionally, the specification of the heirarchy tree is intertwined with the manual specification of a floorplan for the design. + +For example, if we choose to specifiy the previously mentioned ``GemminiRocketConfig`` configuration in a hierarchical fashion in which the Gemmini accelerator and the last-level cache are run separetly from the top-level SoC, we would replace the floorplan example in ``example-design.yml`` from the :ref:`VLSI/Basic-Flow:Place-and-Route` section with the following specification: + +.. code-block:: shell + + vlsi.inputs.hiearchical.top_module: "ChipTop" + vlsi.inputs.hierarchical.mode: manual" + vlsi.inputs.manual_modules: + - ChipTop: + - RocketTile + - InclusiveCache + - RocketTile: + - Gemmini + vlsi.manual_placement_constraints: + - ChipTop + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + width: 500 + height: 500 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + - RocketTile + - path: "chiptop.system.tile_prci_domain.tile" + type: hierarchical + master: ChipTop + x: 0 + y: 0 + width: 250 + height: 250 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + - Gemmini + - path: "chiptop.system.tile_prci_domain.tile.gemmini" + type: hierarchical + master: RocketTile + x: 0 + y: 0 + width: 200 + height: 200 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + - InclusiveCache + - path: "chiptop.system.subsystem_l2_wrapper.l2" + type: hierarchical + master: ChipTop + x: 0 + y: 0 + width: 100 + height: 100 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + + +In this specification, ``vlsi.inputs.hierarchical.mode`` indicates the manual specification of the heirarchy tree (which is the only mode currently supported by Hammer), ``vlsi.inputs.hiearchical.top_module`` sets the root of the hierarchical tree, ``vlsi.inputs.hierarchical.manual_modules`` enumerates the tree of hierarchical modules, and ``vlsi.inputs.hierarchical.manual_placement_constraints`` enumerates the floorplan for each module. + + +.. Specifying a Custom Floorplan +.. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Customizing Generated Tcl Scripts From b1b230ba01fca4ae144cd9e7d8ed1194a2ec4ef3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 10 Jan 2021 23:38:11 -0800 Subject: [PATCH 446/457] Fix ICache SPAD base addr to avoid conflicts with default SerialTL mem --- generators/chipyard/src/main/scala/ConfigFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index c5c85e47..d25b4aac 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -141,7 +141,7 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { class WithRocketICacheScratchpad extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey, site) map { r => - r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000)))) + r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000)))) } }) From 4156bd85131c23d0cd377a1e4b0b63012a948b52 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 10 Jan 2021 23:39:16 -0800 Subject: [PATCH 447/457] Bump testchipip and sodor | increase sodor SerialTL width for faster binary loading --- .../chipyard/src/main/scala/config/SodorConfigs.scala | 6 ++++++ generators/riscv-sodor | 2 +- generators/testchipip | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 998ccff9..3679ed07 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -16,6 +17,7 @@ class Sodor1StageConfig extends Config( class Sodor2StageConfig extends Config( // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -25,6 +27,7 @@ class Sodor2StageConfig extends Config( class Sodor3StageConfig extends Config( // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -34,6 +37,7 @@ class Sodor3StageConfig extends Config( class Sodor3StageSinglePortConfig extends Config( // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -43,6 +47,7 @@ class Sodor3StageSinglePortConfig extends Config( class Sodor5StageConfig extends Config( // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -52,6 +57,7 @@ class Sodor5StageConfig extends Config( class SodorUCodeConfig extends Config( // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 8fc51640..449354c2 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485 +Subproject commit 449354c27bf07ccc865dc6c005df1d08eaf5b01c diff --git a/generators/testchipip b/generators/testchipip index ca67a843..a62ef167 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ca67a843bd8f568e205981380c11d321d1bad677 +Subproject commit a62ef167bcd48e6d9f9f6aabc4db63ac701ad522 From e1ea3561c1b11722cbd9c667ea70e0142a0b1df1 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Tue, 12 Jan 2021 18:36:20 -0500 Subject: [PATCH 448/457] Bump firemarshal to v1.11.0 --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index 199f23ed..aa8e6aa8 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 199f23ed74f723313b3bf225a9b4cfed8b6f6399 +Subproject commit aa8e6aa8714d46b74917ebaa91333f5727e34599 From c481dc2ee84e588820e71a4157b7c42a443112d2 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Tue, 12 Jan 2021 22:53:35 -0800 Subject: [PATCH 449/457] Add 16-core LargeBOOM config to firechip * Fix Jerry's comment on accidentally mixing multiple BOOM configs --- .../firechip/src/main/scala/TargetConfigs.scala | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index b70ef647..bece1896 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -200,3 +200,14 @@ class FireSimMulticlockRocketConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.DividedClockRocketConfig) +//********************************************************************************** +// System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations +// - Requires MTModels and MCRams mixins as prefixes to the platform config +// - May require larger build instances or JVM memory footprints +//*********************************************************************************/ +class FireSim16LargeBoomConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new boom.common.WithNLargeBooms(16) ++ + new chipyard.config.AbstractConfig) From 10dbf68667a0a472c9bf87c4fdef20691067f542 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Wed, 13 Jan 2021 19:21:30 +0000 Subject: [PATCH 450/457] bump prebuilt toolchain --- toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt b/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt index 543ff124..918be237 160000 --- a/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt +++ b/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt @@ -1 +1 @@ -Subproject commit 543ff1245e1c2071ea9d0252a622c9cece88b7f5 +Subproject commit 918be2371723257ed6590c77d5996ed040261c85 From 36fe69020410931dd4874678e0de8b0b158d952b Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 14 Jan 2021 13:09:13 -0800 Subject: [PATCH 451/457] scripts: Ensure git config changes are reverted on failure Fixes #595 --- scripts/init-fpga.sh | 2 +- .../init-submodules-no-riscv-tools-nolog.sh | 67 +++++++++---------- 2 files changed, 33 insertions(+), 36 deletions(-) diff --git a/scripts/init-fpga.sh b/scripts/init-fpga.sh index 08203259..a0ab8ef6 100755 --- a/scripts/init-fpga.sh +++ b/scripts/init-fpga.sh @@ -4,7 +4,7 @@ set -e set -o pipefail # Enable submodule update for FPGA tools. -git config --unset submodule.fpga/fpga-shells.update +git config --unset submodule.fpga/fpga-shells.update || : # Initialize local FPGA tools. git submodule update --init --recursive fpga/fpga-shells # Disable submodule update for FPGA tools. diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 601d641a..0039d9df 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -20,43 +20,41 @@ fi DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")" CHIPYARD_DIR="$(dirname "$DIR")" -# Ignore toolchain submodules cd "$CHIPYARD_DIR" -for name in toolchains/*-tools/*/ ; do - git config submodule."${name%/}".update none -done -git config submodule.toolchains/libgloss.update none -git config submodule.toolchains/qemu.update none -# Don't automatically initialize generators with big submodules (e.g. linux source) -git config submodule.generators/sha3.update none -git config submodule.generators/gemmini.update none +( + # Blocklist of submodules to initially skip: + # - Toolchain submodules + # - Generators with huge submodules (e.g., linux sources) + # - FireSim until explicitly requested + # - Hammer tool plugins + git_submodule_exclude() { + # Call the given subcommand (shell function) on each submodule + # path to temporarily exclude during the recursive update + for name in \ + toolchains/*-tools/*/ \ + toolchains/libgloss \ + toolchains/qemu \ + generators/sha3 \ + generators/gemmini \ + sims/firesim \ + vlsi/hammer-cadence-plugins \ + vlsi/hammer-synopsys-plugins \ + vlsi/hammer-mentor-plugins \ + software/firemarshal \ + fpga/fpga-shells + do + "$1" "${name%/}" + done + } -# Disable updates to the FireSim submodule until explicitly requested -git config submodule.sims/firesim.update none -# Disable updates to the hammer tool plugins repos -git config submodule.vlsi/hammer-cadence-plugins.update none -git config submodule.vlsi/hammer-synopsys-plugins.update none -git config submodule.vlsi/hammer-mentor-plugins.update none -git config submodule.software/firemarshal.update none -# Disable update to fpga-shells -git config submodule.fpga/fpga-shells.update none -git submodule update --init --recursive #--jobs 8 + _skip() { git config --local "submodule.${1}.update" none ; } + _unskip() { git config --local --unset-all "submodule.${1}.update" || : ; } -# Un-ignore toolchain submodules -for name in toolchains/*-tools/*/ ; do - git config --unset submodule."${name%/}".update -done -git config --unset submodule.toolchains/libgloss.update -git config --unset submodule.toolchains/qemu.update - -git config --unset submodule.vlsi/hammer-cadence-plugins.update -git config --unset submodule.vlsi/hammer-synopsys-plugins.update -git config --unset submodule.vlsi/hammer-mentor-plugins.update - -git config --unset submodule.generators/sha3.update -git config --unset submodule.generators/gemmini.update -git config --unset submodule.software/firemarshal.update + trap 'git_submodule_exclude _unskip' EXIT INT TERM + git_submodule_exclude _skip + git submodule update --init --recursive #--jobs 8 +) # Non-recursive clone to exclude riscv-linux git submodule update --init generators/sha3 @@ -65,10 +63,9 @@ git submodule update --init generators/sha3 git submodule update --init generators/gemmini git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests -git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim -git config submodule.sims/firesim.update none +git config --local submodule.sims/firesim.update none # Only shallow clone needed for basic SW tests git submodule update --init software/firemarshal From 5a534391c9073ad00f9254b58dde7cbbfee2eeba Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 18 Jan 2021 15:06:14 -0800 Subject: [PATCH 452/457] Bump Firesim for release --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index f1dafa1b..72a52523 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f1dafa1bae05b8e4d752843ab489fd85e6df75bc +Subproject commit 72a52523e18443d9ef9a1e2664cbc71a45fc0c57 From 72038b62ccb992ff62076ef3aa8404d49a12839d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 18 Jan 2021 16:35:01 -0800 Subject: [PATCH 453/457] Add new DAC paper link --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 0283da58..b3d48b40 100644 --- a/README.md +++ b/README.md @@ -47,6 +47,10 @@ If used for research, please cite Chipyard by the following publication: } ``` +* **Chipyard** + * A. Amid, et al. *IEEE Micro'20* [PDF](https://ieeexplore.ieee.org/document/9099108). + * A. Amid, et al. *DAC'20* [PDF](https://ieeexplore.ieee.org/document/9218756). + These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. * **Generators** From 1dcfa5aa41cd7ad55dcc7a8ebf0fad79c3dc6306 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 18 Jan 2021 16:35:31 -0800 Subject: [PATCH 454/457] Update AXI4Fragmenter docs --- docs/TileLink-Diplomacy-Reference/Widgets.rst | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/docs/TileLink-Diplomacy-Reference/Widgets.rst b/docs/TileLink-Diplomacy-Reference/Widgets.rst index 12086778..4a4bce7d 100644 --- a/docs/TileLink-Diplomacy-Reference/Widgets.rst +++ b/docs/TileLink-Diplomacy-Reference/Widgets.rst @@ -200,10 +200,11 @@ transactions. AXI4Fragmenter -------------- -The AXI4Fragmenter is similar to the :ref:`TileLink-Diplomacy-Reference/Widgets:TLFragmenter`, except it can only -break multi-beat AXI4 transactions into single-beat transactions. This -effectively serves as an AXI4 to AXI4-Lite converter. The constructor for this -widget does not take any arguments. +The AXI4Fragmenter is similar to the :ref:`TileLink-Diplomacy-Reference/Widgets:TLFragmenter`. +The AXI4Fragmenter slices all AXI accesses into simple power-of-two sized and aligned transfers +of the largest size supported by the manager. This makes it suitable as a first stage transformation +to apply before an AXI4=>TL bridge. It also makes it suitable for placing after TL=>AXI4 bridge +driving an AXI-lite slave. **Example Usage:** From 3bb0870b5414c165380de6c20806102d717c32c1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 18 Jan 2021 16:58:38 -0800 Subject: [PATCH 455/457] [ci skip] Fix SonicBOOM citation --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index b3d48b40..1263bf37 100644 --- a/README.md +++ b/README.md @@ -56,7 +56,7 @@ These additional publications cover many of the internal components used in Chip * **Generators** * **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf). * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://www.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf). - * **SonicBOOM (BOOMv3): J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf). + * **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf). * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf). * **Gemmini**: H. Genc, et al., *arXiv*. [PDF](https://arxiv.org/pdf/1911.09925). * **Sims** From 429a32befed110f778e5cf157e8b33b9353dc28c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Jan 2021 19:47:43 -0800 Subject: [PATCH 456/457] Update CHANGELOG for 1.4.0 release --- CHANGELOG.md | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7d06eda8..78b527ac 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,65 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.4.0] - 2021-01-19 + +A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/599 + +### Added +* OpenSBI Support (#633) +* Support for Diplomacy-based clocking (#614, #682) +* Support for Diplomacy-based IOBinders (#699) +* Sodor core integration (#648) +* Simple Divider-Only PLL for Multiclock RTL Simulation (#676) +* Enable parallel Hammer simulations (#600) +* OpenRoad nangate45 Hammer backend (#608) +* Add support for "LBWIF" backing memory through serialized TileLink (#673) +* Add variable to control FIRRTL logging verbosity (#627) +* Add RANDOM_SEED variable to set random init for VCS and Verilator simulations (#629) +* Fast LoadMem support (#635) +* Multithreaded Verilator (#654) +* Support for custom Verilator optimization flags (#728) +* Add config-fragment to use broadcast manager instead of L2 for coherence (#721) +* Added optional ignore QEMU flag to `build-toolchains.sh` (#709) +* Split `JAVA_ARGS` into `JAVA_OPTS` and `SBT_OPTS` (#719) +* Experimental support for SBT thin client. Enable with `export ENABLE_SBT_THIN_CLIENT=1` (https://github.com/sbt/sbt/pull/5620) (#719) +* Helper `make` targets to launch SBT console (`sbt`) and shutdown/start thin server (-sbt-server) (#719) +* Allow users to override `CC` and `CXX` for `build-toolchains.sh` (#739) +* Support VCU118/Arty local FPGA prototypes through `fpga-shells` (#747) +* To highlight the resource-optimizing platform configurations added to FireSim in firesim/firesim#636, a 16-core LargeBOOM configuration has been added to FireChip (#756) + +### Changed +* Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges (#670, #674) +* Have FireSim build recipes use Chipyard configs rather than FireChip configs (#695) +* FireMarshal boot default to OpenSBI rather than BBL (#633) +* Override default baud rate for FireChip (#625) +* DTM only supports HTIF in DMI mode (#672) +* Unify HTIF implementation between Chipyard and Firesim (#683) +* Update to Chisel 3.4.1.x (and other bumps) (#742, #719, #751) +* Renamed Ariane to CVA6 (#710) +* `build.sbt` refactoring/fixes for RC/Chisel/Firrtl bump (#719) +* Bump to SBT 1.4.4 (#719) +* Use `; x; y; z;` syntax to run multiple SBT commands (#719) +* CI Improvements: Cleanup `check-commit` printout. Don't transfer `.git` folders. (#750) + +### Fixed +* Multi-SHA3 configs (#597) +* Allow dramsim_ini folder to be set at the command line (#598) +* Emit HTIF Node in device tree (#607) +* Fixes for AXI4 MMIO and FBus ports (#618) +* Only punch realistic subset of DebugIO through chiptop | default to JTAG+Serial (#664) +* IceNet bug fixes (#720) +* smartelf2hex.sh bug fixes (#677, #693) +* env.sh zsh compatibility (#705) +* build-toolchains.sh bug fixes (#745 #739) +* Bump Dromajo to work with older version of glibc (#709) + +### Removed +* Support for synchronous ChipTop reset (#703) +* Split `JAVA_ARGS` into `JAVA_OPTS` and `SBT_OPTS` (#719) +* Removed bloop support (#719) + + ## [1.3.0] - 2020-05-31 A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/500 From cc580488e4f70b007c99421f00802b6007e3ec14 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Jan 2021 22:24:28 -0800 Subject: [PATCH 457/457] Update CHANGELOG --- CHANGELOG.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 78b527ac..749c925b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -27,19 +27,22 @@ A more detailed account of everything included is included in the dev to master * Helper `make` targets to launch SBT console (`sbt`) and shutdown/start thin server (-sbt-server) (#719) * Allow users to override `CC` and `CXX` for `build-toolchains.sh` (#739) * Support VCU118/Arty local FPGA prototypes through `fpga-shells` (#747) -* To highlight the resource-optimizing platform configurations added to FireSim in firesim/firesim#636, a 16-core LargeBOOM configuration has been added to FireChip (#756) +* A 16-core LargeBOOM configuration has been added to FireChip to highlight the resource-optimizing platform configurations added to FireSim in firesim/firesim#636 (#756) ### Changed +* Bump Chisel to 3.4.1.x (#742, #719, #751) +* Bump RocketChip to a7b016e (#742, #719) +* Bump FireSim to 1.11 +* Bump Gemmini to v0.5 +* Bump to SBT 1.4.4 (#719) * Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges (#670, #674) * Have FireSim build recipes use Chipyard configs rather than FireChip configs (#695) * FireMarshal boot default to OpenSBI rather than BBL (#633) * Override default baud rate for FireChip (#625) * DTM only supports HTIF in DMI mode (#672) * Unify HTIF implementation between Chipyard and Firesim (#683) -* Update to Chisel 3.4.1.x (and other bumps) (#742, #719, #751) * Renamed Ariane to CVA6 (#710) * `build.sbt` refactoring/fixes for RC/Chisel/Firrtl bump (#719) -* Bump to SBT 1.4.4 (#719) * Use `; x; y; z;` syntax to run multiple SBT commands (#719) * CI Improvements: Cleanup `check-commit` printout. Don't transfer `.git` folders. (#750) @@ -58,7 +61,6 @@ A more detailed account of everything included is included in the dev to master ### Removed * Support for synchronous ChipTop reset (#703) * Split `JAVA_ARGS` into `JAVA_OPTS` and `SBT_OPTS` (#719) -* Removed bloop support (#719) ## [1.3.0] - 2020-05-31