From 5bfc289677fcff16c19a71c6b79006a0c31b09c7 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 5 Aug 2020 09:55:31 -0700 Subject: [PATCH] Bump fesvr for better loadmem impl. Fix verilator loadmem support --- .../utilities/src/main/resources/csrc/emulator.cc | 10 ++-------- toolchains/esp-tools/riscv-isa-sim | 2 +- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 0a3b46da..27a8aa4a 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -116,7 +116,6 @@ int main(int argc, char** argv) FILE * vcdfile = NULL; uint64_t start = 0; #endif - char ** htif_argv = NULL; int verilog_plusargs_legal = 1; opterr = 1; @@ -252,10 +251,6 @@ done_processing: usage(argv[0]); return 1; } - int htif_argc = 1 + argc - optind; - htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); - htif_argv[0] = argv[0]; - for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -278,8 +273,8 @@ done_processing: #endif jtag = new remote_bitbang_t(rbb_port); - dtm = new dtm_t(htif_argc, htif_argv); - tsi = new tsi_t(htif_argc, htif_argv); + dtm = new dtm_t(argc, argv); + tsi = new tsi_t(argc, argv); signal(SIGTERM, handle_sigterm); @@ -364,6 +359,5 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) free(htif_argv); return ret; } diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 13384cac..2bc65d1b 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 13384cac1e54828200067ff890f564a505a4ebb3 +Subproject commit 2bc65d1bf6605077e3740941c086724beb35db05