From 5db66116286254dff359f798b9a20c62353a30cf Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 6 Mar 2024 00:02:42 -0800 Subject: [PATCH] FIX: Update UART FIFO depth --- generators/firechip/src/main/scala/TargetConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 7a6d1e66..5b3fef0a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -136,7 +136,7 @@ class WithFireSimHighPerfClocking extends Config( // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz class WithFireSimConfigTweaks extends Config( - new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // FireSim requires a larger UART FIFO buffer, + new chipyard.config.WithUART(txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer, new chipyard.config.WithNoUART() ++ // so we overwrite the default one // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)