From 5e893ea77c3a6698b700d8e38d5eecf3d309d878 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:16:38 -0700 Subject: [PATCH] Add prefetching rocket example config --- build.sbt | 7 ++++++- .../src/main/scala/config/RocketConfigs.scala | 8 ++++++++ .../scala/config/fragments/TileFragments.scala | 17 +++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 6f72940a..0fbdd747 100644 --- a/build.sbt +++ b/build.sbt @@ -153,7 +153,7 @@ lazy val chipyard = (project in file("generators/chipyard")) sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, barf) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -168,6 +168,11 @@ lazy val mempress = (project in file("generators/mempress")) .settings(chiselTestSettings) .settings(commonSettings) +lazy val barf = (project in file("generators/bar-fetchers")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val constellation = (project in file("generators/constellation")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 21b630cc..f71b6ea7 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -126,3 +126,11 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.example.WithCustomIOCells ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) + +class PrefetchingRocketConfig extends Config( + new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher into L1D$ + new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher into L2 for L1I$ accesses + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher into L2 for L1D$ accesses + new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 56042c3d..17eaa3f0 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -9,7 +9,10 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import boom.common.{BoomTileAttachParams} import cva6.{CVA6TileAttachParams} +import sodor.common.{SodorTileAttachParams} +import ibex.{IbexTileAttachParams} import testchipip._ +import barf.{TilePrefetchingMasterPortParams} class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { @@ -79,3 +82,17 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) +class WithTilePrefetchers extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + } +})