diff --git a/.circleci/config.yml b/.circleci/config.yml index 7dcbc809..9c6e9f80 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -308,6 +308,7 @@ jobs: tools-version: "esp-tools" group-key: "group-accels" project-key: "chipyard-hwacha" + timeout: "30m" chipyard-gemmini-run-tests: executor: main-env steps: diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 419071bc..4ea31df5 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -130,7 +130,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ val harnessMultiClockAXIRAM = withClockAndReset(th.harnessClock, th.harnessReset) { SerialAdapter.connectHarnessMultiClockAXIRAM( system.serdesser.get, - port, + serial_bits, axiClockBundle, th.harnessReset) } diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 04920acc..43fea874 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -95,7 +95,7 @@ class WithFireSimDefaultFrequencyTweaks extends Config( // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing ++ + new testchipip.WithAsynchronousSerialSlaveCrossing ) // Tweaks that are generally applied to all firesim configs diff --git a/generators/testchipip b/generators/testchipip index ef59e54c..1d2ac9c1 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ef59e54c42eb990036f13378dea5900713154228 +Subproject commit 1d2ac9c13bd1d4c053bbf9c7d57436f0113c39fd