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Address PR comments for Ibex [ci skip]

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Ella Schwarz
2021-09-17 23:09:36 -07:00
parent 2a050f2be8
commit 5ffc100323
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docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -25,7 +25,7 @@ Processor Cores
See :ref:`Generators/CVA6:CVA6 Core` for more information.
**Ibex Core**
An in-order RISC-V core writeen in System Verilog.
An in-order 32 bit RISC-V core written in System Verilog.
See :ref:`Generators/Ibex:Ibex Core` for more information.
Accelerators

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docs/Generators/Ibex.rst
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Ibex Core
====================================
`Ibex <https://github.com/lowRISC/ibex>`__ is a parameterizable RV32 embedded core written in SystemVerilog, currently maintained by lowRISC.
`Ibex <https://github.com/lowRISC/ibex>`__ is a parameterizable RV32IMC embedded core written in SystemVerilog, currently maintained by `lowRISC <https://lowrisc.org>`__.
The `Ibex core` is wrapped in an `Ibex tile` so it can be used with the `Rocket Chip SoC generator`.
The core exposes a custom memory interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
.. Warning:: The Ibex mtvec register is 256 byte aligned. When writing/running tests, ensure that the trap vector is also 256 byte aligned.
.. Warning:: The Ibex reset vector is located at 0x80.
.. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80.
While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
For more information, see the `GitHub repository <https://github.com/lowRISC/ibex>`__.
For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.