diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 62ccf684..ecb666d1 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -94,7 +94,7 @@ memory channel. Instead of connecting to off-chip DRAM, you can instead connect a scratchpad and remove the off-chip link. This is done by adding a fragment like -``testchipip.WithScratchpad`` to your configuration and removing the +``testchipip.soc.WithScratchpad`` to your configuration and removing the memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``. .. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala diff --git a/fpga/bootrom.rv32.img b/fpga/bootrom.rv32.img new file mode 100755 index 00000000..fbab5033 Binary files /dev/null and b/fpga/bootrom.rv32.img differ diff --git a/fpga/bootrom.rv64.img b/fpga/bootrom.rv64.img new file mode 100755 index 00000000..8d4fea05 Binary files /dev/null and b/fpga/bootrom.rv64.img differ diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 1bf2b643..eeb26b60 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem} @@ -30,7 +30,7 @@ class WithArtyTweaks extends Config( new chipyard.config.WithFrontBusFrequency(32) ++ new chipyard.config.WithControlBusFrequency(32) ++ new chipyard.config.WithPeripheryBusFrequency(32) ++ - new testchipip.WithNoSerialTL + new testchipip.serdes.WithNoSerialTL ) class TinyRocketArtyConfig extends Config( diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 213425f5..c9892aa8 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ import sifive.fpgashells.shell.{DesignKey} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem} @@ -25,7 +25,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( new WithArty100TUARTTSI ++ new WithArty100TDDRTL ++ new WithNoDesignKey ++ - new testchipip.WithUARTTSIClient ++ + new testchipip.tsi.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++ new chipyard.config.WithMemoryBusFrequency(freqMHz) ++ @@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config( class BringupArty100TConfig extends Config( new WithArty100TSerialTLToGPIO ++ new WithArty100TTweaks(freqMHz = 50) ++ - new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++ + new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++ new chipyard.ChipBringupHostConfig) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 4c821970..dd7c1a35 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -20,8 +20,6 @@ import chipyard._ import chipyard.harness._ import chipyard.iobinders._ -import testchipip._ - class WithArty100TUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTTSIPort) => { val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala index 01b095fa..fe53b96d 100644 --- a/fpga/src/main/scala/nexysvideo/Configs.scala +++ b/fpga/src/main/scala/nexysvideo/Configs.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ import sifive.fpgashells.shell.{DesignKey} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem} @@ -26,7 +26,7 @@ class WithNexysVideoTweaks extends Config( new WithNexysVideoUARTTSI ++ new WithNexysVideoDDRTL ++ new WithNoDesignKey ++ - new testchipip.WithUARTTSIClient ++ + new testchipip.tsi.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++ new chipyard.config.WithMemoryBusFrequency(50.0) ++ @@ -53,7 +53,7 @@ class WithTinyNexysVideoTweaks extends Config( new WithNexysVideoUARTTSI ++ new WithNoDesignKey ++ new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR - new testchipip.WithUARTTSIClient ++ + new testchipip.tsi.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++ new chipyard.config.WithMemoryBusFrequency(50.0) ++ diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala index 4027cbcf..e6865eff 100644 --- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala +++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala @@ -12,8 +12,6 @@ import sifive.blocks.devices.uart.{UARTParams} import chipyard._ import chipyard.harness._ - -import testchipip._ import chipyard.iobinders._ class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({ diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index 124920d7..4842434e 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem, ExtTLMem} import chipyard.harness._ diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 32dc3c2c..3f99fdb9 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard._ import chipyard.harness._ diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 65a23a1f..0760fa72 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} -import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} +import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} import chipyard.{BuildSystem} diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 4b9604f9..a52a1b5e 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.clocks._ import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} -import testchipip.{TSIHostWidgetIO} +import testchipip.tsi.{TSIHostWidgetIO} import chipyard.fpga.vcu118.{FMCPMap} diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index c5401d32..e4efbdc7 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule} class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C - with testchipip.HasPeripheryTSIHostWidget + with testchipip.tsi.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index d60de620..c130a697 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -11,7 +11,7 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} -import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} +import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} import chipyard.harness._ import chipyard.iobinders._ diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 155f2647..24b7aa9a 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} -import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} +import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 12398d8f..94d28258 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter} +import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO} +import testchipip.util.{TLSinkSetter} import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer} diff --git a/variables.mk b/variables.mk index fcda57ef..65f493d2 100644 --- a/variables.mk +++ b/variables.mk @@ -97,7 +97,7 @@ ifeq ($(SUB_PROJECT),testchipip) VLOG_MODEL ?= $(MODEL) MODEL_PACKAGE ?= chipyard.unittest CONFIG ?= TestChipUnitTestConfig - CONFIG_PACKAGE ?= testchipip + CONFIG_PACKAGE ?= testchipip.test GENERATOR_PACKAGE ?= chipyard TB ?= TestDriver TOP ?= UnitTestSuite