wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Unify multi-node btw chipyard/firechip | unify harness clocking

Browse Source
This commit is contained in:
Jerry Zhao
2023-05-12 08:21:18 -07:00
parent 0cbca54e19
commit 607c2b5a73
31 changed files with 441 additions and 634 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/src/main/scala/arty/Configs.scala
View File

@@ -21,8 +21,12 @@ class WithArtyTweaks extends Config(
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
new WithDebugResetPassthrough ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithDTSTimebase(32768) ++
new chipyard.config.WithSystemBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
new testchipip.WithNoSerialTL
)

2
fpga/src/main/scala/arty/HarnessBinders.scala
View File

@@ -31,7 +31,7 @@ class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
ports.map {
case j: JTAGChipIO => withClockAndReset(th.buildtopClock, th.hReset) {
case j: JTAGChipIO => {
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := j.TDO
jtag_wire.TDO.driven := true.B

29
fpga/src/main/scala/arty/TestHarness.scala
View File

@@ -8,13 +8,10 @@ import org.chipsalliance.cde.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.harness.{ApplyHarnessBinders, BuildTop, HasHarnessSignalReferences}
import chipyard.harness.{HasHarnessInstantiators}
import chipyard.iobinders.{HasIOBinders}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset())
hReset := ~ck_rst
@@ -22,24 +19,10 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
val dReset = Wire(AsyncReset())
dReset := reset_core.asAsyncReset
// default to 32MHz clock
withClockAndReset(clock_32MHz, hReset) {
val dut = Module(lazyDut.module)
}
def success = {require(false, "Success not supported"); false.B }
val buildtopClock = clock_32MHz
val buildtopReset = hReset
val success = false.B
def implicitClock = clock_32MHz
def implicitReset = hReset
val dutReset = dReset
// must be after HasHarnessSignalReferences assignments
lazyDut match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
implicitHarnessClockBundle.clock := buildtopClock
implicitHarnessClockBundle.reset := buildtopReset
harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
instantiateChipTops()
}

8
fpga/src/main/scala/arty100t/Configs.scala
View File

@@ -26,6 +26,12 @@ class WithArty100TTweaks extends Config(
new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++
new WithNoDesignKey ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
@@ -34,8 +40,6 @@ class WithArty100TTweaks extends Config(
class RocketArty100TConfig extends Config(
new WithArty100TTweaks ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.RocketConfig)

56
fpga/src/main/scala/arty100t/Harness.scala
View File

@@ -4,8 +4,9 @@ import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.subsystem.{SystemBusKey}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.shell._
@@ -14,21 +15,21 @@ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.blocks.devices.uart._
import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem}
import chipyard._
import chipyard.harness._
import chipyard.iobinders.{HasIOBinders}
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences
{
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
def dp = designParameters
val chiptop = LazyModule(p(BuildTop)(p))
require(dp(MultiChipNChips) == 0, "Arty100T harness does not support multi-chip")
val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
val harnessSysPLL = dp(PLLFactoryKey)
val harnessSysPLLNode = harnessSysPLL()
println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
println(s"Arty100T FPGA Base Clock Freq: ${dutFreqMHz} MHz")
val dutWrangler = LazyModule(new ResetWrangler())
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
@@ -39,12 +40,10 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
val ddrInParams = chiptop match { case td: ChipTop =>
td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
lsys.memTLNode.edges.in(0)
}
}
val ddrClient = TLClientNode(Seq(ddrInParams.master))
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
sourceId = IdRange(0, 64)
)))))
val ddrBlockDuringReset = LazyModule(new TLBlockDuringReset(4))
ddrOverlay.overlayOutput.ddr := ddrBlockDuringReset.node := ddrClient
@@ -53,17 +52,16 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
val status_leds = all_leds.take(3)
val other_leds = all_leds.drop(3)
def buildtopClock = dutClock.in.head._1.clock
def buildtopReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }
InModuleBody {
override lazy val module = new HarnessLikeImpl
class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
// Blink the status LEDs for sanity
withClock(clk_100mhz) {
withClockAndReset(clk_100mhz, dutClock.in.head._1.reset) {
val period = (BigInt(100) << 20) / status_leds.size
val counter = RegInit(0.U(log2Ceil(period).W))
val on = RegInit(0.U(log2Ceil(status_leds.size).W))
@@ -78,21 +76,17 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
ddrOverlay.mig.module.clock := buildtopClock
ddrOverlay.mig.module.reset := buildtopReset
ddrBlockDuringReset.module.clock := buildtopClock
ddrBlockDuringReset.module.reset := buildtopReset || !ddrOverlay.mig.module.io.port.init_calib_complete
def implicitClock = dutClock.in.head._1.clock
def implicitReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }
ddrOverlay.mig.module.clock := harnessBinderClock
ddrOverlay.mig.module.reset := harnessBinderReset
ddrBlockDuringReset.module.clock := harnessBinderClock
ddrBlockDuringReset.module.reset := harnessBinderReset.asBool || !ddrOverlay.mig.module.io.port.init_calib_complete
other_leds(6) := ddrOverlay.mig.module.io.port.init_calib_complete
chiptop match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
implicitHarnessClockBundle.clock := buildtopClock
implicitHarnessClockBundle.reset := buildtopReset
harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
instantiateChipTops()
}
}

39
fpga/src/main/scala/arty100t/HarnessBinders.scala
View File

@@ -6,6 +6,7 @@ import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
@@ -20,39 +21,37 @@ import chipyard.iobinders.JTAGChipIO
import testchipip._
class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
(system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val ath = th.asInstanceOf[Arty100THarness]
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val freq = p(PeripheryBusKey).dtsFrequency.get
val bits = port.bits
port.clock := th.buildtopClock
withClockAndReset(th.buildtopClock, th.buildtopReset) {
val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset)
val uart_to_serial = Module(new UARTToSerial(
freq, UARTParams(0, initBaudRate=uartBaudRate)))
val serial_width_adapter = Module(new SerialWidthAdapter(
narrowW = 8, wideW = TSI.WIDTH))
serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
port.clock := th.harnessBinderClock
val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
val uart_to_serial = Module(new UARTToSerial(
freq, UARTParams(0, initBaudRate=uartBaudRate)))
val serial_width_adapter = Module(new SerialWidthAdapter(
narrowW = 8, wideW = TSI.WIDTH))
serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
ath.io_uart_bb.bundle <> uart_to_serial.io.uart
ath.other_leds(1) := uart_to_serial.io.dropped
ath.io_uart_bb.bundle <> uart_to_serial.io.uart
ath.other_leds(1) := uart_to_serial.io.dropped
ath.other_leds(9) := ram.module.io.tsi2tl_state(0)
ath.other_leds(10) := ram.module.io.tsi2tl_state(1)
ath.other_leds(11) := ram.module.io.tsi2tl_state(2)
ath.other_leds(12) := ram.module.io.tsi2tl_state(3)
}
ath.other_leds(9) := ram.module.io.tsi2tl_state(0)
ath.other_leds(10) := ram.module.io.tsi2tl_state(1)
ath.other_leds(11) := ram.module.io.tsi2tl_state(2)
ath.other_leds(12) := ram.module.io.tsi2tl_state(3)
})
}
})
class WithArty100TDDRTL extends OverrideHarnessBinder({
(system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
(system: CanHaveMasterTLMemPort, th: HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => {
require(ports.size == 1)
val artyTh = th.asInstanceOf[Arty100THarness]
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val bundles = artyTh.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }

16
fpga/src/main/scala/vc707/Configs.scala
View File

@@ -18,7 +18,7 @@ import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem}
import chipyard.harness.{DefaultClockFrequencyKey}
import chipyard.harness._
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
@@ -29,7 +29,7 @@ class WithSystemModifications extends Config((site, here, up) => {
case DTSTimebase => BigInt{(1e6).toLong}
case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
// invoke makefile for sdboot
val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong
val freqMHz = (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toLong
val make = s"make -C fpga/src/main/resources/vc707/sdboot PBUS_CLK=${freqMHz} bin"
require (make.! == 0, "Failed to build bootrom")
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
@@ -39,6 +39,15 @@ class WithSystemModifications extends Config((site, here, up) => {
})
class WithVC707Tweaks extends Config (
// clocking
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new WithFPGAFrequency(50) ++ // default 50MHz freq
// harness binders
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new WithVC707UARTHarnessBinder ++
@@ -54,8 +63,7 @@ class WithVC707Tweaks extends Config (
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
new WithFPGAFrequency(50) // default 50MHz freq
new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
)
class RocketVC707Config extends Config (

58
fpga/src/main/scala/vc707/TestHarness.scala
View File

@@ -1,25 +1,25 @@
package chipyard.fpga.vc707
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode}
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem.{SystemBusKey}
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, LEDOverlayKey, LEDDesignInput, SwitchOverlayKey, SwitchDesignInput, ButtonOverlayKey, ButtonDesignInput, SPIOverlayKey, SPIDesignInput, ChipLinkOverlayKey, ChipLinkDesignInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, JTAGDebugOverlayKey, JTAGDebugDesignInput}
import sifive.fpgashells.shell._
import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard.{ChipTop, ExtTLMem, CanHaveMasterTLMemPort}
import chipyard._
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness.{ApplyHarnessBinders, HasHarnessSignalReferences, BuildTop, DefaultClockFrequencyKey}
import chipyard.harness._
class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>
@@ -28,8 +28,6 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
// Order matters; ddr depends on sys_clock
val uart = Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput()))
val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
// place all clocks in the shell
require(dp(ClockInputOverlayKey).size >= 1)
val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node
@@ -41,8 +39,9 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
harnessSysPLL := sysClkNode
// create and connect to the dutClock
println(s"VC707 FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
println(s"VC707 FPGA Base Clock Freq: ${dutFreqMHz} MHz")
val dutWrangler = LazyModule(new ResetWrangler)
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLL
@@ -77,21 +76,19 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
// Modify the last field of `DDRDesignInput` for 1GB RAM size
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
sourceId = IdRange(0, 64)
)))))
// connect 1 mem. channel to the FPGA DDR
val inParams = topDesign match { case td: ChipTop =>
td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
lsys.memTLNode.edges.in(0)
}
}
val ddrClient = TLClientNode(Seq(inParams.master))
ddrNode := ddrClient
// module implementation
override lazy val module = new VC707FPGATestHarnessImp(this)
}
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
require (p(MultiChipNChips) == 0)
val vc707Outer = _outer
@@ -117,25 +114,12 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
val hReset = Wire(Reset())
hReset := _outer.dutClock.in.head._1.reset
val buildtopClock = _outer.dutClock.in.head._1.clock
val buildtopReset = WireInit(hReset)
val dutReset = hReset.asAsyncReset
val success = false.B
def implicitClock = _outer.dutClock.in.head._1.clock
def implicitReset = hReset
def success = { require(false, "Unused"); false.B }
childClock := buildtopClock
childReset := buildtopReset
childClock := implicitClock
childReset := implicitReset
// harness binders are non-lazy
_outer.topDesign match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
// check the top-level reference clock is equal to the default
// non-exhaustive since you need all ChipTop clocks to equal the default
require(getRefClockFreq == p(DefaultClockFrequencyKey))
val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
implicitHarnessClockBundle.clock := buildtopClock
implicitHarnessClockBundle.reset := buildtopReset
harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
instantiateChipTops()
}

17
fpga/src/main/scala/vcu118/Configs.scala
View File

@@ -17,8 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem}
import chipyard.harness.{DefaultClockFrequencyKey}
import chipyard._
import chipyard.harness._
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
@@ -30,7 +30,7 @@ class WithSystemModifications extends Config((site, here, up) => {
case DTSTimebase => BigInt((1e6).toLong)
case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
// invoke makefile for sdboot
val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong
val freqMHz = (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toLong
val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin"
require (make.! == 0, "Failed to build bootrom")
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
@@ -41,8 +41,14 @@ class WithSystemModifications extends Config((site, here, up) => {
// DOC include start: AbstractVCU118 and Rocket
class WithVCU118Tweaks extends Config(
// harness binders
// clocking
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(100) ++
new chipyard.config.WithSystemBusFrequency(100) ++
new chipyard.config.WithPeripheryBusFrequency(100) ++
new WithFPGAFrequency(100) ++ // default 100MHz freq
// harness binders
new WithUART ++
new WithSPISDCard ++
new WithDDRMem ++
@@ -55,8 +61,7 @@ class WithVCU118Tweaks extends Config(
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
new WithFPGAFrequency(100) // default 100MHz freq
new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
)
class RocketVCU118Config extends Config(

10
fpga/src/main/scala/vcu118/HarnessBinders.scala
View File

@@ -9,12 +9,12 @@ import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import chipyard.{CanHaveMasterTLMemPort}
import chipyard.harness.{HasHarnessSignalReferences, OverrideHarnessBinder}
import chipyard._
import chipyard.harness._
/*** UART ***/
class WithUART extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
th match { case vcu118th: VCU118FPGATestHarnessImp => {
vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head
} }
@@ -23,7 +23,7 @@ class WithUART extends OverrideHarnessBinder({
/*** SPI ***/
class WithSPISDCard extends OverrideHarnessBinder({
(system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
(system: HasPeripherySPI, th: BaseModule with HasHarnessInstantiators, ports: Seq[SPIPortIO]) => {
th match { case vcu118th: VCU118FPGATestHarnessImp => {
vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head
} }
@@ -32,7 +32,7 @@ class WithSPISDCard extends OverrideHarnessBinder({
/*** Experimental DDR ***/
class WithDDRMem extends OverrideHarnessBinder({
(system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
(system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => {
th match { case vcu118th: VCU118FPGATestHarnessImp => {
require(ports.size == 1)

50
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -5,8 +5,9 @@ import chisel3.experimental.{IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode}
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
import freechips.rocketchip.subsystem.{SystemBusKey}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
@@ -38,8 +39,6 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))
val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
// DOC include start: ClockOverlay
// place all clocks in the shell
require(dp(ClockInputOverlayKey).size >= 1)
@@ -52,8 +51,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
harnessSysPLL := sysClkNode
// create and connect to the dutClock
println(s"VCU118 FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
println(s"VCU118 FPGA Base Clock Freq: ${dutFreqMHz} MHz")
val dutWrangler = LazyModule(new ResetWrangler)
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLL
@@ -80,19 +80,18 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr
// connect 1 mem. channel to the FPGA DDR
val inParams = topDesign match { case td: ChipTop =>
td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
lsys.memTLNode.edges.in(0)
}
}
val ddrClient = TLClientNode(Seq(inParams.master))
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
sourceId = IdRange(0, 64)
)))))
ddrNode := ddrClient
// module implementation
override lazy val module = new VCU118FPGATestHarnessImp(this)
}
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
require(p(MultiChipNChips) == 0)
val vcu118Outer = _outer
@@ -119,25 +118,12 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
val hReset = Wire(Reset())
hReset := _outer.dutClock.in.head._1.reset
val buildtopClock = _outer.dutClock.in.head._1.clock
val buildtopReset = WireInit(hReset)
val dutReset = hReset.asAsyncReset
val success = false.B
def implicitClock = _outer.dutClock.in.head._1.clock
def implicitReset = hReset
def success = { require(false, "Unused"); false.B }
childClock := buildtopClock
childReset := buildtopReset
childClock := implicitClock
childReset := implicitReset
// harness binders are non-lazy
_outer.topDesign match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
// check the top-level reference clock is equal to the default
// non-exhaustive since you need all ChipTop clocks to equal the default
require(getRefClockFreq == p(DefaultClockFrequencyKey))
val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
implicitHarnessClockBundle.clock := buildtopClock
implicitHarnessClockBundle.reset := buildtopReset
harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
instantiateChipTops()
}

10
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
View File

@@ -13,11 +13,11 @@ import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder, HasHarnessSignalReferences}
import chipyard.harness._
/*** UART ***/
class WithBringupUART extends ComposeHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 2)
@@ -28,7 +28,7 @@ class WithBringupUART extends ComposeHarnessBinder({
/*** I2C ***/
class WithBringupI2C extends OverrideHarnessBinder({
(system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
(system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[I2CPort]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 1)
@@ -39,7 +39,7 @@ class WithBringupI2C extends OverrideHarnessBinder({
/*** GPIO ***/
class WithBringupGPIO extends OverrideHarnessBinder({
(system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
(system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[GPIOPortIO]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
(vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
bb_io.bundle <> dut_io
@@ -50,7 +50,7 @@ class WithBringupGPIO extends OverrideHarnessBinder({
/*** TSI Host Widget ***/
class WithBringupTSIHost extends OverrideHarnessBinder({
(system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => {
(system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessInstantiators, ports: Seq[Data]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link

12
fpga/src/main/scala/vcu118/bringup/TestHarness.scala
View File

@@ -1,5 +1,4 @@
package chipyard.fpga.vcu118.bringup
import chisel3._
import freechips.rocketchip.diplomacy._
@@ -22,6 +21,7 @@ import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidget
import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
import chipyard.{ChipTop}
import chipyard.harness._
class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness {
@@ -78,12 +78,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb))
// connect 1 mem. channel to the FPGA DDR
val inTsiParams = topDesign match { case td: ChipTop =>
td.lazySystem match { case lsys: HasPeripheryTSIHostWidget =>
lsys.tsiMemTLNodes.head.edges.in(0)
}
}
val tsiDdrClient = TLClientNode(Seq(inTsiParams.master))
val tsiDdrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
sourceId = IdRange(0, 64)
)))))
(ddr2Node
:= TLFragmenter(8,64,holdFirstDeny=true)
:= TLCacheCork()