diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc
index 06b57ab3..bedc41f3 100644
--- a/generators/chipyard/src/main/resources/csrc/spiketile.cc
+++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc
@@ -260,11 +260,11 @@ extern "C" void spike_tile(int hartid, char* isa,
                            "vlen:128,elen:64",
                            false,
                            endianness_little,
-                           false,
                            pmpregions,
                            std::vector<mem_cfg_t>(),
                            std::vector<int>(),
-                           false);
+                           false,
+                           0);
     processor_t* p = new processor_t(isa_parser,
                                      cfg,
                                      simif,
diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim
index 0eec0c91..e2a364ad 160000
--- a/toolchains/riscv-tools/riscv-isa-sim
+++ b/toolchains/riscv-tools/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 0eec0c911933ccc722d4b4479a6c4b8ac68f2f52
+Subproject commit e2a364adfd65488623e4cb23e7dde43a52f66c30