some plumbing but still need to remove sram generator target for asap7

.gitmodules

@@ -43,9 +43,6 @@
 [submodule "vlsi/hammer"]
 	path = vlsi/hammer
 	url = https://github.com/ucb-bar/hammer.git
-[submodule "vlsi/hammer-cad-plugins"]
-	path = vlsi/hammer-cad-plugins
-	url = https://github.com/ucb-bar/hammer-cad-plugins.git
 [submodule "tools/dsptools"]
 	path = tools/dsptools
 	url = https://github.com/ucb-bar/dsptools.git
@@ -61,3 +58,12 @@
 [submodule "tools/firrtl-interpreter"]
 	path = tools/firrtl-interpreter
 	url = https://github.com/freechipsproject/firrtl-interpreter.git
+[submodule "vlsi/hammer-cadence-plugins"]
+	path = vlsi/hammer-cadence-plugins
+	url = git@github.com:ucb-bar/hammer-cadence-plugins.git
+[submodule "vlsi/hammer-synopsys-plugins"]
+	path = vlsi/hammer-synopsys-plugins
+	url = git@github.com:ucb-bar/hammer-synopsys-plugins.git
+[submodule "vlsi/hammer-mentor-plugins"]
+	path = vlsi/hammer-mentor-plugins
+	url = git@github.com:ucb-bar/hammer-mentor-plugins.git

scripts/init-vlsi.sh

@@ -5,7 +5,11 @@ set -o pipefail
 
 # Initialize HAMMER and CAD-plugins
 git submodule update --init --recursive vlsi/hammer
-git submodule update --init --recursive vlsi/hammer-cad-plugins
+git submodule update --init --recursive vlsi/hammer-cadence-plugins
+git submodule update --init --recursive vlsi/hammer-synopsys-plugins
+git submodule update --init --recursive vlsi/hammer-mentor-plugins
 
 # Initialize HAMMER tech plugin
-git submodule update --init --recursive vlsi/hammer-"$1"-plugin
+if [[ $1 != *asap7* ]] && [[ $1 != *saed32* ]]; then
+    git submodule update --init --recursive vlsi/hammer-$1-plugin
+fi

vlsi/Makefile

@@ -18,15 +18,15 @@ include $(base_dir)/variables.mk
 # vlsi types and rules
 #########################################################################################
 sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
-tech_name          ?=
-tech_dir           ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)
+tech_name          ?= asap7
+tech_dir           ?= $(if $(filter $(tech_name), asap7 saed32), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
-SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
+cMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
 SMEMS_HAMMER       ?= $(build_dir)/$(long_name).mems.hammer.json
 MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
 OBJ_DIR            ?= $(vlsi_dir)/build
 ENV_YML            ?= $(vlsi_dir)/bwrc-env.yml
-INPUT_CONFS        ?= example.yml $(dir $(tech_dir))/bwrc.yml
+INPUT_CONFS        ?= example.yml
 HAMMER_EXEC        ?= ./example-vlsi
 
 #########################################################################################

vlsi/README.md

@@ -2,8 +2,60 @@ This is the starting point for a vlsi flow from this repository.
 
 This flow will not work without the necessary CAD and technology plugins for HAMMER.
 
-If you are a UCB-affiliate, you may be able to acquire access to the tech-plugins.
+If you are a UCB-affiliate, you may be able to acquire access to the tool & tech plugins.
 
-# Initial Setup Instructions (For All technologies)
-Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-cad-plugins, and the hammer-tech-plugins
-```scripts/init-vlsi.sh TECH_NAME```
+# Initial Setup Instructions (For all technologies)
+Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the included technology 'asap7' is already included and will not submodule a tech plugin.
+```shell
+scripts/init-vlsi.sh TECH_NAME
+```
+
+An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment.
+
+Finally, set up all prerequisites for the build system:
+```shell
+make buildfile
+```
+
+# Example design
+In this example, you will be running a SHA-3 accelerator through the VLSI flow. It is assumed that you have already run through the flow to elaborate the Chisel into Verilog.
+
+HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself.
+
+We start by pulling the HAMMER environment into the shell:
+
+```shell
+export HAMMER_HOME=$PWD/hammer
+source $HAMMER_HOME/sourceme.sh
+```
+
+The configuration for the example design is contained in `example.yml` and the entry script with hooks is contained in `example-vlsi`. You may go through Hammer's readme to learn about the supported configuration options and how to write hooks.
+
+To synthesize a design:
+
+```shell
+make syn
+```
+
+The outputs are written to a log file with a timestamp and the post-synthesis results are in `build/syn-rundir`.
+
+Raw QoR data is available at `build/syn-rundir/reports`, and work is planned to extract this information in a more programmatic manner.
+
+To run place and route:
+```shell
+make par
+```
+
+If successful, the resulting chip can be opened via `./build/par-rundir/generated-scripts/open_chip`.
+
+To run DRC and view violations:
+```shell
+make drc
+./build/drc-rundir/generated-scripts/view-drc
+```
+
+To run LVS and view violations:
+```shell
+make lvs
+./build/lvs-rundir/generated-scripts/view-lvs
+```

vlsi/bwrc-env.yml

@@ -0,0 +1,7 @@
+mentor.mentor_home: "/tools/mentor"
+mentor.MGLS_LICENSE_FILE: "1717@bwrcflex-1.eecs.berkeley.edu:1717@bwrcflex-2.eecs.berkeley.edu"
+cadence.cadence_home: "/tools/cadence"
+cadence.CDS_LIC_FILE: "5280@bwrcflex-1.eecs.berkeley.edu:5280@bwrcflex-2.eecs.berkeley.edu"
+synopsys.synopsys_home: "/tools/synopsys"
+synopsys.SNPSLMD_LICENSE_FILE: "1701@bwrcflex-1.eecs.berkeley.edu:1701@bwrcflex-2.eecs.berkeley.edu"
+synopsys.MGLS_LICENSE_FILE: "1717@bwrcflex-1.eecs.berkeley.edu:1717@bwrcflex-2.eecs.berkeley.edu"

vlsi/example.yml

@@ -30,6 +30,58 @@ vlsi.core.build_system: make
 
 # Power Straps
 par.power_straps_mode: generate
+par.generate_power_straps_method: by_tracks
+par.blockage_spacing: 2.0
+par.generate_power_straps_options:
+  by_tracks:
+    strap_layers:
+      - M3
+      - M4
+      - M5
+      - M6
+      - M7
+      - M8
+      - M9
+    track_width: 6
+    track_spacing: 0
+    power_utilization: 0.05
+    power_utilization_M8: 1.0
+    power_utilization_M9: 1.0
 
 # Placement Constraints
-#vlsi.inputs.placement_constraints:
+vlsi.inputs.placement_constraints:
+  - path: "ExampleTop"
+    type: "toplevel"
+    x: 0
+    y: 0
+    width: 50
+    height: 50
+    margins:
+      left: 0
+      right: 0
+      top: 0
+      bottom: 0
+
+# SRAM Compiler compiler options
+vlsi.core.sram_generator_tool: "sram_compiler"
+vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"]
+vlsi.core.sram_generator_tool_path_meta: "append"
+
+# Tool options. Replace with your tool plugin of choice.
+# Genus options
+vlsi.core.synthesis_tool: "genus"
+vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
+vlsi.core.synthesis_tool_path_meta: "append"
+synthesis.genus.version: "181"
+# Innovus options
+vlsi.core.par_tool: "innovus"
+vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
+vlsi.core.par_tool_path_meta: "append"
+par.innovus.version: "181"
+par.innovus.design_flow_effort: "standard"
+par.inputs.gds_merge: true
+# Calibre options
+vlsi.core.drc_tool: "calibre"
+vlsi.core.drc_tool_path: ["hammer-cad-plugins/drc"]
+vlsi.core.lvs_tool: "calibre"
+vlsi.core.lvs_tool_path: ["hammer-cad-plugins/lvs"]