diff --git a/fpga/Makefile b/fpga/Makefile index fdb0daaf..f9f02fc6 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -77,7 +77,7 @@ ifeq ($(SUB_PROJECT),arty100t) MODEL ?= Arty100THarness VLOG_MODEL ?= Arty100THarness MODEL_PACKAGE ?= chipyard.fpga.arty100t - CONFIG ?= RocketArtyConfig + CONFIG ?= RocketArty100TConfig CONFIG_PACKAGE ?= chipyard.fpga.arty100t GENERATOR_PACKAGE ?= chipyard TB ?= none # unused diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 34678a81..b6cd1bb7 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 34678a8123602860d897b8b9d731d951e99aa21d +Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9 diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index bade069d..af1c128f 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -26,15 +26,33 @@ class WithArty100TTweaks extends Config( new WithArty100TDDRTL ++ new WithNoDesignKey ++ new chipyard.config.WithNoDebug ++ // no jtag - new chipyard.config.WithNoUART ++ + new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad new chipyard.config.WithTLBackingMemory ++ - new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) // 256mb on ARTY + new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY + new freechips.rocketchip.subsystem.WithoutTLMonitors ) -class RocketArtyConfig extends Config( +class RocketArty100TConfig extends Config( new WithArty100TTweaks ++ - new chipyard.config.WithMemoryBusFrequency(10.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) + new chipyard.config.WithMemoryBusFrequency(10.0) ++ new chipyard.config.WithPeripheryBusFrequency(10.0) ++ // Match the sbus and pbus frequency new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.RocketConfig ) + +class NoCoresArty100TConfig extends Config( + new WithArty100TTweaks ++ + new chipyard.config.WithMemoryBusFrequency(10.0) ++ + new chipyard.config.WithPeripheryBusFrequency(10.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithBroadcastManager ++ // no l2 + new chipyard.NoCoresConfig +) + +class InitZeroNoCoresArty100TConfig extends Config( + new WithArty100TTweaks ++ + new chipyard.example.WithInitZero(0x80000000L, 0x1000L) ++ + new chipyard.config.WithMemoryBusFrequency(10.0) ++ + new chipyard.config.WithPeripheryBusFrequency(10.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithBroadcastManager ++ // no l2 + new chipyard.NoCoresConfig +) diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 2b2dd209..20857f7b 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -1,7 +1,7 @@ package chipyard.fpga.arty100t import chisel3._ - +import chisel3.util._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} @@ -24,19 +24,20 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell val chiptop = LazyModule(p(BuildTop)(p)) val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head - val harnessSysPLL = dp(PLLFactoryKey)() + val harnessSysPLL = dp(PLLFactoryKey) + val harnessSysPLLNode = harnessSysPLL() println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz") val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey)) val dutWrangler = LazyModule(new ResetWrangler) val dutGroup = ClockGroup() - dutClock := dutWrangler.node := dutGroup := harnessSysPLL + dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode - harnessSysPLL := clockOverlay.overlayOutput.node + harnessSysPLLNode := clockOverlay.overlayOutput.node val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0)))) val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)) + val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay] val ddrInParams = chiptop match { case td: ChipTop => td.lazySystem match { case lsys: CanHaveMasterTLMemPort => lsys.memTLNode.edges.in(0) @@ -45,11 +46,39 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell val ddrClient = TLClientNode(Seq(ddrInParams.master)) ddrOverlay.overlayOutput.ddr := ddrClient + val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput())) + val all_leds = ledOverlays.map(_.overlayOutput.led) + val status_leds = all_leds.take(3) + val other_leds = all_leds.drop(3) + def buildtopClock = dutClock.in.head._1.clock def buildtopReset = dutClock.in.head._1.reset def success = { require(false, "Unused"); false.B } InModuleBody { + clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin + + val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock + + // Blink the status LEDs for sanity + withClock(clk_100mhz) { + val period = (BigInt(100) << 20) / status_leds.size + val counter = RegInit(0.U(log2Ceil(period).W)) + val on = RegInit(0.U(log2Ceil(status_leds.size).W)) + status_leds.zipWithIndex.map { case (o,s) => o := on === s.U } + counter := Mux(counter === (period-1).U, 0.U, counter + 1.U) + when (counter === 0.U) { + on := Mux(on === (status_leds.size-1).U, 0.U, on + 1.U) + } + } + + other_leds(0) := resetPin + + harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset) + + ddrOverlay.mig.module.clock := buildtopClock + ddrOverlay.mig.module.reset := buildtopReset + chiptop match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index f8763948..e0b39704 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -24,13 +24,24 @@ class WithArty100TUARTTSI extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => + val ath = th.asInstanceOf[Arty100THarness] val freq = p(PeripheryBusKey).dtsFrequency.get val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) withClockAndReset(th.buildtopClock, th.buildtopReset) { val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) val uart_to_tsi = Module(new UARTToTSI(freq)) ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial) - th.asInstanceOf[Arty100THarness].io_uart_bb.bundle <> uart_to_tsi.io.uart + + ath.io_uart_bb.bundle <> uart_to_tsi.io.uart + ath.other_leds(1) := uart_to_tsi.io.serial.out.valid + ath.other_leds(2) := uart_to_tsi.io.serial.in.valid + ath.other_leds(3) := uart_to_tsi.io.uart.rxd + ath.other_leds(4) := uart_to_tsi.io.uart.txd + + ath.other_leds(9) := ram.module.io.adapter_state(0) + ath.other_leds(10) := ram.module.io.adapter_state(1) + ath.other_leds(11) := ram.module.io.adapter_state(2) + ath.other_leds(12) := ram.module.io.adapter_state(3) } }) } diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 1ef19b39..34175d39 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -62,6 +62,9 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem val intSink = IntSinkNode(IntSinkPortSimple()) intSink := intNexus :=* ibus.toPLIC + // avoids a bug when there are no interrupt sources + ibus.fromAsync := NullIntSource() + // Need to have at least 1 driver to the tile notification sinks tileHaltXbarNode := IntSourceNode(IntSourcePortSimple()) tileWFIXbarNode := IntSourceNode(IntSourcePortSimple()) diff --git a/generators/testchipip b/generators/testchipip index 653c86b0..0afbac5f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 653c86b0e81f3f9ac7e6d0a50f250be5a4bb0e1c +Subproject commit 0afbac5f0231d3149f3f4e2a2b67f893c66e9f20