From 624785376a584dc293e1d717e2ea38f72b209b42 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 23:34:29 -0700 Subject: [PATCH] Fix PassThroughClockGenerator to handle multiclock properly --- .../main/scala/clocking/ClockBinders.scala | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index c91f5cb4..5a53051e 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -103,20 +103,20 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ // This aggregate node should do nothing val clockGroupAggNode = ClockGroupAggregateNode("fake") val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - system.allClockGroupsNode :*= clockGroupAggNode := clockGroupsSourceNode + system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode InModuleBody { val reset_io = IO(Input(AsyncReset())) - val clock_ios = clockGroupAggNode.out.map { case (bundle, edge) => - val freqs = edge.sink.members.map(_.take.map(_.freqMHz)).flatten - require(freqs.distinct.size == 1) - val clock_io = IO(Input(new ClockWithFreq(freqs.head))).suggestName(s"clock_${edge.sink.name}") - bundle.member.data.foreach { b => - b.clock := clock_io.clock - b.reset := reset_io - } + require(clockGroupAggNode.out.size == 1) + val (bundle, edge) = clockGroupAggNode.out(0) + + val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) => + val freq = m.take.get.freqMHz + val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}") + b.clock := clock_io.clock + b.reset := reset_io clock_io - } + }.toSeq ((clock_ios :+ reset_io), Nil) } }