diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 7d6c226f..1316d786 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -28,7 +28,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port - with freechips.rocketchip.tilelink.CanHaveMemtraceCore // Enable memtrace core + with radiance.memory.CanHaveMemtraceCore // Enable memtrace core + with radiance.memory.CanHaveRadianceROMs // Enable argument ROMs with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index b136de90..5643e380 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -6,14 +6,13 @@ package chipyard import chisel3._ -import org.chipsalliance.cde.config.{Field, Parameters} + +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util.DontTouch - -import java.nio.file.Paths +import freechips.rocketchip.util.{DontTouch} // --------------------------------------------------------------------- // Base system that uses the debug test module (dtm) to bringup the core @@ -32,7 +31,6 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - p(RadianceROMsLocated()).foreach { BootROM.attachROM(_, this, CBUS) } // If there is no bootrom, the tile reset vector bundle will be tied to zero if (bootROM.isEmpty) { diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala index 34cce07e..5403b8ec 100644 --- a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala +++ b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala @@ -5,18 +5,18 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing} class MemtraceCoreConfig extends Config( // Memtrace - new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", + new radiance.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", traceHasSource = false) ++ - // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + // new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", // traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 2) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ + new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(16 * 8) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) @@ -26,225 +26,225 @@ class MemtraceCoreConfig extends Config( ///////////////////////////////////////////////// class MemtraceCoreNV64B2IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(64) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV128B2IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(128) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV256B2IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(256) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV512B2IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(512) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV64B8IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(64) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV128B8IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(128) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV256B8IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(256) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV512B8IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(512) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV64B16IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(64) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV128B16IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(128) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV256B16IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(256) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV512B16IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(512) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV64B32IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(64) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV128B32IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(128) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV256B32IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(256) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) class MemtraceCoreNV512B32IdConfig extends Config( - new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ + new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(512) ++ // Small Rocket core that does nothing - new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new radiance.subsystem.WithNCustomSmallRocketCores(1) ++ new chipyard.config.AbstractConfig ) diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala new file mode 100644 index 00000000..bbd88c90 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala @@ -0,0 +1,143 @@ +package chipyard + +import chipyard.config.AbstractConfig +import chipyard.stage.phases.TargetDirKey +import freechips.rocketchip.devices.tilelink.BootROMLocated +import freechips.rocketchip.diplomacy.AsynchronousCrossing +import freechips.rocketchip.subsystem.WithExtMemSize +import freechips.rocketchip.tile.XLen +import org.chipsalliance.cde.config.Config +import radiance.memory._ +// -------------- +// Rocket Configs +// -------------- + +class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => { + case RadianceROMsLocated() => Some(up(RadianceROMsLocated()).getOrElse(Seq()) ++ + Seq(RadianceROMParams( + address = address, + size = size, + contentFileName = filename + ))) +}) + +class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => { + case BootROMLocated(x) => up(BootROMLocated(x), site) + .map(_.copy( + address = address, + size = size, + hang = hang, + contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv${site(XLen)}.img" + )) +}) + +class RocketDummyVortexConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++ + + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + + new AbstractConfig) + +class RocketGPUConfig extends Config( + new radiance.subsystem.WithNCustomSmallRocketCores(2) ++ // multiple rocket-core + new chipyard.config.AbstractConfig) + +class RadianceROMConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + // new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new WithRadBootROM() ++ + new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ + new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ + new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ + new AbstractConfig) + +class RadianceROMNoCoalConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + // new radiance.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + // new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new WithRadBootROM() ++ + new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ + new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ + new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ + new AbstractConfig) + +class RadianceROMLargeConfig extends Config( + new radiance.subsystem.WithRadianceCores(4, useVxCache = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + // new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new WithRadBootROM() ++ + new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ + new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ + new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ + new AbstractConfig) + +class RadianceROMCacheConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new WithRadBootROM() ++ + new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ + new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ + new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ + new AbstractConfig) + +class RadianceROMCacheNoCoalConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + // new radiance.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new WithRadBootROM() ++ + new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ + new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ + new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ + new AbstractConfig) + +class RadianceConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new WithRadBootROM() ++ + new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++ + new AbstractConfig) + +class RadianceConfigVortexCache extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = true) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + // new freechips.rocketchip.subsystem.WithNoMemPort ++ + // new testchipip.WithSbusScratchpad(banks=2) ++ + // new testchipip.WithMbusScratchpad(banks=2) ++ + new WithExtMemSize(BigInt("80000000", 16)) ++ + new WithRadBootROM() ++ + new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ + new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ + new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ + new AbstractConfig +) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index cade9157..c45fb6f2 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,12 +1,8 @@ package chipyard -import chipyard.config.{AbstractConfig, WithBootROM} -import chipyard.stage.phases.TargetDirKey -import org.chipsalliance.cde.config.{Config, Field} -import freechips.rocketchip.diplomacy.AsynchronousCrossing -import freechips.rocketchip.devices.tilelink.{BootROMLocated, RadianceROMParams, RadianceROMsLocated} -import freechips.rocketchip.subsystem.{WithBootROMFile, WithExtMemSize} -import freechips.rocketchip.tile.XLen +import org.chipsalliance.cde.config.{Config} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing} + // -------------- // Rocket Configs // -------------- @@ -15,133 +11,6 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) - -class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => { - case RadianceROMsLocated() => up(RadianceROMsLocated()) ++ - Seq(RadianceROMParams( - address = address, - size = size, - contentFileName = filename - )) -}) - -class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => { - case BootROMLocated(x) => up(BootROMLocated(x), site) - .map(_.copy( - address = address, - size = size, - hang = hang, - contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv${site(XLen)}.img" - )) -}) - -class RocketDummyVortexConfig extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++ - - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - - new AbstractConfig) - -class RadianceROMConfig extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - // new freechips.rocketchip.subsystem.WithNBanks(4) ++ - new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ - new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ - new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ - new AbstractConfig) - -class RadianceROMNoCoalConfig extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ - // new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - // new freechips.rocketchip.subsystem.WithNBanks(4) ++ - new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ - new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ - new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ - new AbstractConfig) - -class RadianceROMLargeConfig extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(4, useVxCache = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - // new freechips.rocketchip.subsystem.WithNBanks(4) ++ - new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ - new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ - new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ - new AbstractConfig) - -class RadianceROMCacheConfig extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithVortexL1Banks(nBanks = 1)++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ - new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ - new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ - new AbstractConfig) - -class RadianceROMCacheNoCoalConfig extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ - // new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ - new freechips.rocketchip.subsystem.WithVortexL1Banks(nBanks = 1)++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ - new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ - new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ - new AbstractConfig) - -class RadianceConfig extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++ - new AbstractConfig) - -class RadianceConfigVortexCache extends Config( - new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = true) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - // new freechips.rocketchip.subsystem.WithNoMemPort ++ - // new testchipip.WithSbusScratchpad(banks=2) ++ - // new testchipip.WithMbusScratchpad(banks=2) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ - new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ - new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ - new AbstractConfig -) - class TinyRocketConfig extends Config( new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology @@ -150,10 +19,6 @@ class TinyRocketConfig extends Config( new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core new chipyard.config.AbstractConfig) -class RocketGPUConfig extends Config( - new freechips.rocketchip.subsystem.WithNCustomSmallCores(2) ++ // multiple rocket-core - new chipyard.config.AbstractConfig) - class SimAXIRocketConfig extends Config( new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM new freechips.rocketchip.subsystem.WithNBigCores(1) ++