diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 61a6234c..2a78a54c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -31,7 +31,7 @@ class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithArtyResetHarnessBinder ++ - new WithResetPassthrough ++ + new WithDebugResetPassthrough ++ new WithDefaultPeripherals ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 3c52f249..44913ba2 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,7 +17,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem} +import chipyard.{BuildSystem, ExtTLMem} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) @@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) @@ -41,6 +40,11 @@ class WithSystemModifications extends Config((site, here, up) => { case SerialTLKey => None // remove serialized tl port }) +class WithTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None // disable AXI backing memory + case ExtTLMem => up(ExtMem, site) // enable TL backing memory +}) + // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( new WithUART ++ @@ -50,6 +54,7 @@ class WithVCU118Tweaks extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ + new WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala deleted file mode 100644 index d5c747fa..00000000 --- a/fpga/src/main/scala/vcu118/DigitalTop.scala +++ /dev/null @@ -1,106 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.{DontTouch} - -import chipyard.{DigitalTop, DigitalTopModule, ChipyardSubsystem, ChipyardSubsystemModuleImp} - -// ------------------------------------ -// VCU118 DigitalTop -// ------------------------------------ - -class VCU118DigitalTop(implicit p: Parameters) extends VCU118ChipyardSystem - with testchipip.CanHaveTraceIO // Enables optionally adding trace IO - with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad - with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter - with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART - with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs - with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller - with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port - with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim - with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget - with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget - with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget - with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA -{ - override lazy val module = new VCU118DigitalTopModule(this) -} - -class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends VCU118ChipyardSystemModule(l) - with testchipip.CanHaveTraceIOModuleImp - with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp - with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with chipyard.example.CanHavePeripheryGCDModuleImp - with freechips.rocketchip.util.DontTouch - -// ------------------------------------ -// VCU118 Chipyard System -// ------------------------------------ - -class VCU118ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem - with HasAsyncExtInterrupts - with CanHaveMasterTLMemPort // expose a TL port for outer memory (replaces AXI outer port) - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port -{ - - val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } - val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - override lazy val module = new VCU118ChipyardSystemModule(this) -} - -class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) - with HasRTCModuleImp - with HasExtInterruptsModuleImp - with DontTouch - -// ------------------------------------ -// VCU118 Mem Port Mixin -// ------------------------------------ - -/** Adds a port to the system intended to master an TL DRAM controller. */ -trait CanHaveMasterTLMemPort { this: BaseSubsystem => - private val memPortParamsOpt = p(ExtMem) - private val portName = "tl_mem" - private val device = new MemoryDevice - private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) - - val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => - Seq.tabulate(nMemoryChannels) { channel => - val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - - TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = base.flatMap(_.intersect(filter)), - resources = device.reg, - regionType = RegionType.UNCACHED, // cacheable - executable = true, - supportsGet = TransferSizes(1, mbus.blockBytes), - supportsPutFull = TransferSizes(1, mbus.blockBytes), - supportsPutPartial = TransferSizes(1, mbus.blockBytes))), - beatBytes = memPortParams.beatBytes) - } - }).toList.flatten) - - mbus.coupleTo(s"memory_controller_port_named_$portName") { - (memTLNode - :*= TLBuffer() - :*= TLSourceShrinker(1 << idBits) - :*= TLWidthWidget(mbus.beatBytes) - :*= _) - } - - val mem_tl = InModuleBody { memTLNode.makeIOs() } -} diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index 6ba53642..d60af21a 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{HasHarnessSignalReferences} +import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} import chipyard.harness.{OverrideHarnessBinder} /*** UART ***/ diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala index 4c5bb357..a1f67bcd 100644 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} +import chipyard.{CanHaveMasterTLMemPort} import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index cd88ff8e..5002817f 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -17,7 +17,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -79,7 +79,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** DDR ***/ - val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr + val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr // connect 1 mem. channel to the FPGA DDR val inParams = topDesign match { case td: ChipTop => diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index 251ea8e9..5b554f5b 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -9,18 +9,18 @@ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ -import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} +import chipyard.{DigitalTop, DigitalTopModule} // ------------------------------------ // Bringup VCU118 DigitalTop // ------------------------------------ -class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop +class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } -class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) +class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c0ac1ff7..7fd682d2 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -35,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index bd20ddc7..4ab0da3e 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -7,7 +7,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ @@ -23,7 +23,8 @@ import freechips.rocketchip.util.{DontTouch} */ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts - with CanHaveMasterAXI4MemPort + with CanHaveMasterTLMemPort // export TL port for outer memory + with CanHaveMasterAXI4MemPort // expose AXI port for outer mem with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port { @@ -40,3 +41,46 @@ class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubs with HasRTCModuleImp with HasExtInterruptsModuleImp with DontTouch + +// ------------------------------------ +// TL Mem Port Mixin +// ------------------------------------ + +// Similar to ExtMem but instantiates a TL mem port +case object ExtTLMem extends Field[Option[MemoryPortParams]](None) + +/** Adds a port to the system intended to master an TL DRAM controller. */ +trait CanHaveMasterTLMemPort { this: BaseSubsystem => + private val memPortParamsOpt = p(ExtTLMem) + private val portName = "tl_mem" + private val device = new MemoryDevice + private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsGet = TransferSizes(1, mbus.blockBytes), + supportsPutFull = TransferSizes(1, mbus.blockBytes), + supportsPutPartial = TransferSizes(1, mbus.blockBytes))), + beatBytes = memPortParams.beatBytes) + } + }).toList.flatten) + + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) + } + + val mem_tl = InModuleBody { memTLNode.makeIOs() } +}