From 686d9a5f44bd074e9e28790cd982ebade7a57def Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 18 Oct 2023 00:27:05 -0700
Subject: [PATCH] Bump rocket-chip

---
 generators/rocket-chip                          |  2 +-
 generators/tracegen/src/main/scala/System.scala | 10 +++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/generators/rocket-chip b/generators/rocket-chip
index e0ea9034..d48b45da 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit e0ea90344e9edb6a4e24f84e7729d83c217c8859
+Subproject commit d48b45da568c0d370479325258018a8a5cf3369c
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index 5d3953cb..e7e3a033 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -11,14 +11,22 @@ import boom.lsu.BoomTraceGenTile
 class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
     with InstantiatesHierarchicalElements
     with HasTileNotificationSinks
+    with HasTileInputConstants
+    with HasHierarchicalElementsRootContext
+    with HasHierarchicalElements
     with CanHaveMasterAXI4MemPort {
 
   def coreMonitorBundles = Nil
+
   val tileStatusNodes = totalTiles.values.toSeq.collect {
     case t: GroundTestTile => t.statusNode.makeSink()
     case t: BoomTraceGenTile => t.statusNode.makeSink()
   }
-  lazy val debugNode = IntSyncXbar() := NullIntSyncSource()
+
+  lazy val clintOpt = None
+  lazy val debugOpt = None
+  lazy val plicOpt = None
+
   override lazy val module = new TraceGenSystemModuleImp(this)
 }