wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Fixed typo

Browse Source
This commit is contained in:
Zitao Fang
2020-07-19 21:48:07 -07:00
parent 0a39819f44
commit 692b120b65
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
docs/Customization/Custom-Core.rst
View File

@@ -13,7 +13,7 @@ instructions on how to achieve this.
.. note::
This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately
from Chipyard. If you find any discrepency between the code on this page and the code in the source file, please report it through
from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through
GitHub issues!
Wrap Verilog Module with Blackbox (Optional)