diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ba88377f..42663f0b 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,6 +17,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.fpgashells.shell.{DesignKey} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} @@ -24,14 +25,20 @@ class WithChipyardBuildTop extends Config((site, here, up) => { case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } }) -class WithBringupUARTs extends Config((site, here, up) => { +class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) + case PeripherySPIKey => List( + SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64004000L))) + case PeripheryI2CKey => List( + I2CParams(address = BigInt(0x64005000L))) + case VCU118ShellPMOD => "SDIO" }) class FakeBringupConfig extends Config( - new WithBringupUARTs ++ + new WithBringupPeripherals ++ new WithChipyardBuildTop ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala new file mode 100644 index 00000000..3d51c3e7 --- /dev/null +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -0,0 +1,65 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ + +import freechips.rocketchip.diplomacy._ + +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell.xilinx._ + +import chipyard.fpga.vcu118.{FMCPMap} + +/* Connect the I2C to certain FMC pins */ +class BringupI2CVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) + extends I2CXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(shellInput.index == 0) // only support 1 I2C <-> FMC connection + val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2"))) + val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)), + (i2cLocations(shellInput.index)(1), IOPin(io.sda))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + } } +} + +class BringupI2CVCU118ShellPlacer(val shell: VCU118Shell, val shellInput: I2CShellInput)(implicit val valName: ValName) + extends I2CShellPlacer[VCU118Shell] +{ + def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +/* Connect the UART to certain FMC pins */ +class BringupUARTVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) + extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) +{ + shell { InModuleBody { + val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused + (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused + (FMCPMap("C15"), IOPin(io.rxd)), + (FMCPMap("C14"), IOPin(io.txd))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + + // add pullup on ctsn (ctsn is an input that is not used or driven) + packagePinsWithPackageIOs take 1 foreach { case (pin, io) => { + shell.xdc.addPullup(io) + } } + } } +} + +class BringupUARTVCU118ShellPlacer(shell: VCU118Shell, val shellInput: UARTShellInput)(implicit val valName: ValName) + extends UARTShellPlacer[VCU118Shell] { + def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +/* Connect SPI to ADI device */ diff --git a/fpga/src/main/scala/vcu118/FMCUtil.scala b/fpga/src/main/scala/vcu118/FMCUtil.scala new file mode 100644 index 00000000..00982585 --- /dev/null +++ b/fpga/src/main/scala/vcu118/FMCUtil.scala @@ -0,0 +1,334 @@ +package chipyard.fpga.vcu118 + +import scala.collection.immutable.HashMap + +// TODO: was typed by hand, so this needs a once-over before it can be considered trustworthy + +object FMCMap { + // Take an FMC pin name and return the VCU118 package pin + // See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf + // Pages 97-98 + // Omitted pins are not connected to a GPIO + def apply(fmcPin: String): String = HashMap( + "C10" -> "BD13", + "C11" -> "BE13", + "C14" -> "BB13", + "C15" -> "BB12", + "C18" -> "AW8", + "C19" -> "AW7", + "C22" -> "AP12", + "C23" -> "AR12", + "C26" -> "AL14", + "C27" -> "AM14", + "D1" -> "AK35", + "D8" -> "BF10", + "D9" -> "BF9", + "D11" -> "BE14", + "D12" -> "BF14", + "D14" -> "BA14", + "D15" -> "BB14", + "D17" -> "AY8", + "D18" -> "AY7", + "D20" -> "AR14", + "D21" -> "AT14", + "D23" -> "AN16", + "D24" -> "AP16", + "D26" -> "AK15", + "D27" -> "AL15", + "F1" -> "BA7", + "G2" -> "AV14", + "G3" -> "AV13", + "G6" -> "AY9", + "G7" -> "BA9", + "G9" -> "BD12", + "G10" -> "BE12", + "G12" -> "BE15", + "G13" -> "BF15", + "G15" -> "BC14", + "G16" -> "BC13", + "G18" -> "AV9", + "G19" -> "AV8", + "G21" -> "AW11", + "G22" -> "AY10", + "G24" -> "AW13", + "G25" -> "AY13", + "G27" -> "AT12", + "G28" -> "AU12", + "G30" -> "AN15", + "G31" -> "AP15", + "G33" -> "AM13", + "G34" -> "AM12", + "G36" -> "AK14", + "G37" -> "AK13", + "H2" -> "BB7", + "H4" -> "BC9", + "H5" -> "BC8", + "H7" -> "BC11", + "H8" -> "BD11", + "H10" -> "BF12", + "H11" -> "BF11", + "H13" -> "BC15", + "H14" -> "BD15", + "H16" -> "BA16", + "H17" -> "BA15", + "H19" -> "BB16", + "H20" -> "BC16", + "H22" -> "AW12", + "H23" -> "AY12", + "H25" -> "AU11", + "H26" -> "AV11", + "H28" -> "AP13", + "H29" -> "AR13", + "H31" -> "AV10", + "H32" -> "AW10", + "H34" -> "AK12", + "H35" -> "AL12", + "H37" -> "AJ13", + "H38" -> "AJ12" + )(fmcPin) +} + +object FMCPMap { + // Take an FMC+ pin name and return the VCU118 package pin + // See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf + // Pages 100-106 + // Omitted pins are not connected to a GPIO + def apply(fmcpPin: String): String = HashMap( + "A2" -> "AN45", + "A3" -> "AN46", + "A6" -> "AL45", + "A7" -> "AL45", + "A10" -> "AJ45", + "A11" -> "AJ46", + "A14" -> "W45", + "A15" -> "W46", + "A18" -> "U45", + "A19" -> "U46", + "A22" -> "AP42", + "A23" -> "AP43", + "A26" -> "AM42", + "A27" -> "AM43", + "A30" -> "AL40", + "A31" -> "AL41", + "A34" -> "T42", + "A35" -> "T43", + "A38" -> "P42", + "A39" -> "P43", + "B4" -> "AF43", + "B5" -> "AF44", + "B8" -> "AG45", + "B9" -> "AG46", + "B12" -> "N45", + "B13" -> "N46", + "B16" -> "R45", + "B17" -> "R46", + "B24" -> "AJ40", + "B25" -> "AJ41", + "B28" -> "AK42", + "B29" -> "AK43", + "B32" -> "K42", + "B33" -> "K43", + "B36" -> "M42", + "B37" -> "M43", + "C2" -> "AT42", + "C3" -> "AT43", + "C6" -> "AR45", + "C7" -> "AR46", + "C10" -> "AT35", + "C11" -> "AT36", + "C14" -> "AP35", + "C15" -> "AR35", + "C18" -> "AG31", + "C19" -> "AH31", + "C22" -> "R31", + "C23" -> "P31", + "C26" -> "V33", + "C27" -> "V34", + "D1" -> "AK35", + "D8" -> "AL30", + "D9" -> "AL31", + "D11" -> "AP38", + "D12" -> "AR38", + "D14" -> "AJ33", + "D15" -> "AK33", + "D17" -> "AJ35", + "D18" -> "AJ36", + "D20" -> "R34", + "D21" -> "P34", + "D23" -> "Y32", + "D24" -> "W32", + "D26" -> "V32", + "D27" -> "U33", + "E2" -> "V15", + "E3" -> "U15", + "E6" -> "R14", + "E7" -> "P14", + "E9" -> "W14", + "E10" -> "V14", + "E12" -> "V13", + "E13" -> "U12", + "E15" -> "T14", + "E16" -> "R13", + "E18" -> "M15", + "E19" -> "L15", + "F1" -> "AM34", + "F4" -> "N14", + "F5" -> "N13", + "F7" -> "AA13", + "F8" -> "Y13", + "F10" -> "U11", + "F11" -> "T11", + "F13" -> "T16", + "F14" -> "T15", + "F16" -> "M13", + "F17" -> "M12", + "F19" -> "L14", + "F20" -> "L13", + "G2" -> "P35", + "G3" -> "P36", + "G6" -> "AL35", + "G7" -> "AL36", + "G9" -> "AT39", + "G10" -> "AT40", + "G12" -> "AK29", + "G13" -> "AK30", + "G15" -> "AH33", + "G16" -> "AH34", + "G18" -> "AG34", + "G19" -> "AH35", + "G21" -> "N32", + "G22" -> "M32", + "G24" -> "N34", + "G25" -> "N35", + "G27" -> "Y34", + "G28" -> "W34", + "G30" -> "U35", + "G31" -> "T36", + "G33" -> "P37", + "G34" -> "N37", + "G36" -> "L34", + "G37" -> "K34", + "H2" -> "AM33", + "H4" -> "AL32", + "H5" -> "AM32", + "H7" -> "AJ32", + "H8" -> "AK32", + "H10" -> "AR37", + "H11" -> "AT37", + "H13" -> "AP36", + "H14" -> "AP37", + "H16" -> "AJ30", + "H17" -> "AJ31", + "H19" -> "AG32", + "H20" -> "AG33", + "H22" -> "N33", + "H23" -> "M33", + "H25" -> "M35", + "H26" -> "L35", + "H28" -> "T34", + "H29" -> "T35", + "H31" -> "M36", + "H32" -> "L36", + "H34" -> "N38", + "H35" -> "M38", + "H37" -> "L33", + "H38" -> "K33", + "J6" -> "W12", + "J7" -> "V12", + "J9" -> "AA14", + "J10" -> "Y14", + "J12" -> "R12", + "J13" -> "P12", + "J15" -> "M11", + "J16" -> "L11", + "J18" -> "P15", + "J19" -> "N15", + "J21" -> "K12", + "J22" -> "J12", + "K7" -> "AA12", + "K8" -> "Y12", + "K10" -> "U13", + "K11" -> "T13", + "K13" -> "V16", + "K14" -> "U16", + "K16" -> "R11", + "K17" -> "P11", + "K19" -> "K14", + "K20" -> "K13", + "K22" -> "K11", + "K23" -> "J11", + "L4" -> "R40", + "L5" -> "R41", + "L8" -> "AB38", + "L9" -> "AB39", + "L12" -> "AF38", + "L13" -> "AF39", + "L16" -> "AN34", + "L17" -> "AN35", + "L20" -> "AN33", + "L21" -> "AP33", + "L24" -> "AK34", + "L25" -> "AL34", + "L28" -> "AM36", + "L29" -> "AN36", + "M2" -> "AU45", + "M3" -> "AU46", + "M6" -> "AW45", + "M7" -> "AW46", + "M10" -> "BA45", + "M11" -> "BA46", + "M14" -> "BC45", + "M15" -> "BC46", + "M18" -> "W40", + "M19" -> "W41", + "M22" -> "U40", + "M23" -> "U41", + "M26" -> "H42", + "M27" -> "H43", + "M30" -> "F42", + "M31" -> "F43", + "M34" -> "D42", + "M35" -> "D43", + "M38" -> "B42", + "M39" -> "B43", + "Y2" -> "AV42", + "Y3" -> "AV43", + "Y6" -> "BB42", + "Y7" -> "BB43", + "Y10" -> "AE45", + "Y11" -> "AE46", + "Y14" -> "AC45", + "Y15" -> "AC46", + "Y18" -> "AA45", + "Y19" -> "AA46", + "Y22" -> "Y43", + "Y23" -> "Y44", + "Y26" -> "AE40", + "Y27" -> "AE41", + "Y30" -> "AA40", + "Y31" -> "AA41", + "Y34" -> "J45", + "Y35" -> "J46", + "Y38" -> "E45", + "Y39" -> "E46", + "Z1" -> "AM29", + "Z4" -> "AY42", + "Z5" -> "AY43", + "Z8" -> "BD42", + "Z9" -> "BD43", + "Z12" -> "AD43", + "Z13" -> "AD44", + "Z16" -> "AB43", + "Z17" -> "AB44", + "Z20" -> "AN40", + "Z21" -> "AN41", + "Z24" -> "AG40", + "Z25" -> "AG41", + "Z28" -> "AC40", + "Z29" -> "AC41", + "Z32" -> "L45", + "Z33" -> "L46", + "Z36" -> "G45", + "Z37" -> "G46" + )(fmcpPin) +} diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index 3a4cac8a..47e64de0 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -10,31 +10,46 @@ import freechips.rocketchip.config.{Parameters} import chipyard.{BuildSystem} import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ -trait HasPlatformIO { - val io_uart_bb: BundleBridgeSource[UARTPortIO] +trait HasVCU118PlatformIO { + val io_uart: Seq[UARTPortIO] + val io_spi: Seq[SPIPortIO] + val io_i2c: Seq[I2CPort] } -class VCU118Platform(override implicit val p: Parameters) extends LazyModule - with HasPlatformIO { +class VCU118Platform(override implicit val p: Parameters) extends LazyModule { val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey)(0)))) - override lazy val module = new VCU118PlatformModule(this) } -class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) { +class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) + with HasVCU118PlatformIO { - _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => - // create UART pins in Platform - //val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } - - //(io_uart_pins_temp zip sys.uart) map { case (p, r) => p <> r } - _outer.io_uart_bb.bundle <> sys.uart(0) + val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => + val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") } + (io_uart_pins_temp zip sys.uart).map { case (io, sysio) => + io <> sysio + } + io_uart_pins_temp } + val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp => + val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") } + (io_spi_pins_temp zip sys.spi).map { case (io, sysio) => + io <> sysio + } + io_spi_pins_temp + } + + val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp => + val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") } + (io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) => + io <> sysio + } + io_i2c_pins_temp + } } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 0bce7c97..31f3c0ff 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -13,14 +13,60 @@ import sifive.fpgashells.shell._ import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { - require(p(PeripheryUARTKey).size >= 1) - designParameters(UARTOverlayKey).foreach { uok => - topDesign match { case td: HasPlatformIO => - io_uart_bb)) + /*** UART ***/ + require(p(PeripheryUARTKey).size == 2) + + // 1st UART goes to the VCU118 dedicated UART + + // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design + // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).head))) + designParameters(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_uart_bb.bundle <> dutMod.io_uart.head + } + } + + // 2nd UART goes to the FMC UART + + val uart_fmc = Overlay(UARTOverlayKey, new chipyard.fpga.vcu118.bringup.BringupUARTVCU118ShellPlacer(this, UARTShellInput())) + + val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).last))) + designParameters(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_uart_bb_2.bundle <> dutMod.io_uart.last + } + } + + /*** SPI ***/ + require(p(PeripherySPIKey).size >= 1) + + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head))) + designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_spi_bb.bundle <> dutMod.io_spi.head + } + } + + /*** I2C ***/ + require(p(PeripheryI2CKey).size >= 1) + + val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput())) + + val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) + designParameters(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_i2c_bb.bundle <> dutMod.io_i2c.head } } }