From 6bd2e9dddbf4901bece51ae38408d101f3d8f1b4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 13 Oct 2023 17:36:41 -0700 Subject: [PATCH] [ci skip] Re-add suggestName for axi4 mmio mem --- generators/chipyard/src/main/scala/harness/HarnessBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 0446b783..8530bb33 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -135,7 +135,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({ class WithSimAXIMMIO extends HarnessBinder({ case (th: HasHarnessInstantiators, port: AXI4MMIOPort) => { val mmio_mem = LazyModule(new SimAXIMem(port.edge, size = port.params.size)(Parameters.empty)) - withClock(port.io.clock) { Module(mmio_mem.module) } + withClock(port.io.clock) { Module(mmio_mem.module).suggestName("mmio_mem") } mmio_mem.io_axi4.head <> port.io.bits } })