From 6c115b4234b04475fd58ae14b9f3b739589bcd40 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 25 Oct 2016 11:38:00 -0700
Subject: [PATCH] add verilator simulation

---
 testchipip                 |  2 +-
 verisim/.gitignore         |  5 ++++
 verisim/Makefile           | 52 ++++++++++++++++++++++++++++++++++++++
 verisim/Makefrag-verilator | 35 +++++++++++++++++++++++++
 4 files changed, 93 insertions(+), 1 deletion(-)
 create mode 100644 verisim/.gitignore
 create mode 100644 verisim/Makefile
 create mode 100644 verisim/Makefrag-verilator

diff --git a/testchipip b/testchipip
index a3261102..88144572 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit a326110250a3256c3ffd0ce9b39ae2c94cbf944c
+Subproject commit 8814457231da7201a873c68c5179c6bf450f95dd
diff --git a/verisim/.gitignore b/verisim/.gitignore
new file mode 100644
index 00000000..aedc2d42
--- /dev/null
+++ b/verisim/.gitignore
@@ -0,0 +1,5 @@
+simulator-*
+generated-src/
+verilator/
+DVEfiles/
+*.log
diff --git a/verisim/Makefile b/verisim/Makefile
new file mode 100644
index 00000000..2594f8d4
--- /dev/null
+++ b/verisim/Makefile
@@ -0,0 +1,52 @@
+base_dir=$(abspath ..)
+sim_dir=$(abspath .)
+
+PROJECT ?= example
+MODEL ?= TestHarness
+CONFIG ?= DefaultExampleConfig
+CFG_PROJECT ?= $(PROJECT)
+TB ?= TestDriver
+
+sim = simulator-$(PROJECT)-$(CONFIG)
+sim_debug = simulator-$(PROJECT)-$(CONFIG)-debug
+
+default: $(sim)
+
+debug: $(sim_debug)
+
+CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include
+LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
+
+include $(base_dir)/Makefrag
+include $(sim_dir)/Makefrag-verilator
+
+long_name = $(PROJECT).$(MODEL).$(CONFIG)
+
+sim_vsrcs = \
+	$(build_dir)/$(long_name).v \
+	$(base_dir)/testchipip/vsrc/SimSerial.v
+
+sim_csrcs = \
+	$(base_dir)/testchipip/csrc/SimSerial.cc \
+	$(base_dir)/testchipip/csrc/verilator-harness.cc
+
+model_dir = $(build_dir)/$(long_name)
+model_dir_debug = $(build_dir)/$(long_name).debug
+
+model_header = $(model_dir)/V$(MODEL).h
+model_header_debug = $(model_dir_debug)/V$(MODEL).h
+
+$(sim): $(sim_vsrcs) $(sim_csrcs) $(INSTALLED_VERILATOR)
+	mkdir -p $(build_dir)/$(long_name)
+	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
+	-o $(sim_dir)/$@ $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
+	-CFLAGS "-I$(build_dir) -include $(model_header)"
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
+
+
+$(sim_debug): $(sim_vsrcs) $(sim_csrcs) $(INSTALLED_VERILATOR)
+	mkdir -p $(build_dir)/$(long_name).debug
+	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
+	-o $(sim_dir)/$@ $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
+	-CFLAGS "-I$(build_dir) -include $(model_header_debug)"
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
diff --git a/verisim/Makefrag-verilator b/verisim/Makefrag-verilator
new file mode 100644
index 00000000..dd178191
--- /dev/null
+++ b/verisim/Makefrag-verilator
@@ -0,0 +1,35 @@
+# Build and install our own Verilator, to work around versionining issues.
+VERILATOR_VERSION=3.884
+VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
+INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
+$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
+	$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
+	touch $@
+
+$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
+	$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
+	touch $@
+
+$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
+	mkdir -p $(dir $@)
+	cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
+
+$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
+	rm -rf $(dir $@)
+	mkdir -p $(dir $@)
+	cat $^ | tar -xz --strip-components=1 -C $(dir $@)
+	touch $@
+
+verilator/verilator-$(VERILATOR_VERSION).tar.gz:
+	mkdir -p $(dir $@)
+	wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
+
+# Run Verilator to produce a fast binary to emulate this circuit.
+VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
+VERILATOR_FLAGS := --top-module $(MODEL) \
+  +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+  +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
+  --output-split 20000 \
+	-Wno-STMTDLY --x-assign unique \
+  -I$(base_dir)/testchipip/vsrc \
+  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/rocket-chip/csrc/verilator.h"