updated tutorial configuration files [skip ci]

vlsi/example-designs/sky130-commercial.yml

@@ -2,149 +2,18 @@
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "5ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "30ns", uncertainty: "2ns"}
 ]
 
-# Power Straps
-par.power_straps_mode: generate
-par.generate_power_straps_method: by_tracks
-par.blockage_spacing: 40.0
-par.blockage_spacing_top_layer: met4
-par.generate_power_straps_options:
-  by_tracks:
-    strap_layers:
-      - met4
-      - met5
-    pin_layers:
-      - met5
-    blockage_spacing_met2: 4.0
-    blockage_spacing_met4: 2.0
-    track_width: 3
-    track_width_met5: 1
-    track_spacing: 5
-    track_start: 10
-    track_start_met5: 1
-    power_utilization: 0.1
-    power_utilization_met4: 0.1
-    power_utilization_met5: 0.1
-
 # Placement Constraints
-vlsi.inputs.placement_constraints:
+# If overriding the placement constraints in example-sky130.yml,
-  - path: "ChipTop"
+# ensure one of the toplevel margin sides corresponding with the power pin metal layers
-    type: toplevel
+# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
-    x: 0
+# For example, in example-sky130.yml we set 
-    y: 0
+#   par.generate_power_straps_options.by_tracks.pin_layers: 'met5'  # horizontal layer
-    width: 4000
+# therefore we must also set:
-    height: 2500
+#   vlsi.inputs.placement_constraints:
-    margins:
+#     - path: "ChipTop"
-      left: 0
+#       ...
-      right: 0
+#       margins:
-      top: 0
+#         right: 0  # or left: 0
-      bottom: 0
-
-  # Place data cache SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
-    type: hardmacro
-    x: 50
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
-    type: hardmacro
-    x: 50
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
-    type: hardmacro
-    x: 50
-    y: 1900
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
-    type: hardmacro
-    x: 1000
-    y: 1900
-    orientation: r0
-
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
-    type: hardmacro
-    x: 1000
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
-    type: hardmacro
-    x: 1000
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
-    type: hardmacro
-    x: 1000
-    y: 100
-    orientation: r0
-
-  # Place instruction cache SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 3250
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
-    type: hardmacro
-    x: 3250
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
-    type: hardmacro
-    x: 3450
-    y: 1300
-    orientation: r0
-
-  # Place L2 TLB SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
-    type: hardmacro
-    x: 2000
-    y: 1300
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
-    type: hardmacro
-    x: 2000
-    y: 1900
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
-    type: hardmacro
-    x: 2750
-    y: 1300
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
-    type: hardmacro
-    x: 2750
-    y: 1900
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
-    type: hardmacro
-    x: 3460
-    y: 1900
-    orientation: "r0"
-
-# Pin placement constraints
-vlsi.inputs.pin_mode: generated
-vlsi.inputs.pin.generate_mode: semi_auto
-vlsi.inputs.pin.assignments: [
-  {pins: "*", layers: ["met2", "met4"], side: "bottom"}
-]

vlsi/example-designs/sky130-openroad.yml

@@ -3,88 +3,37 @@
 # Specify clock signals
 # Relax the clock period for OpenROAD to meet timing
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "30ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "50ns", uncertainty: "2ns"}
 ]
 
-# Placement Constraints
+# Flow parameters that yield a routable design with reasonable timing
-vlsi.inputs.placement_constraints:
+par.openroad:
-  - path: "ChipTop"
+  timing_driven: true  # set to false to drastically speed up runs
-    type: toplevel
+  create_archive_mode: none
-    x: 0
-    y: 0
-    width: 4000
-    height: 2500
-    margins:
-      left: 10
-      right: 10
-      top: 10
-      bottom: 10
 
- # Place data cache SRAM instances
+  write_reports: true  # set to false to slightly speed up runs
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 100
-    orientation: r0
 
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
+  floorplan_mode: generate
-    type: hardmacro
-    x: 50
-    y: 700
-    orientation: r0
 
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
+  macro_placement.halo: [50, 50]
-    type: hardmacro
-    x: 50
-    y: 1300
-    orientation: r0
 
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
+  global_placement.timing_driven: true
-    type: hardmacro
+  global_placement.routability_driven: true
-    x: 50
-    y: 1900
-    orientation: r0
 
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
+  global_placement.placement_padding: 6
-    type: hardmacro
+  detailed_placement.placement_padding: 4
-    x: 1000
+  clock_tree.placement_padding: 2
-    y: 1900
+  clock_tree_resize.placement_padding: 0
-    orientation: r0
 
+  clock_tree_resize.setup_margin: 0.0
+  clock_tree_resize.hold_margin: 0.20
+  global_route_resize.hold_margin: 0.60
+  clock_tree_resize.hold_max_buffer_percent: 80  
 
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
+  global_placement.routing_adjustment: 0.5
-    type: hardmacro
+  global_route.routing_adjustment: 0.3
-    x: 1000
+  global_route_resize.routing_adjustment: 0.2
-    y: 1300
-    orientation: r0
 
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
+# DRC/LVS configuration
-    type: hardmacro
+drc.magic.generate_only: true
-    x: 1000
+lvs.netgen.generate_only: true
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
-    type: hardmacro
-    x: 1000
-    y: 100
-    orientation: r0
-
-  # Place instruction cache SRAM instances
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
-    type: hardmacro
-    x: 3250
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
-    type: hardmacro
-    x: 3250
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
-    type: hardmacro
-    x: 3450
-    y: 1300
-    orientation: r0

vlsi/example-sky130.yml

@@ -20,31 +20,70 @@ vlsi.inputs.power_spec_type: "cpf"
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "10ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "20ns", uncertainty: "1ns"}
 ]
 
 # Generate Make include to aid in flow
 vlsi.core.build_system: make
 
+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
   - path: "ChipTop"
     type: toplevel
     x: 0
     y: 0
-    width: 3500
+    width: 4000
-    height: 2500
+    height: 3000
     margins:
       left: 10
-      right: 10
+      right: 0
       top: 10
       bottom: 10
 
+  # Place SRAM memory instances
+    # data cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 450
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 850
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1250
+    orientation: r90
+ 
+  # tag array
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90
+
+
 # Power Straps
 par.power_straps_mode: generate
 par.generate_power_straps_method: by_tracks
-par.blockage_spacing: 40.0
+par.blockage_spacing: 2.0
-par.blockage_spacing_top_layer: met4
+par.blockage_spacing_top_layer: met3
 par.generate_power_straps_options:
   by_tracks:
     strap_layers:
@@ -63,6 +102,7 @@ par.generate_power_straps_options:
     power_utilization_met4: 0.1
     power_utilization_met5: 0.1
 
+
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
 vlsi.inputs.pin.generate_mode: semi_auto
@@ -70,5 +110,6 @@ vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["met2", "met4"], side: "bottom"}
 ]
 
+
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"

vlsi/tutorial.mk

@@ -1,10 +1,7 @@
 #########################################################################################
 # makefile variables for Hammer tutorials
 #########################################################################################
-# tutorial ?= none
+tutorial ?= none
-tutorial ?= sky130-openroad
-
-extra ?=
 
 # TODO: eventually have asap7 commercial/openroad tutorial flavors
 ifeq ($(tutorial),asap7)
@@ -39,5 +36,3 @@ ifeq ($(tutorial),sky130-openroad)
     # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
     ENABLE_YOSYS_FLOW  = 1
 endif
-
-HAMMER_EXTRA_ARGS      ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)