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Fix removal of axi4mem for ChipLikeRocketConfig

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This commit is contained in:
Jerry Zhao
2023-10-26 11:27:03 -07:00
parent 228d9351f8
commit 6f17292e85
1 changed files with 1 additions and 1 deletions
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generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -24,7 +24,7 @@ class ChipLikeRocketConfig extends Config(
//================================== //==================================
new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO
new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
//================================== //==================================