From 784bff266670ea08b7b420aec1b958fa0b01b859 Mon Sep 17 00:00:00 2001
From: Colin Schmidt <colins@berkeley.edu>
Date: Wed, 16 Oct 2019 08:12:52 -0700
Subject: [PATCH 1/2] [docs][ci skip] Remove extra backticks in docs

Also fix sram-cache error. Fixes #299
---
 docs/VLSI/Tutorial.rst | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst
index 66a2f220..a0a9c1ae 100644
--- a/docs/VLSI/Tutorial.rst
+++ b/docs/VLSI/Tutorial.rst
@@ -64,7 +64,7 @@ In the Chipyard root, run:
 
 .. code-block:: shell
 
-    ``./scripts/init-vlsi.sh asap7`` 
+    ./scripts/init-vlsi.sh asap7
     
 to pull the Hammer & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
 
@@ -82,7 +82,8 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u
 
 .. code-block:: shell
 
-    make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
+    export MACROCOMPILER_MODE='--mode synflops'
+    make buildfile CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
 
 The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches).
 
@@ -111,7 +112,7 @@ Synthesis
 ^^^^^^^^^
 .. code-block:: shell
 
-    ``make syn``
+    make syn
 
 Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
 
@@ -119,7 +120,7 @@ Place-and-Route
 ^^^^^^^^^^^^^^^
 .. code-block:: shell
 
-    ``make par``
+    make par
 
 After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
 
@@ -131,7 +132,7 @@ Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped
 
 .. code-block:: shell
 
-    ``python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds``
+    python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds
 
 By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names.
 

From b0b6466c22218b3bb3dc307227f19b365ddf32ed Mon Sep 17 00:00:00 2001
From: Colin Schmidt <colins@berkeley.edu>
Date: Wed, 16 Oct 2019 10:32:56 -0700
Subject: [PATCH 2/2] handle asap7 lack of memories in makefile

---
 docs/VLSI/Tutorial.rst | 5 ++---
 vlsi/Makefile          | 6 +++++-
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst
index a0a9c1ae..406cee46 100644
--- a/docs/VLSI/Tutorial.rst
+++ b/docs/VLSI/Tutorial.rst
@@ -82,10 +82,9 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u
 
 .. code-block:: shell
 
-    export MACROCOMPILER_MODE='--mode synflops'
-    make buildfile CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
+    make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
 
-The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches).
+The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches). This change is automatically inferred by the makefile but is included here for completeness.
 
 The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module.
 
diff --git a/vlsi/Makefile b/vlsi/Makefile
index cc61b957..567090da 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -23,7 +23,11 @@ tech_dir           ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
 SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
 SMEMS_HAMMER       ?= $(build_dir)/$(long_name).mems.hammer.json
-MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
+ifeq ($(tech_name),asap7)
+	MACROCOMPILER_MODE ?= --mode synflops
+else
+	MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
+endif
 OBJ_DIR            ?= $(vlsi_dir)/build
 ENV_YML            ?= $(vlsi_dir)/env.yml
 INPUT_CONFS        ?= example.yml