diff --git a/.github/actions/run-tests/action.yml b/.github/actions/run-tests/action.yml index d74b18af..05cc6498 100644 --- a/.github/actions/run-tests/action.yml +++ b/.github/actions/run-tests/action.yml @@ -17,7 +17,7 @@ runs: using: "composite" steps: - name: Init submodules (since only the RTL is cached) - run: ./scripts/init-submodules-no-riscv-tools.sh + run: ./scripts/init-submodules-no-riscv-tools.sh --skip-validate shell: bash # Note: You shouldn't need the other inputs since it shouldn't build RTL from scratch diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index e056921d..70fbdaab 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -9,6 +9,7 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh +# enter bhd repo cd $LOCAL_CHIPYARD_DIR # ignore the private vlsi submodules @@ -16,15 +17,16 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none -# initialize submodules and get the hashes -git submodule update --init -status=$(git submodule status) - all_names=() search_submodule() { echo "Running check on submodule $submodule in $dir" + # Initialize submodule and get the hashes + git submodule update --init $dir/$submodule + git -C $dir/$submodule fetch --unshallow + + status=$(git submodule status) hash=$(echo "$status" | grep "$dir.*$submodule " | awk '{print$1}' | grep -o "[[:alnum:]]*") for branch in "${branches[@]}" do @@ -47,9 +49,9 @@ search () { done } -submodules=("cva6" "ibex" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") dir="generators" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master" "main") else @@ -81,7 +83,7 @@ search submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017") dir="software" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master") else @@ -91,7 +93,7 @@ search submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "torture") dir="tools" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master") else @@ -106,7 +108,7 @@ search submodules=("firesim") dir="sims" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master") else diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index a5268288..1f4251b1 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -15,7 +15,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh cd $REMOTE_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh +./scripts/init-submodules-no-riscv-tools.sh --skip-validate ./scripts/init-fpga.sh TOOLS_DIR=$REMOTE_RISCV_DIR diff --git a/.github/scripts/remote-run-firesim-scala-tests.sh b/.github/scripts/remote-run-firesim-scala-tests.sh index 732cb59d..6fe52586 100755 --- a/.github/scripts/remote-run-firesim-scala-tests.sh +++ b/.github/scripts/remote-run-firesim-scala-tests.sh @@ -18,7 +18,7 @@ export PATH="$RISCV/bin:$PATH" # This would generally be handled by build-setup.sh/firesim-setup.sh REMOTE_FIRESIM_SYSROOT=$REMOTE_FIRESIM_DIR/lib-install -./scripts/init-submodules-no-riscv-tools.sh +./scripts/init-submodules-no-riscv-tools.sh --skip-validate cd $REMOTE_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib git submodule update --init elfutils libdwarf cd $REMOTE_CHIPYARD_DIR/sims/firesim diff --git a/.gitmodules b/.gitmodules index 6f45793b..d2d618ab 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,36 +1,47 @@ [submodule "rocket-chip"] path = generators/rocket-chip - url = https://github.com/ucb-bar/rocket-chip.git + url = https://github.com/chipsalliance/rocket-chip.git + shallow = true [submodule "testchipip"] path = generators/testchipip url = https://github.com/ucb-bar/testchipip.git + shallow = true [submodule "barstools"] path = tools/barstools url = https://github.com/ucb-bar/barstools.git + shallow = true [submodule "tools/torture"] path = tools/torture url = https://github.com/ucb-bar/riscv-torture.git + shallow = true [submodule "generators/boom"] path = generators/boom url = https://github.com/riscv-boom/riscv-boom.git + shallow = true [submodule "generators/sifive-blocks"] path = generators/sifive-blocks url = https://github.com/sifive/sifive-blocks.git + shallow = true [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git + shallow = true [submodule "sims/firesim"] path = sims/firesim url = https://github.com/firesim/firesim.git + shallow = true [submodule "generators/icenet"] path = generators/icenet url = https://github.com/firesim/icenet.git + shallow = true [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache url = https://github.com/sifive/block-inclusivecache-sifive.git + shallow = true [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git + shallow = true [submodule "toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt"] path = toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt url = https://github.com/ucb-bar/chipyard-toolchain-prebuilt.git @@ -38,99 +49,132 @@ [submodule "toolchains/riscv-tools/riscv-isa-sim"] path = toolchains/riscv-tools/riscv-isa-sim url = https://github.com/riscv/riscv-isa-sim.git + shallow = true [submodule "toolchains/riscv-tools/riscv-pk"] path = toolchains/riscv-tools/riscv-pk url = https://github.com/riscv/riscv-pk.git + shallow = true [submodule "toolchains/riscv-tools/riscv-tests"] path = toolchains/riscv-tools/riscv-tests url = https://github.com/riscv/riscv-tests.git + shallow = true [submodule "toolchains/riscv-tools/riscv-openocd"] path = toolchains/riscv-tools/riscv-openocd url = https://github.com/riscv/riscv-openocd.git + shallow = true [submodule "toolchains/esp-tools/riscv-gnu-toolchain"] path = toolchains/esp-tools/riscv-gnu-toolchain url = https://github.com/ucb-bar/esp-gnu-toolchain.git + shallow = true [submodule "toolchains/esp-tools/riscv-isa-sim"] path = toolchains/esp-tools/riscv-isa-sim url = https://github.com/ucb-bar/esp-isa-sim.git + shallow = true [submodule "toolchains/esp-tools/riscv-pk"] path = toolchains/esp-tools/riscv-pk url = https://github.com/riscv/riscv-pk.git + shallow = true [submodule "toolchains/esp-tools/riscv-tests"] path = toolchains/esp-tools/riscv-tests url = https://github.com/ucb-bar/esp-tests.git + shallow = true [submodule "toolchains/libgloss"] path = toolchains/libgloss url = https://github.com/ucb-bar/libgloss-htif.git + shallow = true [submodule "vlsi/hammer"] path = vlsi/hammer url = https://github.com/ucb-bar/hammer.git + shallow = true [submodule "tools/dsptools"] path = tools/dsptools url = https://github.com/ucb-bar/dsptools.git + shallow = true [submodule "tools/chisel-testers"] path = tools/chisel-testers url = https://github.com/freechipsproject/chisel-testers.git + shallow = true [submodule "generators/sha3"] path = generators/sha3 url = https://github.com/ucb-bar/sha3.git + shallow = true [submodule "vlsi/hammer-cadence-plugins"] path = vlsi/hammer-cadence-plugins url = https://github.com/ucb-bar/hammer-cadence-plugins.git + shallow = true [submodule "vlsi/hammer-synopsys-plugins"] path = vlsi/hammer-synopsys-plugins url = https://github.com/ucb-bar/hammer-synopsys-plugins.git + shallow = true [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins url = https://github.com/ucb-bar/hammer-mentor-plugins.git + shallow = true [submodule "toolchains/qemu"] path = toolchains/qemu url = https://github.com/qemu/qemu.git + shallow = true [submodule "tools/axe"] path = tools/axe url = https://github.com/CTSRD-CHERI/axe.git + shallow = true [submodule "software/spec2017"] path = software/spec2017 url = https://github.com/ucb-bar/spec2017-workload.git + shallow = true [submodule "software/coremark"] path = software/coremark url = https://github.com/ucb-bar/coremark-workload.git + shallow = true [submodule "generators/gemmini"] path = generators/gemmini url = https://github.com/ucb-bar/gemmini + shallow = true [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git + shallow = true [submodule "generators/cva6"] path = generators/cva6 url = https://github.com/ucb-bar/cva6-wrapper.git + shallow = true [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git + shallow = true [submodule "generators/nvdla"] path = generators/nvdla url = https://github.com/ucb-bar/nvdla-wrapper.git + shallow = true [submodule "software/nvdla-workload"] path = software/nvdla-workload url = https://github.com/ucb-bar/nvdla-workload.git + shallow = true [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/riscv-boom/dromajo.git + shallow = true [submodule "generators/riscv-sodor"] path = generators/riscv-sodor url = https://github.com/ucb-bar/riscv-sodor.git + shallow = true [submodule "fpga/fpga-shells"] path = fpga/fpga-shells url = https://github.com/sifive/fpga-shells.git + shallow = true [submodule "tools/api-config-chipsalliance"] path = tools/api-config-chipsalliance url = https://github.com/chipsalliance/api-config-chipsalliance.git + shallow = true [submodule "tools/rocket-dsp-utils"] path = tools/rocket-dsp-utils url = https://github.com/ucb-bar/rocket-dsp-utils + shallow = true [submodule "generators/ibex"] path = generators/ibex url = https://github.com/ucb-bar/ibex-wrapper + shallow = true [submodule "generators/fft-generator"] path = generators/fft-generator url = https://github.com/ucb-bar/FFTGenerator.git + shallow = true diff --git a/.readthedocs.yml b/.readthedocs.yml index 43e2d306..51959f5a 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -1,7 +1,16 @@ version: 2 + +build: + os: ubuntu-20.04 + tools: + python: "3.6" + formats: all + sphinx: - configuration: docs/conf.py + configuration: docs/conf.py + fail_on_warning: true + python: - install: - - requirements: docs/requirements.txt + install: + - requirements: docs/requirements.txt diff --git a/build.sbt b/build.sbt index 2808adb1..9d0a7ac0 100644 --- a/build.sbt +++ b/build.sbt @@ -6,10 +6,10 @@ lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", - version := "1.3", + version := "1.6", scalaVersion := "2.12.10", - test in assembly := {}, - assemblyMergeStrategy in assembly := { _ match { + assembly / test := {}, + assembly / assemblyMergeStrategy := { _ match { case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), @@ -48,8 +48,8 @@ lazy val firesimDir = if (firesimAsLibrary) { def freshProject(name: String, dir: File): Project = { Project(id = name, base = dir / "src") .settings( - scalaSource in Compile := baseDirectory.value / "main" / "scala", - resourceDirectory in Compile := baseDirectory.value / "main" / "resources" + Compile / scalaSource := baseDirectory.value / "main" / "scala", + Compile / resourceDirectory := baseDirectory.value / "main" / "resources" ) } @@ -60,25 +60,19 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.4.4" +val chiselVersion = "3.5.1" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion), addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) -val firrtlVersion = "1.4.4" +val firrtlVersion = "1.5.1" lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion)) -// In some projects we override the default versions of Chisel and friends. -// This map captures the expected defaults used by projects under Chipyard. -lazy val chipyardMandatedVersions = Map( - "chisel-iotesters" -> "1.5.4", - "firrtl-interpreter" -> "1.4.4", - "treadle" -> "1.3.4", - "chisel3" -> chiselVersion, - "firrtl" -> firrtlVersion -) +val chiselTestVersion = "2.5.1" + +lazy val chiselTestSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel-iotesters" % chiselTestVersion)) // Subproject definitions begin @@ -138,19 +132,6 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) // -- Chipyard-managed External Projects -- -// Because we're not using a release version of iotesters to work around a -// scala test version problem, override it's libdeps to prevent using snapshots -lazy val chisel_testers = (project in file("tools/chisel-testers")) - .settings(chiselSettings) - .settings( - allDependencies := allDependencies.value.map { - case dep if chipyardMandatedVersions.isDefinedAt(dep.name) => - dep.organization %% dep.name % chipyardMandatedVersions(dep.name) - case o => o - }) - -// -- Normal Projects -- - // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") @@ -209,13 +190,15 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(commonSettings) lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) + .dependsOn(rocketchip, midasTargetUtils) .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(chiselTestSettings) .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(testchipip, rocketchip, chisel_testers) + .dependsOn(testchipip, rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(chiselTestSettings) .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) @@ -223,26 +206,24 @@ lazy val nvdla = (project in file("generators/nvdla")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val iocell = (project in file("./tools/barstools/iocell/")) +lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "src") + .settings( + Compile / scalaSource := baseDirectory.value / "main" / "scala" / "barstools" / "iocell", + Compile / resourceDirectory := baseDirectory.value / "main" / "resources" + ) .settings(chiselSettings) .settings(commonSettings) -lazy val tapeout = (project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources - .settings(commonSettings) - -lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings(commonSettings) - -lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) - .dependsOn(mdf) +lazy val tapeout = (project in file("./tools/barstools/")) + .settings(chiselSettings) + .settings(chiselTestSettings) .enablePlugins(sbtassembly.AssemblyPlugin) - .settings(firrtlSettings) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .dependsOn(chisel_testers) .settings( + chiselSettings, + chiselTestSettings, commonSettings, libraryDependencies ++= Seq( "org.scalatest" %% "scalatest" % "3.2.+" % "test", @@ -273,7 +254,7 @@ lazy val sifive_blocks = (project in file("generators/sifive-blocks")) lazy val sifive_cache = (project in file("generators/sifive-cache")) .settings( commonSettings, - scalaSource in Compile := baseDirectory.value / "design/craft") + Compile / scalaSource := baseDirectory.value / "design/craft") .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) @@ -284,9 +265,10 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( + chiselSettings, commonSettings, - testGrouping in Test := isolateAllTests( (definedTests in Test).value ), - testOptions in Test += Tests.Argument("-oF") + Test / testGrouping := isolateAllTests( (Test / definedTests).value ), + Test / testOptions += Tests.Argument("-oF") ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .dependsOn(rocketchip, sifive_blocks) diff --git a/common.mk b/common.mk index d055f784..1993c475 100644 --- a/common.mk +++ b/common.mk @@ -71,7 +71,7 @@ else lookup_srcs = $(shell fd -L ".*\.$(2)" $(1)) endif -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools fpga/fpga-shells fpga/src) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources @@ -135,6 +135,7 @@ $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,\ + --allow-unrecognized-annotations \ --output-file $(TOP_FILE) \ --harness-o $(HARNESS_FILE) \ --input-file $(FIRRTL_FILE) \ @@ -162,7 +163,7 @@ $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): top_macro_temp @echo "" > /dev/null top_macro_temp: $(TOP_SMEMS_CONF) - $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)) HARNESS_MACROCOMPILER_MODE = --mode synflops .INTERMEDIATE: harness_macro_temp @@ -170,7 +171,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): harness_macro_temp @echo "" > /dev/null harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp - $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)) ######################################################################################## # remove duplicate files and headers in list of simulation file inputs diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 1194009f..2638d852 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -29,13 +29,17 @@ Setting up the Chipyard Repo Start by fetching Chipyard's sources. Run: -.. code-block:: shell +.. parsed-literal:: git clone https://github.com/ucb-bar/chipyard.git cd chipyard + # checkout latest official chipyard release + # note: this may not be the latest release if the documentation version != "stable" + git checkout |version| ./scripts/init-submodules-no-riscv-tools.sh This will initialize and checkout all of the necessary git submodules. +This will also validate that you are on a tagged branch, otherwise it will prompt for confirmation. When updating Chipyard to a new version, you will also want to rerun this script to update the submodules. Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior. diff --git a/docs/conf.py b/docs/conf.py index f78001c8..acf781f5 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -20,6 +20,8 @@ # import sys # sys.path.insert(0, os.path.abspath('.')) +import os +import subprocess # -- General configuration ------------------------------------------------ @@ -59,11 +61,32 @@ author = u'Berkeley Architecture Research' # The version info for the project you're documenting, acts as replacement for # |version| and |release|, also used in various other places throughout the # built documents. -# -# The short X.Y version. -version = u'' -# The full version, including alpha/beta/rc tags. -release = u'' + +on_rtd = os.environ.get("READTHEDOCS") == "True" +if on_rtd: + for item, value in os.environ.items(): + print("[READTHEDOCS] {} = {}".format(item, value)) + +if on_rtd: + rtd_version = os.environ.get("READTHEDOCS_VERSION") + if rtd_version == "latest": + version = "main" # TODO: default to what "latest" points to + elif rtd_version == "stable": + # get the latest git tag (which is what rtd normally builds under "stable") + # this works since rtd builds things within the repo + process = subprocess.Popen(["git", "describe", "--exact-match", "--tags"], stdout=subprocess.PIPE) + output = process.communicate()[0].decode("utf-8").strip() + if process.returncode == 0: + version = output + else: + version = "v?.?.?" # this should not occur as "stable" is always pointing to tagged version + else: + version = rtd_version # name of a branch +else: + version = "v?.?.?" + +# for now make these match +release = version # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. @@ -132,6 +155,17 @@ html_logo = '_static/images/chipyard-logo.png' # Output file base name for HTML help builder. htmlhelp_basename = 'Chipyarddoc' +# -- Misc Options --------------------------------------------------------- + +html_context = { + "version": version +} + +# add rst to end of each rst source file +# can put custom strings here that are generated from this file +rst_epilog = f""" +.. |overall_version| replace:: {version} +""" # -- Options for LaTeX output --------------------------------------------- diff --git a/docs/index.rst b/docs/index.rst index 3e0db05a..48791642 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,10 +1,5 @@ -.. Chipyard documentation master file, created by - sphinx-quickstart on Fri Mar 8 11:46:38 2019. - You can adapt this file completely to your liking, but it should at least - contain the root `toctree` directive. - -Welcome to Chipyard's documentation! -==================================== +Welcome to Chipyard's documentation (version "|version|")! +========================================================== .. image:: ./_static/images/chipyard-logo.svg diff --git a/generators/boom b/generators/boom index e1a70afe..ad64c541 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit e1a70afed7de77f6ba9f6e501de71f7f41afc47c +Subproject commit ad64c5419151e5e886daee7084d8399713b46b4b diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 30a29bcb..8c2a7365 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -72,8 +72,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) := ClockGroupCombiner() := ClockGroupResetSynchronizer() - := TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) - := TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) + := prci_ctrl_domain { TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) } + := prci_ctrl_domain { TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) } := allClockGroupsNode) } diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 1888fc5a..b1719773 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -142,9 +142,9 @@ class LoopbackNICRocketConfig extends Config( // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( new testchipip.WithSerialPBusMem ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new chipyard.config.WithL2TLBs(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala index c351a4dd..a9885d34 100644 --- a/generators/chipyard/src/main/scala/example/InitZero.scala +++ b/generators/chipyard/src/main/scala/example/InitZero.scala @@ -52,7 +52,7 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) { state := s_resp } - when (mem.d.fire()) { + when (mem.d.fire) { state := Mux(bytesLeft === 0.U, s_done, s_write) } } diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index fad51c01..97294428 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -28,6 +28,7 @@ case class MyCoreParams( enableToFromHostCaching: Boolean = false, ) extends CoreParams { val useVM: Boolean = true + val useHypervisor: Boolean = false val useUser: Boolean = true val useSupervisor: Boolean = false val useDebug: Boolean = true @@ -41,6 +42,7 @@ case class MyCoreParams( val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket val nLocalInterrupts: Int = 0 val useNMI: Boolean = false + val nPTECacheEntries: Int = 0 // TODO: Check val nPMPs: Int = 0 // TODO: Check val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index ed16b25d..f45b318c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -25,8 +25,6 @@ case object GenericFIRKey extends Field[Option[GenericFIRParams]](None) class GenericFIRCellBundle[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { val data: T = genIn.cloneType val carry: T = genOut.cloneType - - override def cloneType: this.type = GenericFIRCellBundle(genIn, genOut).asInstanceOf[this.type] } object GenericFIRCellBundle { def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellBundle[T] = new GenericFIRCellBundle(genIn, genOut) @@ -43,8 +41,6 @@ object GenericFIRCellIO { class GenericFIRBundle[T<:Data:Ring](proto: T) extends Bundle { val data: T = proto.cloneType - - override def cloneType: this.type = GenericFIRBundle(proto).asInstanceOf[this.type] } object GenericFIRBundle { def apply[T<:Data:Ring](proto: T): GenericFIRBundle[T] = new GenericFIRBundle(proto) @@ -119,7 +115,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { // When a new transaction is ready on the input, we will have new data to output // next cycle. Take this data in - when (io.in.fire()) { + when (io.in.fire) { hasNewData := 1.U inputReg := io.in.bits.data } @@ -127,7 +123,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { // We should output data when our cell has new data to output and is ready to // recieve new data. This insures that every cell in the chain passes its data // on at the same time - io.out.valid := hasNewData & io.in.fire() + io.out.valid := hasNewData & io.in.fire io.out.bits.data := inputReg // Compute carry diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 923f12e2..fe02c996 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -26,8 +26,6 @@ case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughPar class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle { val data: T = proto.cloneType - - override def cloneType: this.type = StreamingPassthroughBundle(proto).asInstanceOf[this.type] } object StreamingPassthroughBundle { def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala index 7d293c36..da9311bf 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala @@ -10,6 +10,5 @@ trait ChipyardCli { this: Shell => parser.note("Chipyard Generator Options") Seq( UnderscoreDelimitedConfigsAnnotation - ) - .foreach(_.addOptions(parser)) + ).foreach(_.addOptions(parser)) } diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index 4e429618..a830c3a8 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.system.RocketChipStage import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} import firrtl.options.phases.DeletedWrapper -class ChipyardStage extends ChiselStage with PreservesAll[Phase] { +class ChipyardStage extends ChiselStage { override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli override val targets: Seq[PhaseDependency] = Seq( Dependency[freechips.rocketchip.stage.phases.Checks], @@ -33,4 +33,5 @@ class ChipyardStage extends ChiselStage with PreservesAll[Phase] { Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], ) + override final def invalidates(a: Phase): Boolean = false } diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 177d26b0..25a6fa61 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -22,7 +22,7 @@ import freechips.rocketchip.tile.XLen import chipyard.TestSuiteHelper import chipyard.TestSuitesKey -class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { +class AddDefaultTests extends Phase with HasRocketChipStageUtils { // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). override val prerequisites = Seq( @@ -52,4 +52,6 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance addTestSuiteAnnotations ++ oAnnos } + + override final def invalidates(a: Phase): Boolean = false } diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala index 0ed5ec11..e0796db5 100644 --- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -21,7 +21,7 @@ trait MakefragSnippet { self: Annotation => case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable /** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */ -class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { +class GenerateTestSuiteMakefrags extends Phase with HasRocketChipStageUtils { // Our annotations tend not to be serializable, but are not marked as such. override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], @@ -46,4 +46,6 @@ class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with Has writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString) outputAnnotations } + + override final def invalidates(a: Phase): Boolean = false } diff --git a/generators/cva6 b/generators/cva6 index 47173903..705c48a1 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 4717390310f8cf14f608e2a1d72d5c6f6a9ffc0f +Subproject commit 705c48a1dacc011cef9b4d021a88b4948e7f9b64 diff --git a/generators/fft-generator b/generators/fft-generator index b9f1c085..4c335ff6 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit b9f1c085afa25e1688d5acbd3f252882d511b90e +Subproject commit 4c335ff6aba3734fcc373548ea39f4c798f70cea diff --git a/generators/gemmini b/generators/gemmini index 72461235..c47cb7f3 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 72461235cc955a48f45ae3fefc7dfd68e27bc284 +Subproject commit c47cb7f3eb5c18390f176f3a53c43c8546d487d2 diff --git a/generators/hwacha b/generators/hwacha index 62c01f5a..7cc63543 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 62c01f5a8858aa1b827f0f9372a4392d7b596fca +Subproject commit 7cc6354351457c6b5bf186cdd34297ee5caeb22a diff --git a/generators/ibex b/generators/ibex index bdf41a05..0eac465e 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit bdf41a05484e57afa4ed20b35beff80320cfdd02 +Subproject commit 0eac465e3e9e06eceba111b4b43d5178ede817c2 diff --git a/generators/icenet b/generators/icenet index 084ca507..e14c1e8c 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 084ca5070605ea7919358f917289cca240d0289a +Subproject commit e14c1e8c54851d3fa7bc55fbbc6fc48873a3b2a9 diff --git a/generators/nvdla b/generators/nvdla index b2b78c9f..2b17011b 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit b2b78c9f892a6196634eb3f1fbc443436c897a00 +Subproject commit 2b17011b266025704b958efeeca2363c0cdd446d diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 50a4925d..5643a8e2 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 50a4925d5aeaf0d294fcb8d25f989736abd7c35a +Subproject commit 5643a8e245d562647f626295ad2dab9b4d5f6a13 diff --git a/generators/rocket-chip b/generators/rocket-chip index a7b016e4..114325b2 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit a7b016e46e22e4fdc013357051e30511f80df082 +Subproject commit 114325b27cfe5312c86a8a325b187be9455a62af diff --git a/generators/sha3 b/generators/sha3 index 63eda826..88ada85a 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 63eda8268c16c502cada9944ae41b584e6e32789 +Subproject commit 88ada85a84253434ea5cef729d90cd74796aa442 diff --git a/generators/testchipip b/generators/testchipip index 5917176c..52027a04 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5917176c911cec667655984c2adc566aa404f4fe +Subproject commit 52027a049f7810013e5940a1c115ff83127c1a96 diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 712cffc1..93d3c2c9 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -66,10 +66,10 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) tracegen_uop.ctrl.is_sta := isWrite(io.tracegen.req.bits.cmd) tracegen_uop.ctrl.is_std := isWrite(io.tracegen.req.bits.cmd) - io.lsu.dis_uops(0).valid := io.tracegen.req.fire() + io.lsu.dis_uops(0).valid := io.tracegen.req.fire io.lsu.dis_uops(0).bits := tracegen_uop - when (io.tracegen.req.fire()) { + when (io.tracegen.req.fire) { rob_tail := WrapInc(rob_tail, rob_sz) rob_bsy(rob_tail) := true.B rob_uop(rob_tail) := tracegen_uop @@ -111,7 +111,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) assert(!io.lsu.lxcpt.valid) - io.lsu.exe(0).req.valid := RegNext(io.tracegen.req.fire()) + io.lsu.exe(0).req.valid := RegNext(io.tracegen.req.fire) io.lsu.exe(0).req.bits := DontCare io.lsu.exe(0).req.bits.uop := RegNext(tracegen_uop) io.lsu.exe(0).req.bits.addr := RegNext(io.tracegen.req.bits.addr) @@ -158,7 +158,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) io.lsu.rob_head_idx := rob_head - + io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy } case class BoomTraceGenTileAttachParams( @@ -236,6 +236,7 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) ptw.io.requestors.head <> lsu.io.ptw outer.dcache.module.io.lsu <> lsu.io.dmem boom_shim.io.tracegen <> tracegen.io.mem + tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered boom_shim.io.lsu <> lsu.io.core // Normally the PTW would use this port diff --git a/project/build.properties b/project/build.properties index dbae93bc..10fd9eee 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.4.9 +sbt.version=1.5.5 diff --git a/project/plugins.sbt b/project/plugins.sbt index 026b95e9..e9f7f4e1 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,14 +1,2 @@ -addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") -addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") -addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") -addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0") -addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") -addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") -addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") -addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") -addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") -addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") -addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") -addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) diff --git a/scripts/check-tracegen.sh b/scripts/check-tracegen.sh index 3ba63067..947e7312 100755 --- a/scripts/check-tracegen.sh +++ b/scripts/check-tracegen.sh @@ -13,7 +13,7 @@ AXE_SHRINK=${AXE_DIR}/src/axe-shrink.py PATH=$PATH:${AXE_DIR}/src grep '.*:.*#.*@' $1 > /tmp/clean-trace.txt -"$TO_AXE" /tmp/clean-trace.txt > /tmp/trace.axe +python2 "$TO_AXE" /tmp/clean-trace.txt > /tmp/trace.axe result=$("$AXE" check wmo /tmp/trace.axe) if [ "$result" != OK ]; then diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index a110cb61..a7f265f1 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -13,5 +13,5 @@ cd "${scripts_dir}/.." # Reenable the FireSim submodule git config --unset submodule.sims/firesim.update || true cd sims/firesim -./build-setup.sh "$@" --library +./build-setup.sh "$@" --library --skip-validate cd "$RDIR" diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 6f9202f0..86420ac6 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -4,6 +4,34 @@ set -e set -o pipefail +SKIP_VALIDATE=false + +function usage +{ + echo "Usage: $0 [--skip-validate]" + echo "Initialize Chipyard submodules and setup initial env.sh script." + echo "" + echo " --skip-validate Skip prompt checking for tagged release" +} + +while test $# -gt 0 +do + case "$1" in + --skip-validate) + SKIP_VALIDATE=true; + ;; + -h | -H | --help) + usage + exit 1 + ;; + *) echo "ERROR: bad argument $1" + usage + exit 2 + ;; + esac + shift +done + # Check that git version is at least 1.7.8 MYGIT=$(git --version) MYGIT=${MYGIT#'git version '} # Strip prefix @@ -17,6 +45,21 @@ if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then false fi +# before doing anything verify that you are on a release branch/tag +set +e +tag=$(git describe --exact-match --tags) +tag_ret_code=$? +set -e +if [ $tag_ret_code -ne 0 ]; then + if [ "$SKIP_VALIDATE" = false ]; then + read -p "WARNING: You are not on an official release of Chipyard.\nType \"y\" to continue if this is intended, otherwise see https://chipyard.readthedocs.io/en/stable/Chipyard-Basics/Initial-Repo-Setup.html#setting-up-the-chipyard-repo: " validate + [[ $validate == [yY] ]] || exit 3 + echo "Setting up non-official Chipyard release" + fi +else + echo "Setting up official Chipyard release: $tag" +fi + # On macOS, use GNU readlink from 'coreutils' package in Homebrew/MacPorts if [ "$(uname -s)" = "Darwin" ] ; then READLINK=greadlink diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index bc67c91b..a701ecf1 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,28 +1,30 @@ diff --git a/build.sbt b/build.sbt -index 2187fe12..2319fc95 100644 +index bbbb8251..b7adcb73 100644 --- a/build.sbt +++ b/build.sbt -@@ -162,7 +162,7 @@ lazy val testchipip = (project in file("generators/testchipip")) +@@ -143,7 +143,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches -+ //sha3, // On separate line to allow for cleaner tutorial-setup patches ++// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, - gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex) + gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator) .settings(libraryDependencies ++= rocketLibDeps.value) -@@ -203,10 +203,10 @@ lazy val sodor = (project in file("generators/riscv-sodor")) +@@ -189,11 +189,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sha3 = (project in file("generators/sha3")) -- .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +- .dependsOn(rocketchip, midasTargetUtils) - .settings(libraryDependencies ++= rocketLibDeps.value) +- .settings(chiselTestSettings) - .settings(commonSettings) +//lazy val sha3 = (project in file("generators/sha3")) -+// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .dependsOn(rocketchip, midasTargetUtils) +// .settings(libraryDependencies ++= rocketLibDeps.value) ++// .settings(chiselTestSettings) +// .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(testchipip, rocketchip, chisel_testers) + .dependsOn(testchipip, rocketchip) diff --git a/sims/firesim b/sims/firesim index 1e6d7861..9636f8f8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1e6d7861588ced4ebe286228dce340692df8b4c4 +Subproject commit 9636f8f874671f8d1a3b8509d95febc34222a66f diff --git a/software/firemarshal b/software/firemarshal index 73f17936..da820669 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 73f17936e7bd4dcd01175181496bf814b692ac5f +Subproject commit da820669117f7619bfb6b7a8fc21e6080c33cfc1 diff --git a/tools/barstools b/tools/barstools index 9130e36f..064c8be7 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 9130e36fd1f0dbe7dad4ffe1a0e672246239f8d2 +Subproject commit 064c8be7bb3d86eccfd603c614f74de6de1c3f4a diff --git a/tools/dsptools b/tools/dsptools index aad6a3db..a1809fba 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit aad6a3db1520a05ae668681941a19bdcc40aec03 +Subproject commit a1809fbae9e49de7213116bbec79252645292e39 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 355bf9f2..0ffb46ad 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 355bf9f2038c68f4d44650f66d1516d171bfb224 +Subproject commit 0ffb46ad12d0335a1d44bc283bae596abfd79606