From 71ea647baec456c1fd524a627c49b8ee95b3a940 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 14 Dec 2021 22:47:45 +0000 Subject: [PATCH 01/55] Update build.sbt to use X.5-RC1 --- build.sbt | 40 ++++++++++++---------------------------- 1 file changed, 12 insertions(+), 28 deletions(-) diff --git a/build.sbt b/build.sbt index afb82b5d..f790d534 100644 --- a/build.sbt +++ b/build.sbt @@ -60,25 +60,19 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.4.4" +val chiselVersion = "3.5.0-RC1" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion), addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) -val firrtlVersion = "1.4.4" +val firrtlVersion = "1.5.0-RC1" lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion)) -// In some projects we override the default versions of Chisel and friends. -// This map captures the expected defaults used by projects under Chipyard. -lazy val chipyardMandatedVersions = Map( - "chisel-iotesters" -> "1.5.4", - "firrtl-interpreter" -> "1.4.4", - "treadle" -> "1.3.4", - "chisel3" -> chiselVersion, - "firrtl" -> firrtlVersion -) +val chiselTestVersion = "2.5.0-RC1" + +lazy val chiselTestSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel-iotesters" % chiselTestVersion)) // Subproject definitions begin @@ -138,19 +132,6 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) // -- Chipyard-managed External Projects -- -// Because we're not using a release version of iotesters to work around a -// scala test version problem, override it's libdeps to prevent using snapshots -lazy val chisel_testers = (project in file("tools/chisel-testers")) - .settings(chiselSettings) - .settings( - allDependencies := allDependencies.value.map { - case dep if chipyardMandatedVersions.isDefinedAt(dep.name) => - dep.organization %% dep.name % chipyardMandatedVersions(dep.name) - case o => o - }) - -// -- Normal Projects -- - // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") @@ -204,13 +185,15 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(commonSettings) lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) + .dependsOn(rocketchip, midasTargetUtils) .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(chiselTestSettings) .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(testchipip, rocketchip, chisel_testers) + .dependsOn(testchipip, rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(chiselTestSettings) .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) @@ -223,7 +206,8 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) .settings(commonSettings) lazy val tapeout = (project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources + .dependsOn(chipyard) // must depend on chipyard to get scala resources + .settings(chiselTestSettings) .settings(commonSettings) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) @@ -236,7 +220,7 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .dependsOn(chisel_testers) + .settings(chiselTestSettings) .settings( commonSettings, libraryDependencies ++= Seq( From 6b633ad13f155366ae644f1a80fc07d49e939b94 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 4 Oct 2021 15:48:18 -0700 Subject: [PATCH 02/55] Point to IOCells separately | Fixup Hwacha/Sodor more | Use tapeout package --- build.sbt | 18 +++++++----------- common.mk | 4 ++-- generators/boom | 2 +- generators/hwacha | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- tools/barstools | 2 +- tools/dsptools | 2 +- 9 files changed, 16 insertions(+), 20 deletions(-) diff --git a/build.sbt b/build.sbt index f790d534..04a162f6 100644 --- a/build.sbt +++ b/build.sbt @@ -201,22 +201,18 @@ lazy val nvdla = (project in file("generators/nvdla")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val iocell = (project in file("./tools/barstools/iocell/")) +lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "src") + .settings( + Compile / scalaSource := baseDirectory.value / "main" / "scala" / "barstools" / "iocell", + Compile / resourceDirectory := baseDirectory.value / "main" / "resources" + ) .settings(chiselSettings) .settings(commonSettings) -lazy val tapeout = (project in file("./tools/barstools/tapeout/")) - .dependsOn(chipyard) // must depend on chipyard to get scala resources +lazy val tapeout = (project in file("./tools/barstools/")) + .settings(chiselSettings) .settings(chiselTestSettings) - .settings(commonSettings) - -lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings(commonSettings) - -lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) - .dependsOn(mdf) .enablePlugins(sbtassembly.AssemblyPlugin) - .settings(firrtlSettings) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) diff --git a/common.mk b/common.mk index d055f784..14a505fd 100644 --- a/common.mk +++ b/common.mk @@ -162,7 +162,7 @@ $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): top_macro_temp @echo "" > /dev/null top_macro_temp: $(TOP_SMEMS_CONF) - $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)) HARNESS_MACROCOMPILER_MODE = --mode synflops .INTERMEDIATE: harness_macro_temp @@ -170,7 +170,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): harness_macro_temp @echo "" > /dev/null harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp - $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)) ######################################################################################## # remove duplicate files and headers in list of simulation file inputs diff --git a/generators/boom b/generators/boom index e1a70afe..e252e797 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit e1a70afed7de77f6ba9f6e501de71f7f41afc47c +Subproject commit e252e797c21aa3bf860cb9d67c6009ef00c5916f diff --git a/generators/hwacha b/generators/hwacha index 62c01f5a..17bdafcb 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 62c01f5a8858aa1b827f0f9372a4392d7b596fca +Subproject commit 17bdafcb3a6bae36956dd7255af157844a6d5b4d diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 449354c2..c4fdaa29 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 449354c27bf07ccc865dc6c005df1d08eaf5b01c +Subproject commit c4fdaa29798f69df7c2bdaf124f9b493d26da212 diff --git a/generators/rocket-chip b/generators/rocket-chip index a7b016e4..303564bb 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit a7b016e46e22e4fdc013357051e30511f80df082 +Subproject commit 303564bb36c3679d90954806a7c162300567a6b9 diff --git a/generators/testchipip b/generators/testchipip index 5917176c..247cad2d 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5917176c911cec667655984c2adc566aa404f4fe +Subproject commit 247cad2d0cf0f70f517a3f2a2d976bf4452b169e diff --git a/tools/barstools b/tools/barstools index 9130e36f..314d8072 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 9130e36fd1f0dbe7dad4ffe1a0e672246239f8d2 +Subproject commit 314d80729e7b32e3c10c0da6734bbdc9a867916f diff --git a/tools/dsptools b/tools/dsptools index aad6a3db..1b3b9485 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit aad6a3db1520a05ae668681941a19bdcc40aec03 +Subproject commit 1b3b94853da900c4566f16f16f5dbe6ab55bc090 From 8f93b873bcd03377b6b13b0b1acdc0d29446291e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 7 Oct 2021 10:19:08 -0700 Subject: [PATCH 03/55] Remove other small deprecations [ci skip] --- build.sbt | 4 ++-- generators/chipyard/src/main/scala/stage/ChipyardCli.scala | 3 +-- generators/chipyard/src/main/scala/stage/ChipyardStage.scala | 3 ++- .../src/main/scala/stage/phases/AddDefaultTests.scala | 4 +++- .../main/scala/stage/phases/GenerateTestSuiteMakefrags.scala | 4 +++- 5 files changed, 11 insertions(+), 7 deletions(-) diff --git a/build.sbt b/build.sbt index 04a162f6..e83992b9 100644 --- a/build.sbt +++ b/build.sbt @@ -260,8 +260,8 @@ lazy val firechip = (project in file("generators/firechip")) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, - testGrouping in Test := isolateAllTests( (definedTests in Test).value ), - testOptions in Test += Tests.Argument("-oF") + Test / testGrouping := isolateAllTests( (Test / definedTests).value ), + Test / testOptions += Tests.Argument("-oF") ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .dependsOn(rocketchip, sifive_blocks) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala index 7d293c36..da9311bf 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala @@ -10,6 +10,5 @@ trait ChipyardCli { this: Shell => parser.note("Chipyard Generator Options") Seq( UnderscoreDelimitedConfigsAnnotation - ) - .foreach(_.addOptions(parser)) + ).foreach(_.addOptions(parser)) } diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index 4e429618..a830c3a8 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.system.RocketChipStage import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} import firrtl.options.phases.DeletedWrapper -class ChipyardStage extends ChiselStage with PreservesAll[Phase] { +class ChipyardStage extends ChiselStage { override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli override val targets: Seq[PhaseDependency] = Seq( Dependency[freechips.rocketchip.stage.phases.Checks], @@ -33,4 +33,5 @@ class ChipyardStage extends ChiselStage with PreservesAll[Phase] { Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], ) + override final def invalidates(a: Phase): Boolean = false } diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 177d26b0..25a6fa61 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -22,7 +22,7 @@ import freechips.rocketchip.tile.XLen import chipyard.TestSuiteHelper import chipyard.TestSuitesKey -class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { +class AddDefaultTests extends Phase with HasRocketChipStageUtils { // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). override val prerequisites = Seq( @@ -52,4 +52,6 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance addTestSuiteAnnotations ++ oAnnos } + + override final def invalidates(a: Phase): Boolean = false } diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala index 0ed5ec11..e0796db5 100644 --- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -21,7 +21,7 @@ trait MakefragSnippet { self: Annotation => case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable /** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */ -class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { +class GenerateTestSuiteMakefrags extends Phase with HasRocketChipStageUtils { // Our annotations tend not to be serializable, but are not marked as such. override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], @@ -46,4 +46,6 @@ class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with Has writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString) outputAnnotations } + + override final def invalidates(a: Phase): Boolean = false } From eea1373c65033d43f800a2330a7a3d8d8864ea97 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 14 Dec 2021 23:39:36 +0000 Subject: [PATCH 04/55] Bump SBT --- project/build.properties | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/build.properties b/project/build.properties index dbae93bc..10fd9eee 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.4.9 +sbt.version=1.5.5 From 6b16d40c41df547ff8efdf38f47e1886b9c7526f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 14 Dec 2021 23:49:59 +0000 Subject: [PATCH 05/55] Aggressively remove SBT plugins that may no longer be needed --- project/plugins.sbt | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/project/plugins.sbt b/project/plugins.sbt index 026b95e9..e9f7f4e1 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,14 +1,2 @@ -addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") -addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") -addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") -addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0") -addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") -addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") -addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") -addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") -addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") -addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") -addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") -addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) From 89050565734d0f4cd8b254705475d499465a2d69 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 15 Dec 2021 00:03:13 +0000 Subject: [PATCH 06/55] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 1e6d7861..111e47a9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1e6d7861588ced4ebe286228dce340692df8b4c4 +Subproject commit 111e47a96f3d39ac20d3640b4954e0a474a0de27 From 13c22252b00ca2158b6c5c4d47848372ab28f31e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 11:16:03 -0800 Subject: [PATCH 07/55] Update to non RC --- build.sbt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index e83992b9..00460b96 100644 --- a/build.sbt +++ b/build.sbt @@ -60,17 +60,17 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5.0-RC1" +val chiselVersion = "3.5.0" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion), addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) -val firrtlVersion = "1.5.0-RC1" +val firrtlVersion = "1.5.0" lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion)) -val chiselTestVersion = "2.5.0-RC1" +val chiselTestVersion = "2.5.0" lazy val chiselTestSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel-iotesters" % chiselTestVersion)) From c42f369b47fc77707381edf6632d6ae1888f43f8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 11:18:36 -0800 Subject: [PATCH 08/55] Remove MaxPermSize --- variables.mk | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/variables.mk b/variables.mk index dd40f565..d41473b2 100644 --- a/variables.mk +++ b/variables.mk @@ -160,7 +160,7 @@ sim_common_files ?= $(build_dir)/sim_files.common.f # java arguments used in sbt ######################################################################################### JAVA_HEAP_SIZE ?= 8G -export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir=$(base_dir)/.java_tmp +export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(base_dir)/.java_tmp ######################################################################################### # default sbt launch command diff --git a/vlsi/hammer b/vlsi/hammer index 95428fb4..353af21d 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 95428fb44f3d8eda395b496dbdd4e04689e08acb +Subproject commit 353af21da3fe6f0c2e054ac513b5db583031b962 From 36e6a1736ec01d1bf61d5e8b914436c598d27f61 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 11:26:21 -0800 Subject: [PATCH 09/55] Update tutorial patch | Small warning fixes to build.sbt --- build.sbt | 10 +++++----- scripts/tutorial-patches/build.sbt.patch | 14 ++++++++------ 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/build.sbt b/build.sbt index 00460b96..da56aff3 100644 --- a/build.sbt +++ b/build.sbt @@ -8,8 +8,8 @@ lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.3", scalaVersion := "2.12.10", - test in assembly := {}, - assemblyMergeStrategy in assembly := { _ match { + assembly / test := {}, + assembly / assemblyMergeStrategy := { _ match { case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), @@ -48,8 +48,8 @@ lazy val firesimDir = if (firesimAsLibrary) { def freshProject(name: String, dir: File): Project = { Project(id = name, base = dir / "src") .settings( - scalaSource in Compile := baseDirectory.value / "main" / "scala", - resourceDirectory in Compile := baseDirectory.value / "main" / "resources" + Compile / scalaSource := baseDirectory.value / "main" / "scala", + Compile / resourceDirectory := baseDirectory.value / "main" / "resources" ) } @@ -248,7 +248,7 @@ lazy val sifive_blocks = (project in file("generators/sifive-blocks")) lazy val sifive_cache = (project in file("generators/sifive-cache")) .settings( commonSettings, - scalaSource in Compile := baseDirectory.value / "design/craft") + Compile / scalaSource := baseDirectory.value / "design/craft") .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index bc67c91b..b80ed216 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,8 +1,8 @@ diff --git a/build.sbt b/build.sbt -index 2187fe12..2319fc95 100644 +index 00460b96..1d37f975 100644 --- a/build.sbt +++ b/build.sbt -@@ -162,7 +162,7 @@ lazy val testchipip = (project in file("generators/testchipip")) +@@ -143,7 +143,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, @@ -11,18 +11,20 @@ index 2187fe12..2319fc95 100644 dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex) .settings(libraryDependencies ++= rocketLibDeps.value) -@@ -203,10 +203,10 @@ lazy val sodor = (project in file("generators/riscv-sodor")) +@@ -184,11 +184,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sha3 = (project in file("generators/sha3")) -- .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +- .dependsOn(rocketchip, midasTargetUtils) - .settings(libraryDependencies ++= rocketLibDeps.value) +- .settings(chiselTestSettings) - .settings(commonSettings) +//lazy val sha3 = (project in file("generators/sha3")) -+// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .dependsOn(rocketchip, midasTargetUtils) +// .settings(libraryDependencies ++= rocketLibDeps.value) ++// .settings(chiselTestSettings) +// .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(testchipip, rocketchip, chisel_testers) + .dependsOn(testchipip, rocketchip) From c36506229c4a6520f60e1cc427f99cd3eaeae862 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 14:21:16 -0800 Subject: [PATCH 10/55] Bump Ibex/CVA6/testchipip --- generators/cva6 | 2 +- generators/ibex | 2 +- generators/testchipip | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/cva6 b/generators/cva6 index 47173903..39e3b481 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 4717390310f8cf14f608e2a1d72d5c6f6a9ffc0f +Subproject commit 39e3b4811e4aab85044cb4dcc153dda6bb822a7d diff --git a/generators/ibex b/generators/ibex index bdf41a05..f92ffe73 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit bdf41a05484e57afa4ed20b35beff80320cfdd02 +Subproject commit f92ffe736450064e4a7bad7f2412ff46a09754a3 diff --git a/generators/testchipip b/generators/testchipip index 247cad2d..c8f4cf2f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 247cad2d0cf0f70f517a3f2a2d976bf4452b169e +Subproject commit c8f4cf2fb522fe48fbf4f35df0d62d1cdb1a12cd From e291cd4b7c77e8c981eda99e5660353afab42ed0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 14:25:16 -0800 Subject: [PATCH 11/55] Bump dsptools/rocket-dsp-utils --- tools/dsptools | 2 +- tools/rocket-dsp-utils | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/dsptools b/tools/dsptools index 1b3b9485..a1809fba 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 1b3b94853da900c4566f16f16f5dbe6ab55bc090 +Subproject commit a1809fbae9e49de7213116bbec79252645292e39 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 355bf9f2..0ffb46ad 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 355bf9f2038c68f4d44650f66d1516d171bfb224 +Subproject commit 0ffb46ad12d0335a1d44bc283bae596abfd79606 From a9a2236bdd58e62a7eaa1e8ecb9031853edbfbfc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 14:45:50 -0800 Subject: [PATCH 12/55] Update BOOM/Gemmini/Hwacha/Icenet/Sodor --- generators/boom | 2 +- generators/gemmini | 2 +- generators/hwacha | 2 +- generators/icenet | 2 +- generators/riscv-sodor | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/boom b/generators/boom index e252e797..68e76740 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit e252e797c21aa3bf860cb9d67c6009ef00c5916f +Subproject commit 68e767400cc5b0ea46ae797d88f0908729de8fce diff --git a/generators/gemmini b/generators/gemmini index 7ac61db6..5687ff9f 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 7ac61db64fecbc8918b3039d738513b4a03337ca +Subproject commit 5687ff9f809cb3eb0acafc1ac2f73a57d0a67b2c diff --git a/generators/hwacha b/generators/hwacha index 17bdafcb..f7e47e1c 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 17bdafcb3a6bae36956dd7255af157844a6d5b4d +Subproject commit f7e47e1c3a717e4ebefd4b3b3aec10020b65db39 diff --git a/generators/icenet b/generators/icenet index 084ca507..29db0e04 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 084ca5070605ea7919358f917289cca240d0289a +Subproject commit 29db0e040412684cb28a15b127a16109cdecb0ac diff --git a/generators/riscv-sodor b/generators/riscv-sodor index c4fdaa29..7b19a1c7 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit c4fdaa29798f69df7c2bdaf124f9b493d26da212 +Subproject commit 7b19a1c74fa36217db288987ac8d63e699eda1b4 From e3bdbb2041443b9a93cccce04ee35aff2fe713af Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 14:46:12 -0800 Subject: [PATCH 13/55] Update Chipyard --- generators/chipyard/src/main/scala/example/TutorialTile.scala | 2 ++ .../chipyard/src/main/scala/example/dsptools/GenericFIR.scala | 4 ---- .../main/scala/example/dsptools/StreamingPassthrough.scala | 2 -- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index fad51c01..97294428 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -28,6 +28,7 @@ case class MyCoreParams( enableToFromHostCaching: Boolean = false, ) extends CoreParams { val useVM: Boolean = true + val useHypervisor: Boolean = false val useUser: Boolean = true val useSupervisor: Boolean = false val useDebug: Boolean = true @@ -41,6 +42,7 @@ case class MyCoreParams( val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket val nLocalInterrupts: Int = 0 val useNMI: Boolean = false + val nPTECacheEntries: Int = 0 // TODO: Check val nPMPs: Int = 0 // TODO: Check val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index ed16b25d..b92ca181 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -25,8 +25,6 @@ case object GenericFIRKey extends Field[Option[GenericFIRParams]](None) class GenericFIRCellBundle[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { val data: T = genIn.cloneType val carry: T = genOut.cloneType - - override def cloneType: this.type = GenericFIRCellBundle(genIn, genOut).asInstanceOf[this.type] } object GenericFIRCellBundle { def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellBundle[T] = new GenericFIRCellBundle(genIn, genOut) @@ -43,8 +41,6 @@ object GenericFIRCellIO { class GenericFIRBundle[T<:Data:Ring](proto: T) extends Bundle { val data: T = proto.cloneType - - override def cloneType: this.type = GenericFIRBundle(proto).asInstanceOf[this.type] } object GenericFIRBundle { def apply[T<:Data:Ring](proto: T): GenericFIRBundle[T] = new GenericFIRBundle(proto) diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 923f12e2..fe02c996 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -26,8 +26,6 @@ case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughPar class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle { val data: T = proto.cloneType - - override def cloneType: this.type = StreamingPassthroughBundle(proto).asInstanceOf[this.type] } object StreamingPassthroughBundle { def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto) From 00626b51e00f78aaff0c082528f5dec90534543f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 14:51:08 -0800 Subject: [PATCH 14/55] Update Hwacha/Icenet --- generators/hwacha | 2 +- generators/icenet | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/hwacha b/generators/hwacha index f7e47e1c..062e46e3 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit f7e47e1c3a717e4ebefd4b3b3aec10020b65db39 +Subproject commit 062e46e36d1e5fbe486ab2db54bda62f71fd3dab diff --git a/generators/icenet b/generators/icenet index 29db0e04..2d4022de 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 29db0e040412684cb28a15b127a16109cdecb0ac +Subproject commit 2d4022de45bae66eef1817ac9ef18708961ec6ea From 74e20b49f0cc5c70d3b3437e60ab2cf216d618fd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 15:15:09 -0800 Subject: [PATCH 15/55] Convert fire() to fire --- generators/boom | 2 +- generators/chipyard/src/main/scala/example/InitZero.scala | 2 +- .../src/main/scala/example/dsptools/GenericFIR.scala | 4 ++-- generators/gemmini | 2 +- generators/hwacha | 2 +- generators/icenet | 2 +- generators/riscv-sodor | 2 +- generators/testchipip | 2 +- generators/tracegen/src/main/scala/Tile.scala | 6 +++--- 9 files changed, 12 insertions(+), 12 deletions(-) diff --git a/generators/boom b/generators/boom index 68e76740..42dc388e 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 68e767400cc5b0ea46ae797d88f0908729de8fce +Subproject commit 42dc388e755b8a1b7631e355d532d9b6b6730743 diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala index c351a4dd..a9885d34 100644 --- a/generators/chipyard/src/main/scala/example/InitZero.scala +++ b/generators/chipyard/src/main/scala/example/InitZero.scala @@ -52,7 +52,7 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) { state := s_resp } - when (mem.d.fire()) { + when (mem.d.fire) { state := Mux(bytesLeft === 0.U, s_done, s_write) } } diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index b92ca181..f45b318c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -115,7 +115,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { // When a new transaction is ready on the input, we will have new data to output // next cycle. Take this data in - when (io.in.fire()) { + when (io.in.fire) { hasNewData := 1.U inputReg := io.in.bits.data } @@ -123,7 +123,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { // We should output data when our cell has new data to output and is ready to // recieve new data. This insures that every cell in the chain passes its data // on at the same time - io.out.valid := hasNewData & io.in.fire() + io.out.valid := hasNewData & io.in.fire io.out.bits.data := inputReg // Compute carry diff --git a/generators/gemmini b/generators/gemmini index 5687ff9f..a99a4eee 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 5687ff9f809cb3eb0acafc1ac2f73a57d0a67b2c +Subproject commit a99a4eee1e6c101eed392e22b271f24f65744629 diff --git a/generators/hwacha b/generators/hwacha index 062e46e3..34aaffd2 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 062e46e36d1e5fbe486ab2db54bda62f71fd3dab +Subproject commit 34aaffd206a3fe07f6bea05588a20862bf95a68b diff --git a/generators/icenet b/generators/icenet index 2d4022de..af7253de 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 2d4022de45bae66eef1817ac9ef18708961ec6ea +Subproject commit af7253dea91c48b13f43f2da5ee2abae170aaa36 diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 7b19a1c7..f8892559 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 7b19a1c74fa36217db288987ac8d63e699eda1b4 +Subproject commit f8892559c6b499d2b80a3bc095fac99b15ea8a6a diff --git a/generators/testchipip b/generators/testchipip index c8f4cf2f..aaf0cd18 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c8f4cf2fb522fe48fbf4f35df0d62d1cdb1a12cd +Subproject commit aaf0cd18100a1b6b11f554b9acfcf2c01c0d40a4 diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 712cffc1..2e0084ec 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -66,10 +66,10 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) tracegen_uop.ctrl.is_sta := isWrite(io.tracegen.req.bits.cmd) tracegen_uop.ctrl.is_std := isWrite(io.tracegen.req.bits.cmd) - io.lsu.dis_uops(0).valid := io.tracegen.req.fire() + io.lsu.dis_uops(0).valid := io.tracegen.req.fire io.lsu.dis_uops(0).bits := tracegen_uop - when (io.tracegen.req.fire()) { + when (io.tracegen.req.fire) { rob_tail := WrapInc(rob_tail, rob_sz) rob_bsy(rob_tail) := true.B rob_uop(rob_tail) := tracegen_uop @@ -111,7 +111,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) assert(!io.lsu.lxcpt.valid) - io.lsu.exe(0).req.valid := RegNext(io.tracegen.req.fire()) + io.lsu.exe(0).req.valid := RegNext(io.tracegen.req.fire) io.lsu.exe(0).req.bits := DontCare io.lsu.exe(0).req.bits.uop := RegNext(tracegen_uop) io.lsu.exe(0).req.bits.addr := RegNext(io.tracegen.req.bits.addr) From 70202eb9df4cd14370b757a77da0953bcb6d5831 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 15:19:00 -0800 Subject: [PATCH 16/55] Use temp. rocket-chip to get past elaboration --- .gitmodules | 2 +- generators/rocket-chip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 6128783a..cb3b173c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ [submodule "rocket-chip"] path = generators/rocket-chip - url = https://github.com/ucb-bar/rocket-chip.git + url = https://github.com/abejgonzalez/rocket-chip.git [submodule "testchipip"] path = generators/testchipip url = https://github.com/ucb-bar/testchipip.git diff --git a/generators/rocket-chip b/generators/rocket-chip index 303564bb..c3491b4e 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 303564bb36c3679d90954806a7c162300567a6b9 +Subproject commit c3491b4e7a948b45408813f31003e49b39635774 From 12634276559eb4a722c4ad625a0a8772c3e70a30 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 15:46:37 -0800 Subject: [PATCH 17/55] Allow unrecognized annos --- common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/common.mk b/common.mk index 14a505fd..b4f4d644 100644 --- a/common.mk +++ b/common.mk @@ -135,6 +135,7 @@ $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,\ + --allow-unrecognized-annotations \ --output-file $(TOP_FILE) \ --harness-o $(HARNESS_FILE) \ --input-file $(FIRRTL_FILE) \ From 9845657a070d9acceff11f0c9de402bee2b1a157 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 15:52:26 -0800 Subject: [PATCH 18/55] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 111e47a9..0a68c1b2 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 111e47a96f3d39ac20d3640b4954e0a474a0de27 +Subproject commit 0a68c1b24afc7a0b50a0c7eea17c4b2054c0cb6a From cd0d194ba63f5f148fb5c73a2a3b6bc354b912fc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 16:12:22 -0800 Subject: [PATCH 19/55] Update rocketchip --- .gitmodules | 2 +- generators/rocket-chip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index cb3b173c..76e9f804 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ [submodule "rocket-chip"] path = generators/rocket-chip - url = https://github.com/abejgonzalez/rocket-chip.git + url = https://github.com/chipsalliance/rocket-chip.git [submodule "testchipip"] path = generators/testchipip url = https://github.com/ucb-bar/testchipip.git diff --git a/generators/rocket-chip b/generators/rocket-chip index c3491b4e..114325b2 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit c3491b4e7a948b45408813f31003e49b39635774 +Subproject commit 114325b27cfe5312c86a8a325b187be9455a62af From 117624d8eea27bafd613eec09e9b9b3e31239e08 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 17 Jan 2022 16:23:47 -0800 Subject: [PATCH 20/55] Bump BOOM/Gemmini --- generators/boom | 2 +- generators/gemmini | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 42dc388e..d90e6639 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 42dc388e755b8a1b7631e355d532d9b6b6730743 +Subproject commit d90e6639cea70397850380c6f14ae6e93aa60727 diff --git a/generators/gemmini b/generators/gemmini index a99a4eee..032f387e 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit a99a4eee1e6c101eed392e22b271f24f65744629 +Subproject commit 032f387ea6f2583c5be5ab36f8aa1a33baadb9a3 From ad5c77d8bc7296185d966e3dbd84d235d0687f7b Mon Sep 17 00:00:00 2001 From: Hasan Genc Date: Wed, 19 Jan 2022 11:47:36 -0800 Subject: [PATCH 21/55] Bump Gemmini to v0.6.3 --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 032f387e..c47cb7f3 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 032f387ea6f2583c5be5ab36f8aa1a33baadb9a3 +Subproject commit c47cb7f3eb5c18390f176f3a53c43c8546d487d2 From bce60a3d0e4f771974d69bfd9b54d4c018e0484e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Jan 2022 21:47:01 -0800 Subject: [PATCH 22/55] Bump BOOM and Sodor --- generators/boom | 2 +- generators/riscv-sodor | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index d90e6639..5c813dbc 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit d90e6639cea70397850380c6f14ae6e93aa60727 +Subproject commit 5c813dbc1fa033b2cd1d2566e6320f1f30c3d239 diff --git a/generators/riscv-sodor b/generators/riscv-sodor index f8892559..0a0f0479 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit f8892559c6b499d2b80a3bc095fac99b15ea8a6a +Subproject commit 0a0f04799fd8a5e955073dd3ad28521d825d5e16 From 596e979cf8dee434b07df8ab626c61b2dd268724 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 20 Jan 2022 15:39:53 -0800 Subject: [PATCH 23/55] Use 3.5-SNAPSHOT to get compatibility module fix --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index da56aff3..c6194322 100644 --- a/build.sbt +++ b/build.sbt @@ -60,7 +60,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5.0" +val chiselVersion = "3.5-SNAPSHOT" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion), From b168d9cc23283c42ea2d3891d5921f597d3d4b9d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Jan 2022 16:25:17 -0800 Subject: [PATCH 24/55] Bump sodor for virtual io fix --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 52b26201..5643a8e2 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 52b26201aecab16e2bb46748a12c0f872a2da6da +Subproject commit 5643a8e245d562647f626295ad2dab9b4d5f6a13 From 10c813db3811e3cd094050088f822a0c64ca802b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Jan 2022 17:10:34 -0800 Subject: [PATCH 25/55] Bump BOOM for hypervisor changes --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 5c813dbc..efe2b35c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 5c813dbc1fa033b2cd1d2566e6320f1f30c3d239 +Subproject commit efe2b35cc2224edf3a417381d437cfdcb37e02a8 From 0e6080682b3dd0ce11cdfed1292ec20e70d75f80 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Jan 2022 20:30:17 -0800 Subject: [PATCH 26/55] Use Chisel 3.5-SNAPSHOT fixes --- build.sbt | 7 ++++--- sims/firesim | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index c6194322..7f415871 100644 --- a/build.sbt +++ b/build.sbt @@ -6,7 +6,7 @@ lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", - version := "1.3", + version := "1.6", scalaVersion := "2.12.10", assembly / test := {}, assembly / assemblyMergeStrategy := { _ match { @@ -66,11 +66,11 @@ lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion), addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) -val firrtlVersion = "1.5.0" +val firrtlVersion = "1.5-SNAPSHOT" lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion)) -val chiselTestVersion = "2.5.0" +val chiselTestVersion = "2.5-SNAPSHOT" lazy val chiselTestSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel-iotesters" % chiselTestVersion)) @@ -147,6 +147,7 @@ lazy val chipyard = (project in file("generators/chipyard")) dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex) .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(chiselSettings) .settings(commonSettings) lazy val tracegen = (project in file("generators/tracegen")) diff --git a/sims/firesim b/sims/firesim index 0a68c1b2..beba9262 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 0a68c1b24afc7a0b50a0c7eea17c4b2054c0cb6a +Subproject commit beba9262902c2e3e7551f83f6ea4e196e137211a From 0c369c4782ed552db51768f09e9155d2fd75e9d3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Jan 2022 14:21:49 -0800 Subject: [PATCH 27/55] Bump BOOM and FireSim --- generators/boom | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index efe2b35c..1ad28828 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit efe2b35cc2224edf3a417381d437cfdcb37e02a8 +Subproject commit 1ad28828673f2fce7a18f7255facd4705f04a58a diff --git a/sims/firesim b/sims/firesim index beba9262..1bf9ece6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit beba9262902c2e3e7551f83f6ea4e196e137211a +Subproject commit 1bf9ece69345d713db1a4e30f1140d0d46054776 From e48108da567fffb2ad464097c64ce617b8cc9fb2 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 21 Jan 2022 16:08:03 -0800 Subject: [PATCH 28/55] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 1bf9ece6..9c778b6c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1bf9ece69345d713db1a4e30f1140d0d46054776 +Subproject commit 9c778b6cd7f50f7a8ed1c7188df855bf042d36ef From 3a2af9672098f100b6fdb7186da5af14859e7040 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 24 Jan 2022 14:42:16 -0800 Subject: [PATCH 29/55] Fix ScratchPadOnly config --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 43bb2fb2..3b3bb597 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -135,9 +135,9 @@ class LoopbackNICRocketConfig extends Config( // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( new testchipip.WithSerialPBusMem ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new chipyard.config.WithL2TLBs(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) From e17f478d01b94621d09012e9c42349a0d2fd2274 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 24 Jan 2022 14:43:25 -0800 Subject: [PATCH 30/55] Fix tracegen compile --- generators/tracegen/src/main/scala/Tile.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 2e0084ec..93d3c2c9 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -158,7 +158,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) io.lsu.rob_head_idx := rob_head - + io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy } case class BoomTraceGenTileAttachParams( @@ -236,6 +236,7 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) ptw.io.requestors.head <> lsu.io.ptw outer.dcache.module.io.lsu <> lsu.io.dmem boom_shim.io.tracegen <> tracegen.io.mem + tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered boom_shim.io.lsu <> lsu.io.core // Normally the PTW would use this port From c18bc6bd0df3b7e43c6af089bd949174050abf64 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 24 Jan 2022 14:54:23 -0800 Subject: [PATCH 31/55] Add chisel plugin to firechip --- build.sbt | 1 + 1 file changed, 1 insertion(+) diff --git a/build.sbt b/build.sbt index 7f415871..5d590717 100644 --- a/build.sbt +++ b/build.sbt @@ -260,6 +260,7 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( + chiselSettings, commonSettings, Test / testGrouping := isolateAllTests( (Test / definedTests).value ), Test / testOptions += Tests.Argument("-oF") From 4180463d52bc0a6b4c004530601ccdabebf0ab7d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 24 Jan 2022 17:52:10 -0800 Subject: [PATCH 32/55] Bump CVA6/Ibex/NVDLA for BB fix | Bump FireSim --- generators/cva6 | 2 +- generators/ibex | 2 +- generators/nvdla | 2 +- sims/firesim | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/cva6 b/generators/cva6 index 39e3b481..5d8ece5c 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 39e3b4811e4aab85044cb4dcc153dda6bb822a7d +Subproject commit 5d8ece5c21ec201223eee45818d8b088fd62c3fb diff --git a/generators/ibex b/generators/ibex index f92ffe73..1a01a82b 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit f92ffe736450064e4a7bad7f2412ff46a09754a3 +Subproject commit 1a01a82b6c5fc7565ddb7cf6b58cdac17b1dc9bc diff --git a/generators/nvdla b/generators/nvdla index b2b78c9f..e08f1825 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit b2b78c9f892a6196634eb3f1fbc443436c897a00 +Subproject commit e08f18250333cfd16240baeab01d9934e840621d diff --git a/sims/firesim b/sims/firesim index 9c778b6c..6a3dc348 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9c778b6cd7f50f7a8ed1c7188df855bf042d36ef +Subproject commit 6a3dc348d8c0a3ebcf71ce9aeaf062cec04d8b75 From af9435d0c51bf466955f1ba906054e69a486deec Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 31 Jan 2022 10:23:51 -0800 Subject: [PATCH 33/55] Fix `SOURCE_DIRS` for barstools [ci skip] --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index b4f4d644..1993c475 100644 --- a/common.mk +++ b/common.mk @@ -71,7 +71,7 @@ else lookup_srcs = $(shell fd -L ".*\.$(2)" $(1)) endif -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools fpga/fpga-shells fpga/src) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources From aa7edcf2dae6f19eb2de9854c1f3122019def825 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 31 Jan 2022 10:54:16 -0800 Subject: [PATCH 34/55] Bump BOOM/FireSim --- generators/boom | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 1ad28828..90a4ec64 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1ad28828673f2fce7a18f7255facd4705f04a58a +Subproject commit 90a4ec647e9fbb5a7d0f396835d87adb7b8274af diff --git a/sims/firesim b/sims/firesim index 6a3dc348..35e45c9b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6a3dc348d8c0a3ebcf71ce9aeaf062cec04d8b75 +Subproject commit 35e45c9b76ccac45e2636594d480f57ff06e7797 From 88effe688a3a7e250d552a4e9e3c225149af59f3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 31 Jan 2022 11:19:50 -0800 Subject: [PATCH 35/55] Update FFT repo | Fix dsptools compile --- build.sbt | 4 ++-- generators/fft-generator | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index fc144862..bbbb8251 100644 --- a/build.sbt +++ b/build.sbt @@ -152,7 +152,6 @@ lazy val chipyard = (project in file("generators/chipyard")) lazy val fft_generator = (project in file("generators/fft-generator")) .dependsOn(rocketchip, `rocket-dsp-utils`) .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(chiselSettings) .settings(commonSettings) lazy val tracegen = (project in file("generators/tracegen")) @@ -222,8 +221,9 @@ lazy val tapeout = (project in file("./tools/barstools/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .settings(chiselTestSettings) .settings( + chiselSettings, + chiselTestSettings, commonSettings, libraryDependencies ++= Seq( "org.scalatest" %% "scalatest" % "3.2.+" % "test", diff --git a/generators/fft-generator b/generators/fft-generator index b9f1c085..511e33f9 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit b9f1c085afa25e1688d5acbd3f252882d511b90e +Subproject commit 511e33f933e83020f3f7b535641da0b46ceb6923 From 4636b15f726f55437694ba3cd7b0ceaa4952702f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 1 Feb 2022 11:04:25 -0800 Subject: [PATCH 36/55] Bump SHA3 --- generators/sha3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sha3 b/generators/sha3 index 63eda826..bca1e607 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 63eda8268c16c502cada9944ae41b584e6e32789 +Subproject commit bca1e6078e25af32d0ef143a197d40f1857ab433 From a3f0d1ed574f3e702f54860caf071eac0c33b8bb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 1 Feb 2022 11:06:34 -0800 Subject: [PATCH 37/55] Bump tutorial build.sbt patch --- scripts/tutorial-patches/build.sbt.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index b80ed216..a701ecf1 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,5 +1,5 @@ diff --git a/build.sbt b/build.sbt -index 00460b96..1d37f975 100644 +index bbbb8251..b7adcb73 100644 --- a/build.sbt +++ b/build.sbt @@ -143,7 +143,7 @@ lazy val testchipip = (project in file("generators/testchipip")) @@ -7,11 +7,11 @@ index 00460b96..1d37f975 100644 lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches -+ //sha3, // On separate line to allow for cleaner tutorial-setup patches ++// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, - gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex) + gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator) .settings(libraryDependencies ++= rocketLibDeps.value) -@@ -184,11 +184,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) +@@ -189,11 +189,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) From 27fceafdd7949cbbc9f64f940f1643b31ee3439e Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Tue, 1 Feb 2022 14:17:42 -0800 Subject: [PATCH 38/55] Bump sha3 --- generators/sha3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sha3 b/generators/sha3 index bca1e607..88ada85a 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit bca1e6078e25af32d0ef143a197d40f1857ab433 +Subproject commit 88ada85a84253434ea5cef729d90cd74796aa442 From a6d656bbbe0c81b30c93eb4e6aa1fae61221896f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Feb 2022 16:06:41 -0800 Subject: [PATCH 39/55] Try barstools fix --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 314d8072..d1de92d2 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 314d80729e7b32e3c10c0da6734bbdc9a867916f +Subproject commit d1de92d28787d4fb395e0e631a5c68fa31b02227 From e7c7a7751279fdaa052afb74efe0c66463ceed34 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Mon, 7 Feb 2022 17:44:43 -0800 Subject: [PATCH 40/55] Bump hwacha --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index 34aaffd2..fbb499e8 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 34aaffd206a3fe07f6bea05588a20862bf95a68b +Subproject commit fbb499e86c8e4a91485cf5d9f51375321b1cdd6a From e39795e873a3083ef6e493f726844ee5cbefdffc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 8 Feb 2022 09:18:46 -0800 Subject: [PATCH 41/55] Bump to Chisel 3.5.1 --- build.sbt | 6 +++--- sims/firesim | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index bbbb8251..9d0a7ac0 100644 --- a/build.sbt +++ b/build.sbt @@ -60,17 +60,17 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5-SNAPSHOT" +val chiselVersion = "3.5.1" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion), addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) -val firrtlVersion = "1.5-SNAPSHOT" +val firrtlVersion = "1.5.1" lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion)) -val chiselTestVersion = "2.5-SNAPSHOT" +val chiselTestVersion = "2.5.1" lazy val chiselTestSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel-iotesters" % chiselTestVersion)) diff --git a/sims/firesim b/sims/firesim index 35e45c9b..e3fb3b6b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 35e45c9b76ccac45e2636594d480f57ff06e7797 +Subproject commit e3fb3b6b28ce401a799a80f5161e50a8688f2fdd From 40a5f36d5005608f5dbdbd57765ef1ae4706f433 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 8 Feb 2022 09:22:17 -0800 Subject: [PATCH 42/55] Rebump FireSim | Bump barstools for updated Chisel 3.5.1 --- sims/firesim | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/firesim b/sims/firesim index e3fb3b6b..9636f8f8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e3fb3b6b28ce401a799a80f5161e50a8688f2fdd +Subproject commit 9636f8f874671f8d1a3b8509d95febc34222a66f diff --git a/tools/barstools b/tools/barstools index d1de92d2..adaca594 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit d1de92d28787d4fb395e0e631a5c68fa31b02227 +Subproject commit adaca59416294898611f3fa2401888526e8bf95a From 9588d7536c3ea20170d0a3768b99af6fc28d98ca Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 8 Feb 2022 11:03:55 -0800 Subject: [PATCH 43/55] Have PRCI control registers be clocked by the bus they hang off of (#1109) This was technically correct before if the CBUS clock was the implicit clock. but this change makes it correct when that is not the case --- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 30a29bcb..8c2a7365 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -72,8 +72,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) := ClockGroupCombiner() := ClockGroupResetSynchronizer() - := TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) - := TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) + := prci_ctrl_domain { TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) } + := prci_ctrl_domain { TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) } := allClockGroupsNode) } From 534fde1c0f46a29933e12e23f40d54afc48f4820 Mon Sep 17 00:00:00 2001 From: Kevin Laeufer Date: Tue, 8 Feb 2022 14:12:33 -0800 Subject: [PATCH 44/55] tracegen: execute to axe script with python2 (#1107) --- scripts/check-tracegen.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/check-tracegen.sh b/scripts/check-tracegen.sh index 3ba63067..947e7312 100755 --- a/scripts/check-tracegen.sh +++ b/scripts/check-tracegen.sh @@ -13,7 +13,7 @@ AXE_SHRINK=${AXE_DIR}/src/axe-shrink.py PATH=$PATH:${AXE_DIR}/src grep '.*:.*#.*@' $1 > /tmp/clean-trace.txt -"$TO_AXE" /tmp/clean-trace.txt > /tmp/trace.axe +python2 "$TO_AXE" /tmp/clean-trace.txt > /tmp/trace.axe result=$("$AXE" check wmo /tmp/trace.axe) if [ "$result" != OK ]; then From cfb55cdffc569dc8c2e62b91d059ea26a558bc38 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 10 Feb 2022 17:24:54 -0800 Subject: [PATCH 45/55] Bump to master commits --- generators/boom | 2 +- generators/cva6 | 2 +- generators/fft-generator | 2 +- generators/hwacha | 2 +- generators/ibex | 2 +- generators/icenet | 2 +- generators/nvdla | 2 +- tools/barstools | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/generators/boom b/generators/boom index 90a4ec64..ad64c541 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 90a4ec647e9fbb5a7d0f396835d87adb7b8274af +Subproject commit ad64c5419151e5e886daee7084d8399713b46b4b diff --git a/generators/cva6 b/generators/cva6 index 5d8ece5c..705c48a1 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 5d8ece5c21ec201223eee45818d8b088fd62c3fb +Subproject commit 705c48a1dacc011cef9b4d021a88b4948e7f9b64 diff --git a/generators/fft-generator b/generators/fft-generator index 511e33f9..4c335ff6 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit 511e33f933e83020f3f7b535641da0b46ceb6923 +Subproject commit 4c335ff6aba3734fcc373548ea39f4c798f70cea diff --git a/generators/hwacha b/generators/hwacha index fbb499e8..7cc63543 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit fbb499e86c8e4a91485cf5d9f51375321b1cdd6a +Subproject commit 7cc6354351457c6b5bf186cdd34297ee5caeb22a diff --git a/generators/ibex b/generators/ibex index 1a01a82b..0eac465e 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 1a01a82b6c5fc7565ddb7cf6b58cdac17b1dc9bc +Subproject commit 0eac465e3e9e06eceba111b4b43d5178ede817c2 diff --git a/generators/icenet b/generators/icenet index af7253de..e14c1e8c 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit af7253dea91c48b13f43f2da5ee2abae170aaa36 +Subproject commit e14c1e8c54851d3fa7bc55fbbc6fc48873a3b2a9 diff --git a/generators/nvdla b/generators/nvdla index e08f1825..2b17011b 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit e08f18250333cfd16240baeab01d9934e840621d +Subproject commit 2b17011b266025704b958efeeca2363c0cdd446d diff --git a/tools/barstools b/tools/barstools index adaca594..064c8be7 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit adaca59416294898611f3fa2401888526e8bf95a +Subproject commit 064c8be7bb3d86eccfd603c614f74de6de1c3f4a From 7bb19fe7dc6fe714304ac86196e0317adb844a24 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 10 Feb 2022 17:31:20 -0800 Subject: [PATCH 46/55] Bump testchipip to master --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index aaf0cd18..52027a04 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit aaf0cd18100a1b6b11f554b9acfcf2c01c0d40a4 +Subproject commit 52027a049f7810013e5940a1c115ff83127c1a96 From 12d4444e3d5598a05c8a3d7bd69163c13a72e1b5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Feb 2022 19:48:09 +0000 Subject: [PATCH 47/55] Check for tagged release --- .../init-submodules-no-riscv-tools-nolog.sh | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 6f9202f0..9d98e6f2 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -4,6 +4,34 @@ set -e set -o pipefail +SKIP_VALIDATE=false + +function usage +{ + echo "Usage: $0 [--skip-validate]" + echo "Initialize Chipyard submodules and setup initial env.sh script." + echo "" + echo " --skip-validate Skip prompt checking for tagged release" +} + +while test $# -gt 0 +do + case "$1" in + --skip-validate) + SKIP_VALIDATE=true; + ;; + -h | -H | --help) + usage + exit 1 + ;; + *) echo "ERROR: bad argument $1" + usage + exit 2 + ;; + esac + shift +done + # Check that git version is at least 1.7.8 MYGIT=$(git --version) MYGIT=${MYGIT#'git version '} # Strip prefix @@ -17,6 +45,21 @@ if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then false fi +# before doing anything verify that you are on a release branch/tag +set +e +tag=$(git describe --exact-match --tags) +tag_ret_code=$? +set -e +if [ $tag_ret_code -ne 0 ]; then + if [ "$SKIP_VALIDATE" = false ]; then + read -p "WARNING: You are not on a tagged release of Chipyard. Type \"ok\" to continue: " validate + [[ $validate == [oO][kK] ]] || exit 3 + echo "Setting up non-release Chipyard" + fi +else + echo "Setting up Chipyard $tag" +fi + # On macOS, use GNU readlink from 'coreutils' package in Homebrew/MacPorts if [ "$(uname -s)" = "Darwin" ] ; then READLINK=greadlink From 0b27c9f37e0ccb38e8bdb0e1c601839787a11178 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Feb 2022 19:49:09 +0000 Subject: [PATCH 48/55] Fix CI for --skip-validate in init-submodules --- .github/scripts/remote-do-rtl-build.sh | 2 +- .github/scripts/remote-run-firesim-scala-tests.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index a5268288..1f4251b1 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -15,7 +15,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh cd $REMOTE_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh +./scripts/init-submodules-no-riscv-tools.sh --skip-validate ./scripts/init-fpga.sh TOOLS_DIR=$REMOTE_RISCV_DIR diff --git a/.github/scripts/remote-run-firesim-scala-tests.sh b/.github/scripts/remote-run-firesim-scala-tests.sh index 732cb59d..6fe52586 100755 --- a/.github/scripts/remote-run-firesim-scala-tests.sh +++ b/.github/scripts/remote-run-firesim-scala-tests.sh @@ -18,7 +18,7 @@ export PATH="$RISCV/bin:$PATH" # This would generally be handled by build-setup.sh/firesim-setup.sh REMOTE_FIRESIM_SYSROOT=$REMOTE_FIRESIM_DIR/lib-install -./scripts/init-submodules-no-riscv-tools.sh +./scripts/init-submodules-no-riscv-tools.sh --skip-validate cd $REMOTE_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib git submodule update --init elfutils libdwarf cd $REMOTE_CHIPYARD_DIR/sims/firesim From f226901ff9cc643af210ae2821467db312951343 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Feb 2022 19:59:58 +0000 Subject: [PATCH 49/55] skip-validate on FireSim setup (assume this is checked in init-submod 1st --- scripts/firesim-setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index a110cb61..a7f265f1 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -13,5 +13,5 @@ cd "${scripts_dir}/.." # Reenable the FireSim submodule git config --unset submodule.sims/firesim.update || true cd sims/firesim -./build-setup.sh "$@" --library +./build-setup.sh "$@" --library --skip-validate cd "$RDIR" From 1dae13d3fe9295abd903a0a55872a10a65d8682e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 12 Feb 2022 00:03:58 +0000 Subject: [PATCH 50/55] Update docs --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 1194009f..93e12ca6 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -33,9 +33,12 @@ Start by fetching Chipyard's sources. Run: git clone https://github.com/ucb-bar/chipyard.git cd chipyard + # fancy way to checkout latest tag (for example resolves to "1.5.0" if that is the latest) │ 31 ------------------------------------------- + git checkout $(git describe --tags $(git rev-list --tags --max-count=1)) ./scripts/init-submodules-no-riscv-tools.sh This will initialize and checkout all of the necessary git submodules. +This will also validate that you are on a tagged branch, otherwise it will prompt for confirmation. When updating Chipyard to a new version, you will also want to rerun this script to update the submodules. Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior. From 6cce3b1cbd1da34e7ade12234db075c66ca0a064 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Mon, 14 Feb 2022 14:01:46 -0500 Subject: [PATCH 51/55] bump firemarshal 1.12.1 --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index 73f17936..da820669 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 73f17936e7bd4dcd01175181496bf814b692ac5f +Subproject commit da820669117f7619bfb6b7a8fc21e6080c33cfc1 From 31cb221cc03617e30583f40363d1968ea618f421 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 14 Feb 2022 18:55:51 -0800 Subject: [PATCH 52/55] Update all --- .readthedocs.yml | 15 +++++-- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 7 +-- docs/conf.py | 44 ++++++++++++++++--- docs/index.rst | 9 +--- .../init-submodules-no-riscv-tools-nolog.sh | 8 ++-- 5 files changed, 61 insertions(+), 22 deletions(-) diff --git a/.readthedocs.yml b/.readthedocs.yml index 43e2d306..51959f5a 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -1,7 +1,16 @@ version: 2 + +build: + os: ubuntu-20.04 + tools: + python: "3.6" + formats: all + sphinx: - configuration: docs/conf.py + configuration: docs/conf.py + fail_on_warning: true + python: - install: - - requirements: docs/requirements.txt + install: + - requirements: docs/requirements.txt diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 93e12ca6..2638d852 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -29,12 +29,13 @@ Setting up the Chipyard Repo Start by fetching Chipyard's sources. Run: -.. code-block:: shell +.. parsed-literal:: git clone https://github.com/ucb-bar/chipyard.git cd chipyard - # fancy way to checkout latest tag (for example resolves to "1.5.0" if that is the latest) │ 31 ------------------------------------------- - git checkout $(git describe --tags $(git rev-list --tags --max-count=1)) + # checkout latest official chipyard release + # note: this may not be the latest release if the documentation version != "stable" + git checkout |version| ./scripts/init-submodules-no-riscv-tools.sh This will initialize and checkout all of the necessary git submodules. diff --git a/docs/conf.py b/docs/conf.py index f78001c8..acf781f5 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -20,6 +20,8 @@ # import sys # sys.path.insert(0, os.path.abspath('.')) +import os +import subprocess # -- General configuration ------------------------------------------------ @@ -59,11 +61,32 @@ author = u'Berkeley Architecture Research' # The version info for the project you're documenting, acts as replacement for # |version| and |release|, also used in various other places throughout the # built documents. -# -# The short X.Y version. -version = u'' -# The full version, including alpha/beta/rc tags. -release = u'' + +on_rtd = os.environ.get("READTHEDOCS") == "True" +if on_rtd: + for item, value in os.environ.items(): + print("[READTHEDOCS] {} = {}".format(item, value)) + +if on_rtd: + rtd_version = os.environ.get("READTHEDOCS_VERSION") + if rtd_version == "latest": + version = "main" # TODO: default to what "latest" points to + elif rtd_version == "stable": + # get the latest git tag (which is what rtd normally builds under "stable") + # this works since rtd builds things within the repo + process = subprocess.Popen(["git", "describe", "--exact-match", "--tags"], stdout=subprocess.PIPE) + output = process.communicate()[0].decode("utf-8").strip() + if process.returncode == 0: + version = output + else: + version = "v?.?.?" # this should not occur as "stable" is always pointing to tagged version + else: + version = rtd_version # name of a branch +else: + version = "v?.?.?" + +# for now make these match +release = version # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. @@ -132,6 +155,17 @@ html_logo = '_static/images/chipyard-logo.png' # Output file base name for HTML help builder. htmlhelp_basename = 'Chipyarddoc' +# -- Misc Options --------------------------------------------------------- + +html_context = { + "version": version +} + +# add rst to end of each rst source file +# can put custom strings here that are generated from this file +rst_epilog = f""" +.. |overall_version| replace:: {version} +""" # -- Options for LaTeX output --------------------------------------------- diff --git a/docs/index.rst b/docs/index.rst index 3e0db05a..48791642 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,10 +1,5 @@ -.. Chipyard documentation master file, created by - sphinx-quickstart on Fri Mar 8 11:46:38 2019. - You can adapt this file completely to your liking, but it should at least - contain the root `toctree` directive. - -Welcome to Chipyard's documentation! -==================================== +Welcome to Chipyard's documentation (version "|version|")! +========================================================== .. image:: ./_static/images/chipyard-logo.svg diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 9d98e6f2..86420ac6 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -52,12 +52,12 @@ tag_ret_code=$? set -e if [ $tag_ret_code -ne 0 ]; then if [ "$SKIP_VALIDATE" = false ]; then - read -p "WARNING: You are not on a tagged release of Chipyard. Type \"ok\" to continue: " validate - [[ $validate == [oO][kK] ]] || exit 3 - echo "Setting up non-release Chipyard" + read -p "WARNING: You are not on an official release of Chipyard.\nType \"y\" to continue if this is intended, otherwise see https://chipyard.readthedocs.io/en/stable/Chipyard-Basics/Initial-Repo-Setup.html#setting-up-the-chipyard-repo: " validate + [[ $validate == [yY] ]] || exit 3 + echo "Setting up non-official Chipyard release" fi else - echo "Setting up Chipyard $tag" + echo "Setting up official Chipyard release: $tag" fi # On macOS, use GNU readlink from 'coreutils' package in Homebrew/MacPorts From 3435982c50b3c4912dfba3c4b7a642ea8b951778 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 15 Feb 2022 11:20:39 -0800 Subject: [PATCH 53/55] Fix skip-validate --- .github/actions/run-tests/action.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/actions/run-tests/action.yml b/.github/actions/run-tests/action.yml index d74b18af..05cc6498 100644 --- a/.github/actions/run-tests/action.yml +++ b/.github/actions/run-tests/action.yml @@ -17,7 +17,7 @@ runs: using: "composite" steps: - name: Init submodules (since only the RTL is cached) - run: ./scripts/init-submodules-no-riscv-tools.sh + run: ./scripts/init-submodules-no-riscv-tools.sh --skip-validate shell: bash # Note: You shouldn't need the other inputs since it shouldn't build RTL from scratch From 349664d9e369534a6ecda1805a7795f2a2ae5ec3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Dec 2021 16:58:53 -0800 Subject: [PATCH 54/55] Switch to shallow clone for all submodules --- .github/scripts/check-commit.sh | 12 +++++---- .gitmodules | 44 +++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 5 deletions(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index e056921d..cca86da1 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -9,6 +9,7 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh +# enter bhd repo cd $LOCAL_CHIPYARD_DIR # ignore the private vlsi submodules @@ -16,15 +17,16 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none -# initialize submodules and get the hashes -git submodule update --init -status=$(git submodule status) - all_names=() search_submodule() { echo "Running check on submodule $submodule in $dir" + # Initialize submodule and get the hashes + git submodule update --init $dir/$submodule + (cd $dir/$submodule && git fetch origin) + + status=$(git submodule status) hash=$(echo "$status" | grep "$dir.*$submodule " | awk '{print$1}' | grep -o "[[:alnum:]]*") for branch in "${branches[@]}" do @@ -47,7 +49,7 @@ search () { done } -submodules=("cva6" "ibex" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then diff --git a/.gitmodules b/.gitmodules index 11ca0d5a..d2d618ab 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,36 +1,47 @@ [submodule "rocket-chip"] path = generators/rocket-chip url = https://github.com/chipsalliance/rocket-chip.git + shallow = true [submodule "testchipip"] path = generators/testchipip url = https://github.com/ucb-bar/testchipip.git + shallow = true [submodule "barstools"] path = tools/barstools url = https://github.com/ucb-bar/barstools.git + shallow = true [submodule "tools/torture"] path = tools/torture url = https://github.com/ucb-bar/riscv-torture.git + shallow = true [submodule "generators/boom"] path = generators/boom url = https://github.com/riscv-boom/riscv-boom.git + shallow = true [submodule "generators/sifive-blocks"] path = generators/sifive-blocks url = https://github.com/sifive/sifive-blocks.git + shallow = true [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git + shallow = true [submodule "sims/firesim"] path = sims/firesim url = https://github.com/firesim/firesim.git + shallow = true [submodule "generators/icenet"] path = generators/icenet url = https://github.com/firesim/icenet.git + shallow = true [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache url = https://github.com/sifive/block-inclusivecache-sifive.git + shallow = true [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git + shallow = true [submodule "toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt"] path = toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt url = https://github.com/ucb-bar/chipyard-toolchain-prebuilt.git @@ -38,99 +49,132 @@ [submodule "toolchains/riscv-tools/riscv-isa-sim"] path = toolchains/riscv-tools/riscv-isa-sim url = https://github.com/riscv/riscv-isa-sim.git + shallow = true [submodule "toolchains/riscv-tools/riscv-pk"] path = toolchains/riscv-tools/riscv-pk url = https://github.com/riscv/riscv-pk.git + shallow = true [submodule "toolchains/riscv-tools/riscv-tests"] path = toolchains/riscv-tools/riscv-tests url = https://github.com/riscv/riscv-tests.git + shallow = true [submodule "toolchains/riscv-tools/riscv-openocd"] path = toolchains/riscv-tools/riscv-openocd url = https://github.com/riscv/riscv-openocd.git + shallow = true [submodule "toolchains/esp-tools/riscv-gnu-toolchain"] path = toolchains/esp-tools/riscv-gnu-toolchain url = https://github.com/ucb-bar/esp-gnu-toolchain.git + shallow = true [submodule "toolchains/esp-tools/riscv-isa-sim"] path = toolchains/esp-tools/riscv-isa-sim url = https://github.com/ucb-bar/esp-isa-sim.git + shallow = true [submodule "toolchains/esp-tools/riscv-pk"] path = toolchains/esp-tools/riscv-pk url = https://github.com/riscv/riscv-pk.git + shallow = true [submodule "toolchains/esp-tools/riscv-tests"] path = toolchains/esp-tools/riscv-tests url = https://github.com/ucb-bar/esp-tests.git + shallow = true [submodule "toolchains/libgloss"] path = toolchains/libgloss url = https://github.com/ucb-bar/libgloss-htif.git + shallow = true [submodule "vlsi/hammer"] path = vlsi/hammer url = https://github.com/ucb-bar/hammer.git + shallow = true [submodule "tools/dsptools"] path = tools/dsptools url = https://github.com/ucb-bar/dsptools.git + shallow = true [submodule "tools/chisel-testers"] path = tools/chisel-testers url = https://github.com/freechipsproject/chisel-testers.git + shallow = true [submodule "generators/sha3"] path = generators/sha3 url = https://github.com/ucb-bar/sha3.git + shallow = true [submodule "vlsi/hammer-cadence-plugins"] path = vlsi/hammer-cadence-plugins url = https://github.com/ucb-bar/hammer-cadence-plugins.git + shallow = true [submodule "vlsi/hammer-synopsys-plugins"] path = vlsi/hammer-synopsys-plugins url = https://github.com/ucb-bar/hammer-synopsys-plugins.git + shallow = true [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins url = https://github.com/ucb-bar/hammer-mentor-plugins.git + shallow = true [submodule "toolchains/qemu"] path = toolchains/qemu url = https://github.com/qemu/qemu.git + shallow = true [submodule "tools/axe"] path = tools/axe url = https://github.com/CTSRD-CHERI/axe.git + shallow = true [submodule "software/spec2017"] path = software/spec2017 url = https://github.com/ucb-bar/spec2017-workload.git + shallow = true [submodule "software/coremark"] path = software/coremark url = https://github.com/ucb-bar/coremark-workload.git + shallow = true [submodule "generators/gemmini"] path = generators/gemmini url = https://github.com/ucb-bar/gemmini + shallow = true [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git + shallow = true [submodule "generators/cva6"] path = generators/cva6 url = https://github.com/ucb-bar/cva6-wrapper.git + shallow = true [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git + shallow = true [submodule "generators/nvdla"] path = generators/nvdla url = https://github.com/ucb-bar/nvdla-wrapper.git + shallow = true [submodule "software/nvdla-workload"] path = software/nvdla-workload url = https://github.com/ucb-bar/nvdla-workload.git + shallow = true [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/riscv-boom/dromajo.git + shallow = true [submodule "generators/riscv-sodor"] path = generators/riscv-sodor url = https://github.com/ucb-bar/riscv-sodor.git + shallow = true [submodule "fpga/fpga-shells"] path = fpga/fpga-shells url = https://github.com/sifive/fpga-shells.git + shallow = true [submodule "tools/api-config-chipsalliance"] path = tools/api-config-chipsalliance url = https://github.com/chipsalliance/api-config-chipsalliance.git + shallow = true [submodule "tools/rocket-dsp-utils"] path = tools/rocket-dsp-utils url = https://github.com/ucb-bar/rocket-dsp-utils + shallow = true [submodule "generators/ibex"] path = generators/ibex url = https://github.com/ucb-bar/ibex-wrapper + shallow = true [submodule "generators/fft-generator"] path = generators/fft-generator url = https://github.com/ucb-bar/FFTGenerator.git + shallow = true From 4c1d860d22992bf760e7a0b8b37144cd9a5f6a27 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 14 Feb 2022 10:22:50 -0800 Subject: [PATCH 55/55] Update check commit w/ GH-A env + unshallow fetch --- .github/scripts/check-commit.sh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index cca86da1..70fbdaab 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -24,7 +24,7 @@ search_submodule() { echo "Running check on submodule $submodule in $dir" # Initialize submodule and get the hashes git submodule update --init $dir/$submodule - (cd $dir/$submodule && git fetch origin) + git -C $dir/$submodule fetch --unshallow status=$(git submodule status) hash=$(echo "$status" | grep "$dir.*$submodule " | awk '{print$1}' | grep -o "[[:alnum:]]*") @@ -51,7 +51,7 @@ search () { submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") dir="generators" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master" "main") else @@ -83,7 +83,7 @@ search submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017") dir="software" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master") else @@ -93,7 +93,7 @@ search submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "torture") dir="tools" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master") else @@ -108,7 +108,7 @@ search submodules=("firesim") dir="sims" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +if [ "$GITHUB_REF_NAME" == "master" ] || [ "$GITHUB_REF_NAME" == "dev" ] then branches=("master") else