Editing Docs
This commit is contained in:
Zitao Fang
@@ -3,21 +3,24 @@
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Adding a custom core
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====================
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You may want to add a custom RISC-V core to Chipyard generator. If the top module of your core is not in Chisel,
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you will first need to create a Verilog blackbox for it. See :ref:`incorporating-verilog-blocks` for instructions.
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Once you have a top module in Chisel, you are ready to create integrate it with Chipyard.
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``generators/ariane/src/main/scala/ArianeTile.scala`` and ``generators/boom/src/main/scala/common/tile.scala``
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provide two examples of how to integrate a core.
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You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides a step-to-step
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instruction on how to achieve this.
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.. note::
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RoCC is not supported by custom core currently. Please use Rocket or Boom as the RoCC base core if you need to use RoCC.
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RoCC is currently not supported by cores other than Rocket and BOOM. Please use Rocket or BOOM as the RoCC base core if you need to use RoCC.
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Parameter Case Classes
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----------------------
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Chipyard will generate a core for every ``InstantiableTileParams`` object it discovered in the current config.
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Wrap Verilog Module with Blackbox (Optional)
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--------------------------------------------
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Since Chipyard uses Scala and Chisel, if the top module of your core is not in Chisel, you will first need to create a Verilog
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blackbox for it so that it can be processed by Chipyard. See :ref:`incorporating-verilog-blocks` for instructions.
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Create Parameter Case Classes
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-----------------------------
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Chipyard will generate a core for every ``InstantiableTileParams`` object it discovered in the ``TilesLocated(InSubsystem)`` key.
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This object is derived from``TileParams``, a trait containing the information needed to create a tile. All cores must have
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their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``.
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@@ -41,7 +44,7 @@ need a custom field with similar purposes):
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val icache: Option[ICacheParams] // Rocket specific: I1 cache option
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val dcache: Option[DCacheParams] // Rocket specific: D1 cache option
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val btb: Option[BTBParams] // Rocket specific: BTB / branch predictor option
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val hartId: Int // Hart ID: Must be unique within a design config
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val hartId: Int // Hart ID: Must be unique within a design config (This MUST be a case class parameter)
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val beuAddr: Option[BigInt] // Rocket specific: Bus Error Unit for Rocket Core
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val blockerCtrlAddr: Option[BigInt] // Rocket specific: Bus Blocker for Rocket Core
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val name: Option[String] // Name of the core
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@@ -110,110 +113,64 @@ need a custom field with similar purposes):
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dfmaLatency: Int = 4 // Rocket specific: Fused multiply-add pipeline latency (double precision)
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)
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Most of the fields here are originally designed for Rocket core and contains some architecture-specific details, but
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Most of the fields here are originally designed for the Rocket core and thus contain some implementation-specific details, but
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many of them are general enough to be useful for other cores. It is strongly recommended to use these fields instead
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of creating your own custom fields when applicable.
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You will also need a ``CanAttachTile`` class to add the tile config into the config system, with the following format:
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
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:language: scala
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:lines: 61-67
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.. note::
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Implementations may choose to ignore some fields here or use them in a non-standard way, but using an inaccurate
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value may break Chipyard components that rely on them (e.g. inaccurate indication of supported ISA extension will
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result in incorrect test suite being generated) as well as any custom module that use them. ALWAYS document any
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value may break Chipyard components that rely on them (e.g. an inaccurate indication of supported ISA extension will
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result in an incorrect test suite being generated) as well as any custom modules that use them. ALWAYS document any
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fields you ignore or with altered usage in your core implementation, and if you are implementing other devices that
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would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but
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you should document them if you use them.
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Tile Class
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----------
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Create Tile Class
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-----------------
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In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System
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interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated.
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See :ref:`tilelink_and_diplomacy` for more details.
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See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core.
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All tile classes implement ``BaseTile`` and will normally implement ``SinksExternalInterrupts`` and ``SourcesExternalNotifications``,
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which allow the tile to accept external interrupt. A typical tile has the following form:
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.. code-block:: scala
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
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:language: scala
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:lines: 87-125, 143
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class MyTile(
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val myParams: MyTileParams,
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crossing: ClockCrossingType,
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lookup: LookupByHartIdImpl,
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q: Parameters,
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logicalTreeNode: LogicalTreeNode)
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extends BaseTile(myParams, crossing, lookup, q)
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with SinksExternalInterrupts
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with SourcesExternalNotifications
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{
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Connect TileLink Buses
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----------------------
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// Private constructor ensures altered LazyModule.p is used implicitly
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def this(params: MyTileParams, crossing: RocketCrossingParams, lookup: LookupByHartIdImpl, logicalTreeNode: LogicalTreeNode)(implicit p: Parameters) =
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this(params, crossing.crossingType, lookup, p, logicalTreeNode)
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// Require TileLink nodes
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val intOutwardNode = IntIdentityNode()
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val masterNode = visibilityNode
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val slaveNode = TLIdentityNode()
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// Implementation class (See below)
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override lazy val module = new MyTileModuleImp(this)
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// Required entry of CPU device in the device tree for interrupt purpose
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val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("my-organization,my-cpu", "riscv")) {
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override def parent = Some(ResourceAnchors.cpus)
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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Description(name, mapping ++
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cpuProperties ++
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nextLevelCacheProperty ++
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tileProperties)
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}
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}
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ResourceBinding {
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Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
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}
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// (Connection to bus, interrupt, etc.)
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}
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TileLink Connection
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-------------------
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Chipyard use TileLink as its onboard bus protocol, and if your core doesn't use TileLink, you will need to convert them
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Chipyard use TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters
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between the core's memory protocol and TileLink in the Tile module.
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in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by
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Chipyards:
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Rocket chip:
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.. code-block:: scala
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val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node
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(tlMasterXbar.node // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar
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:= memoryTap
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:= TLBuffer()
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:= TLFIFOFixer(TLFIFOFixer.all) // fix FIFO ordering
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:= TLWidthWidget(beatBytes) // reduce size of TL
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:= AXI4ToTL() // convert to TL
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:= AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed
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:= AXI4Fragmenter() // deal with multi-beat xacts
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:= memAXI4Node) // The custom node, see below
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
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:language: scala
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:lines: 133-142
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Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate
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widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also
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provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the
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source files in ``generators/rocket-chip/src/main/scala/amba`` for more info.
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If you are using other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba``
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If you are using some other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba``
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as the template, but it is not recommended unless you are familiar with TileLink.
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``memAXI4Node`` is an AXI4 master node and is defined as following in our example:
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.. code-block:: scala
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val memAXI4Node = AXI4MasterNode(
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Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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name = portName,
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id = IdRange(0, 1 << idBits))))))
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
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:language: scala
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:lines: 126-132
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where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile.
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Make sure to read :ref:`node_types` to check out what type of nodes Chipyard supports and their parameters!
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@@ -228,8 +185,8 @@ can override the following two functions to control how to buffer the bus reques
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You can find more information on ``TLBuffer`` in :ref:`diplomatic_widgets`.
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Interrupt
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---------
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Connect Interrupt
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-----------------
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Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices.
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In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and
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@@ -258,48 +215,33 @@ from the implementation class:
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reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating)
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reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed
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Implementation Class
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--------------------
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Create Implementation Class
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---------------------------
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The implementation class is of the following form:
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The implementation class for your core is of the following form:
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.. code-block:: scala
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class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
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// annotate the parameters
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Annotated.params(this, outer.tileParams)
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// TODO: Create the top module of the core and connect it with the ports in "outer"
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}
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
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:language: scala
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:lines: 145-149, 160
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In the body of this class, you can look up any parameters by calling ``p({key})``, where ``{key}`` is the config key of
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the value you want to look up. For a list of available keys, see the appendix below.
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the value you want to look up. For a list of frequently used keys, see the appendix below.
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If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this:
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.. code-block:: scala
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
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:language: scala
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:lines: 151-159
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outer.myAXI4Node.out foreach { case (out, edgeOut) =>
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// Connect your module IO port to "out"
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// The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala
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// Please refer to this file for the definition of the ports.
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// If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala
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// If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala
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// (choose one depends on the type of AHB node you create)
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// If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala
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}
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Create Config Fragments to Integrate the Core
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---------------------------------------------
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Integrate the Core
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------------------
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To use your core in a set of config, you would need a config fragment that would create a ``TileParams`` object of your core in
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To use your core in a Chipyard config, you would need a config fragment that would create a ``TileParams`` object of your core in
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the current config. An example of such config will be like this:
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.. code-block:: scala
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class WithNMyCores(n: Int, hartidOffset: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) :++ List.tabulate(n)(i => MyTileParams(hartId = i + hartidOffset))
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})
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
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:language: scala
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:lines: 162-179
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Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``.
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This config fragment simply appends new tile parameters to the end of this list.
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@@ -308,6 +250,9 @@ Now you have finished all the steps to prepare your cores for Chipyard! To gener
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in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`.
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You can now run any desired workflow for the new config just as you do for the built-in cores.
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If you would like to see how an actual core are integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala``
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provides a concrete example of integrating a third party Verilog core Ariane.
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Appendix: Common Config Keys
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----------------------------
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179
generators/chipyard/src/main/scala/example/TutorialTile.scala
Normal file
179
generators/chipyard/src/main/scala/example/TutorialTile.scala
Normal file
@@ -0,0 +1,179 @@
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package chipyard.example
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode}
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.subsystem.{RocketCrossingParams}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.amba.axi4._
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// Example parameter class copied from Ariane, not included in documentation but for compile check only
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// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
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// out what parameters you need before you write the parameter class
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case class MyCoreParams(
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bootFreqHz: BigInt = BigInt(1700000000),
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rasEntries: Int = 4,
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btbEntries: Int = 16,
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bhtEntries: Int = 16,
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enableToFromHostCaching: Boolean = false,
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) extends CoreParams {
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val useVM: Boolean = true
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val useUser: Boolean = true
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val useSupervisor: Boolean = false
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val useDebug: Boolean = true
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val useAtomics: Boolean = true
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val useAtomicsOnlyForIO: Boolean = false // copied from Rocket
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val useCompressed: Boolean = true
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override val useVector: Boolean = false
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val useSCIE: Boolean = false
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val useRVE: Boolean = false
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val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket
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val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
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val nLocalInterrupts: Int = 0
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val nPMPs: Int = 0 // TODO: Check
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val pmpGranularity: Int = 4 // copied from Rocket
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val nBreakpoints: Int = 0 // TODO: Check
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val useBPWatch: Boolean = false
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val nPerfCounters: Int = 29
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val haveBasicCounters: Boolean = true
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val haveFSDirty: Boolean = false
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val misaWritable: Boolean = false
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val haveCFlush: Boolean = false
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val nL2TLBEntries: Int = 512 // copied from Rocket
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val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket
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val mtvecWritable: Boolean = true // copied from Rocket
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val instBits: Int = if (useCompressed) 16 else 32
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val lrscCycles: Int = 80 // copied from Rocket
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val decodeWidth: Int = 1 // TODO: Check
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val fetchWidth: Int = 1 // TODO: Check
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val retireWidth: Int = 2
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}
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case class MyTileAttachParams(
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tileParams: MyTileParams,
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crossingParams: RocketCrossingParams
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) extends CanAttachTile {
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type TileType = MyTile
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val lookup = PriorityMuxHartIdFromSeq(Seq(tileParams))
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}
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case class MyTileParams(
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name: Option[String] = Some("my_tile"),
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hartId: Int = 0,
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trace: Boolean = false,
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val core: MyCoreParams = MyCoreParams()
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) extends InstantiableTileParams[MyTile]
|
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{
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val beuAddr: Option[BigInt] = None
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val blockerCtrlAddr: Option[BigInt] = None
|
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val btb: Option[BTBParams] = Some(BTBParams())
|
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val boundaryBuffers: Boolean = false
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val dcache: Option[DCacheParams] = Some(DCacheParams())
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val icache: Option[ICacheParams] = Some(ICacheParams())
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def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
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new MyTile(this, crossing, lookup)
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}
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||||
}
|
||||
|
||||
class MyTile(
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val myParams: MyTileParams,
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crossing: ClockCrossingType,
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lookup: LookupByHartIdImpl,
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q: Parameters)
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||||
extends BaseTile(myParams, crossing, lookup, q)
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||||
with SinksExternalInterrupts
|
||||
with SourcesExternalNotifications
|
||||
{
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||||
|
||||
// Private constructor ensures altered LazyModule.p is used implicitly
|
||||
def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
|
||||
this(params, crossing.crossingType, lookup, p)
|
||||
|
||||
// Require TileLink nodes
|
||||
val intOutwardNode = IntIdentityNode()
|
||||
val masterNode = visibilityNode
|
||||
val slaveNode = TLIdentityNode()
|
||||
|
||||
// Implementation class (See below)
|
||||
override lazy val module = new MyTileModuleImp(this)
|
||||
|
||||
// Required entry of CPU device in the device tree for interrupt purpose
|
||||
val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("my-organization,my-cpu", "riscv")) {
|
||||
override def parent = Some(ResourceAnchors.cpus)
|
||||
override def describe(resources: ResourceBindings): Description = {
|
||||
val Description(name, mapping) = super.describe(resources)
|
||||
Description(name, mapping ++
|
||||
cpuProperties ++
|
||||
nextLevelCacheProperty ++
|
||||
tileProperties)
|
||||
}
|
||||
}
|
||||
|
||||
ResourceBinding {
|
||||
Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
|
||||
}
|
||||
|
||||
// (Connection to bus, interrupt, etc.)
|
||||
// # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more.
|
||||
val idBits = 4
|
||||
val memAXI4Node = AXI4MasterNode(
|
||||
Seq(AXI4MasterPortParameters(
|
||||
masters = Seq(AXI4MasterParameters(
|
||||
name = "myPortName",
|
||||
id = IdRange(0, 1 << idBits))))))
|
||||
val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node
|
||||
(tlMasterXbar.node // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar
|
||||
:= memoryTap
|
||||
:= TLBuffer()
|
||||
:= TLFIFOFixer(TLFIFOFixer.all) // fix FIFO ordering
|
||||
:= TLWidthWidget(masterPortBeatBytes) // reduce size of TL
|
||||
:= AXI4ToTL() // convert to TL
|
||||
:= AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed
|
||||
:= AXI4Fragmenter() // deal with multi-beat xacts
|
||||
:= memAXI4Node) // The custom node, see below
|
||||
}
|
||||
|
||||
class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
|
||||
// annotate the parameters
|
||||
Annotated.params(this, outer.myParams)
|
||||
|
||||
// TODO: Create the top module of the core and connect it with the ports in "outer"
|
||||
|
||||
outer.memAXI4Node.out foreach { case (out, edgeOut) =>
|
||||
// Connect your module IO port to "out"
|
||||
// The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala
|
||||
// Please refer to this file for the definition of the ports.
|
||||
// If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala
|
||||
// If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala
|
||||
// (choose one depends on the type of AHB node you create)
|
||||
// If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala
|
||||
}
|
||||
}
|
||||
|
||||
class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
|
||||
case TilesLocated(InSubsystem) => {
|
||||
// Calculate the next available hart ID (since hart ID cannot be duplicated)
|
||||
val prev = up(TilesLocated(InSubsystem), site)
|
||||
val idOffset = overrideIdOffset.getOrElse(prev.size)
|
||||
// Create TileAttachParams for every core to be instantiated
|
||||
(0 until n).map { i =>
|
||||
MyTileAttachParams(
|
||||
tileParams = MyTileParams(hartId = i + idOffset),
|
||||
crossingParams = RocketCrossingParams()
|
||||
)
|
||||
} ++ prev
|
||||
}
|
||||
// Configurate # of bytes in one memory / IO transaction. For RV64, one load/store instruction can transfer 8 bytes at most.
|
||||
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
|
||||
// The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits.
|
||||
case XLen => 64
|
||||
})
|
||||
Reference in New Issue
Block a user