diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
index 3b420be1..1d79fbc0 100644
--- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
@@ -40,35 +40,32 @@ class RadianceBaseConfig(argsBinFilename: String = "args.bin") extends Config(
   new WithExtMemSize(BigInt("80000000", 16)) ++
   new WithRadBootROM() ++
   new WithRadROMs(0x7FFF0000L, 0x10000, s"sims/${argsBinFilename}") ++
-  new WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++
 //  new chipyard.harness.WithCeaseSuccess ++
   new chipyard.iobinders.WithCeasePunchThrough ++
   new radiance.subsystem.WithRadianceSimParams(true) ++
   new WithCacheBlockBytes(64) ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
+  new freechips.rocketchip.subsystem.WithEdgeDataBits(256) ++
   new AbstractConfig)
 
-class RadianceConfig extends Config(
-  // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16) ++
-  new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), useVxCache = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new RadianceBaseConfig)
-
 class RadianceClusterConfig extends Config(
   // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16) ++
-  new radiance.subsystem.WithRadianceCores(2, location = InCluster(0),
-    // crossing = RocketCrossingParams(master = HierarchicalElementMasterPortParams(where = CMBUS(0))),
-    useVxCache = false) ++
+  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
+  new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++
+  new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++
+  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++
   new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
   new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
-  new radiance.subsystem.WithRadianceCluster(0,
-    // crossing = RocketCrossingParams(master = HierarchicalElementMasterPortParams(where = MBUS))
-  ) ++
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
-  new freechips.rocketchip.subsystem.WithEdgeDataBits(256) ++
+  new radiance.subsystem.WithRadianceCluster(0) ++
+  new RadianceBaseConfig)
+
+class Radiance16KClusterConfig extends Config(
+  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++
+  new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++
+  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10, numBanks = 4, numWords = 8) ++
+  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
+  new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
+  new radiance.subsystem.WithRadianceCluster(0) ++
   new RadianceBaseConfig)
 
 class RadianceClusterConfig0 extends Config(
diff --git a/generators/gemmini b/generators/gemmini
index 8a9c4239..38d10203 160000
--- a/generators/gemmini
+++ b/generators/gemmini
@@ -1 +1 @@
-Subproject commit 8a9c423900766ea59efefd4ce51e40cd242555b4
+Subproject commit 38d10203c187cd460b430cb890177b3f83107e1e
diff --git a/generators/radiance b/generators/radiance
index 697c37b9..17756d5f 160000
--- a/generators/radiance
+++ b/generators/radiance
@@ -1 +1 @@
-Subproject commit 697c37b9801ed30c6d1a4ee74ab2647dee97a2d3
+Subproject commit 17756d5f530d0d2c2869531834038a20baef2311
diff --git a/sims/parse_printf.py b/sims/parse_printf.py
index 3f04fffa..267c042f 100644
--- a/sims/parse_printf.py
+++ b/sims/parse_printf.py
@@ -1,6 +1,7 @@
 import sys
 
-PRINT_BUF = 0x4000 / 4
+# PRINT_BUF = 0x4000 / 4
+PRINT_BUF = 0x10000 / 4
 
 def parse_log_file(log_file_path):
     target_string = ''  # Initialize the string we'll build from hex values
@@ -24,7 +25,7 @@ def parse_log_file(log_file_path):
 
                 # print(rs1_data_last_element)
                 for rs1, rs2, byteen in zip(rs1_data_elts, rs2_data_elts, byteen_elts):
-                    if '0x3fc0' in rs1:
+                    if int(rs1, 16) >> 18 == 0xff0:
                         offset = (int(rs1, 16) - PRINT_BUF) % 65536
                         if offset < 0 or offset >= 1024:
                             continue
@@ -89,7 +90,7 @@ def main():
         sys.exit(1)
 
     log_file_path = sys.argv[1]
-    if log_file_path[-4:] == "log":
+    if log_file_path[-4:] == ".log":
         print(parse_log_file(log_file_path))
     else:
         print(parse_out_file(log_file_path))