From 74c1c9d7aba6df6157da3719f0247687e2ed4e33 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 15 Oct 2020 10:00:07 -0700 Subject: [PATCH] Punch out reset in AXI4MMIO IOBinder --- generators/chipyard/src/main/scala/IOBinders.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 8537b418..87480bfc 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -282,10 +282,12 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { - val ports: Seq[ClockedIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => - val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") + val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => + val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") p.bits <> m - p.clock := BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) + val mbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS) + p.clock := BoreHelper("axi4_mmio_clock", mbus.module.clock) + p.reset := BoreHelper("axi4_mmio_reset", mbus.module.reset) p }) (ports, Nil)