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Fix CI | Fix Verilator compile

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This commit is contained in:
abejgonzalez
2023-11-02 17:27:42 -07:00
parent 0c1ca5750e
commit 7525b9fd04
3 changed files with 3 additions and 3 deletions
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2
.github/scripts/check-commit.sh vendored
View File

@@ -45,7 +45,7 @@ search () {
done
}
submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle")
submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "caliptra-aes-acc" "rocc-acc-utils")
dir="generators"
branches=("master" "main" "dev")
search

2
.github/scripts/defaults.sh vendored
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@@ -67,7 +67,7 @@ mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig verilog"
mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
mapping["constellation"]=" SUB_PROJECT=constellation"
mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"

2
generators/caliptra-aes-acc

Submodule generators/caliptra-aes-acc updated: 350cf7fbf5...15d2f85262