Bump rc/components to improve module naming

generators/chipyard/src/main/scala/clocking/ClockBinders.scala

@@ -27,9 +27,9 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr
     val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
     val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
-    clockDivider.tlNode  := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
+    clockDivider.tlNode  := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
-    clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
+    clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
-    pllCtrl.tlNode       := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
+    pllCtrl.tlNode       := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
 
     system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 

generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala

@@ -28,6 +28,7 @@ class ClockGroupParameterModifier(
     sinkFn:   ClockGroupSinkParameters   => ClockGroupSinkParameters   = { s => s })(
     implicit p: Parameters, v: ValName) extends LazyModule {
   val node = ClockGroupAdapterNode(sourceFn, sinkFn)
+  override def shouldBeInlined = true
   lazy val module = new LazyRawModuleImp(this) {
     (node.out zip node.in).map { case ((o, _), (i, _)) =>
       (o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD }

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -40,7 +40,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
   val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
     .suggestName("chipyard_prcictrl_domain")
 
-  val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
+  val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } }
   prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
     := TLFIFOFixer(TLFIFOFixer.all)
     := TLBuffer()
@@ -71,13 +71,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
   }
   val tileClockGater     = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
     val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
-    clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
+    clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get
     clock_gater
   } }
   val tileResetSetter    = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
     val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
       tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
-    reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
+    reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get
     reset_setter
   } }
 

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -123,7 +123,6 @@ class AbstractConfig extends Config(
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
   new chipyard.config.WithSV48IfPossible ++                         /** use sv48 if possible */
 
-
   // ================================================
   //   Set up power, reset and clocking
   // ================================================

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -7,6 +7,8 @@ import testchipip.soc.{OBUS}
 
 // A simple config demonstrating how to set up a basic chip in Chipyard
 class ChipLikeRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+
   //==================================
   // Set up TestHarness
   //==================================

generators/chipyard/src/main/scala/config/NoCoreConfigs.scala

@@ -13,9 +13,9 @@ class NoCoresConfig extends Config(
   new chipyard.config.WithNoUART ++
   new chipyard.config.WithNoTileClockGaters ++
   new chipyard.config.WithNoTileResetSetters ++
-  new chipyard.config.WithNoBusErrorDevices ++
   new chipyard.config.WithNoDebug ++
   new chipyard.config.WithNoPLIC ++
+  new chipyard.config.WithNoBusErrorDevices ++
   new chipyard.config.AbstractConfig)
 
 // A config that uses a empty chiptop module with no rocket-chip soc components