From 8a60b3612541450124d1ba80890de20dda9b992c Mon Sep 17 00:00:00 2001 From: Nikhil Jha Date: Fri, 26 May 2023 14:02:19 -0700 Subject: [PATCH 01/27] doc: add higher level explanations of RoCC + more resources --- docs/Customization/RoCC-Accelerators.rst | 53 ++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/docs/Customization/RoCC-Accelerators.rst b/docs/Customization/RoCC-Accelerators.rst index 79d9e898..a2d98589 100644 --- a/docs/Customization/RoCC-Accelerators.rst +++ b/docs/Customization/RoCC-Accelerators.rst @@ -1,10 +1,15 @@ .. _rocc-accelerators: Adding a RoCC Accelerator ----------------------------- +------------------------- -RoCC accelerators are lazy modules that extend the ``LazyRoCC`` class. -Their implementation should extends the ``LazyRoCCModule`` class. +A RoCC accelerator is a component that can be added into a particular Rocket or BooM tile. +It receives instructions that match a certain opcode, talks to other parts of the core or SoC (L1, L2, PTW, FPU), and then optionally writes back a value into the register corresponding with the ``rd`` field of the instruction. +RoCC accelerators are instantiated via modules that extend the ``LazyRoCC`` class. +These modules lazily instantiate another module which extends the ``LazyRoCCModule`` class. +This extra layer of indirection is used so that Diplomacy can figure out how to connect the RoCC module to the chip, without needing to instantiate the module ahead of time. +Lazy modules are further explained in the :ref:`Chipyard-Basics/Configs-Parameters-Mixins:Cake Pattern / Mixin` section. +Below is a minimal instantiation of a RoCC accelerator. .. code-block:: scala @@ -31,7 +36,6 @@ Their implementation should extends the ``LazyRoCCModule`` class. ... } - The ``opcodes`` parameter for ``LazyRoCC`` is the set of custom opcodes that will map to this accelerator. More on this in the next subsection. @@ -46,6 +50,46 @@ the ``busy`` signal, which indicates when the accelerator is still handling an i and the ``interrupt`` signal, which can be used to interrupt the CPU. Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala`` for detailed information on the different IOs. +There is also more information about each of the signals in `the RoCC Documentation written by UCSD `_, although it is updated out of tree and may be out of date. + + +Accessing Memory via L1 Cache +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +A RoCC accelerator can access memory through the L1 Cache of the core it is attached to. +This is a simpler interface for accelerator architects to implement, but will generally have lower achievable throughput than a dedicated TileLink port. + +In your ``LazyRoCCModuleImp``, the signal ``io.mem`` is a ``HellaCacheIO``, which is defined in ``generators/rocket-chip/src/main/scala/rocket/HellaCache.scala``. + +.. code-block:: scala + + class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { + val req = Decoupled(new HellaCacheReq) + val s1_kill = Output(Bool()) // kill previous cycle's req + val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req + val s2_nack = Input(Bool()) // req from two cycles ago is rejected + val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) + val s2_kill = Output(Bool()) // kill req from two cycles ago + val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO + val s2_paddr = Input(UInt(paddrBits.W)) // translated address + + val resp = Flipped(Valid(new HellaCacheResp)) + val replay_next = Input(Bool()) + val s2_xcpt = Input(new HellaCacheExceptions) + val s2_gpa = Input(UInt(vaddrBitsExtended.W)) + val s2_gpa_is_pte = Input(Bool()) + val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) + val ordered = Input(Bool()) + val perf = Input(new HellaCachePerfEvents()) + + val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? + val clock_enabled = Input(Bool()) // is D$ currently being clocked? + } + +At a high level, you must tag requests that you send across this interface using the ``io.mem.req.tag``, and the tag will be returned to you when the data is ready. +Responses may come back out of order if you issue multiple requests, so you can use these tags to tell what data came back. +Note that the top two bits of the tag are reserved, and MUST be set to zero, or the interface will exhibit undefined behavior. + Adding RoCC accelerator to Config ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -67,3 +111,4 @@ For instance, if we wanted to add the previously defined accelerator and route c new RocketConfig) To add RoCC instructions in your program, use the RoCC C macros provided in ``tests/rocc.h``. You can find examples in the files ``tests/accum.c`` and ``charcount.c``. + From cb24357a8abcf094e324f2d2e189a7cea50b48da Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 8 Jun 2023 10:52:49 -0700 Subject: [PATCH 02/27] Ignore barstools compilation if not needed --- common.mk | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/common.mk b/common.mk index 9bb2f94c..981d9f4a 100644 --- a/common.mk +++ b/common.mk @@ -68,7 +68,7 @@ include $(base_dir)/tools/torture.mk ######################################################################################### # Prerequisite lists ######################################################################################### -# Returns a list of files in directory $1 with file extension $2. +# Returns a list of files in directories $1 with single file extension $2. # If available, use 'fd' to find the list of files, which is faster than 'find'. ifeq ($(shell which fd 2> /dev/null),) lookup_srcs = $(shell find -L $(1)/ -name target -prune -o \( -iname "*.$(2)" ! -iname ".*" \) -print 2> /dev/null) @@ -76,9 +76,17 @@ else lookup_srcs = $(shell fd -L -t f -e $(2) . $(1)) endif -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools fpga/fpga-shells fpga/src) -SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) -VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) +# Returns a list of files in directories $1 with *any* of the file extensions in $2 +lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type))) + +SCALA_EXT = scala +VLOG_EXT = sv v +CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src) +CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT)) +CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT)) +BARSTOOLS_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/barstools) +BARSTOOLS_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(SCALA_EXT)) +BARSTOOLS_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(VLOG_EXT)) # This assumes no SBT meta-build sources SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties @@ -106,12 +114,12 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) +$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) mkdir -p $(dir $@) $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS) +$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -206,13 +214,13 @@ else echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@ endif -$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LEVEL) +$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL) if [ $(shell cat $(SFC_LEVEL)) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $@; fi if [ $(shell cat $(SFC_LEVEL)) = none ]; then cat $(EXTRA_ANNO_FILE) > $@; fi touch $@ $(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX) -$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) +$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) $(CHIPYARD_VLOG_SOURCES) $(BARSTOOLS_VLOG_SOURCES) rm -rf $(GEN_COLLATERAL_DIR) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\ --no-dedup \ From 5ccd2b8bb4182c51ed2fed11ac4c0aac2323ce55 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 8 Jun 2023 13:42:09 -0700 Subject: [PATCH 03/27] Fix parallelism issue --- common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/common.mk b/common.mk index 981d9f4a..7e0f664b 100644 --- a/common.mk +++ b/common.mk @@ -208,6 +208,7 @@ else endif $(MFC_LOWERING_OPTIONS): + mkdir -p $(dir $@) ifeq (,$(ENABLE_YOSYS_FLOW)) echo "$(MFC_BASE_LOWERING_OPTIONS)" > $@ else From 4328041c259a25751c7830788dbe6ca3711df263 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 31 May 2023 22:10:47 -0700 Subject: [PATCH 04/27] Add shuttle core --- .gitmodules | 3 ++ .../main/scala/config/ShuttleConfigs.scala | 32 +++++++++++++++++++ generators/shuttle | 1 + 3 files changed, 36 insertions(+) create mode 100644 generators/chipyard/src/main/scala/config/ShuttleConfigs.scala create mode 160000 generators/shuttle diff --git a/.gitmodules b/.gitmodules index 5a3eb6fc..ea6b5ddb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -124,3 +124,6 @@ [submodule "software/embench/embench-iot"] path = software/embench/embench-iot url = https://github.com/embench/embench-iot.git +[submodule "shuttle"] + path = generators/shuttle + url = https://github.com/ucb-bar/shuttle.git diff --git a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala new file mode 100644 index 00000000..6e86e020 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala @@ -0,0 +1,32 @@ +package chipyard + +import org.chipsalliance.cde.config.{Config} + +//----------------- +// Shuttle Configs +//----------------- + +class ShuttleConfig extends Config( + new shuttle.common.WithNShuttleCores ++ + new chipyard.config.AbstractConfig) + +class ShuttleCosimConfig extends Config( + new chipyard.harness.WithCospike ++ // attach spike-cosim + new chipyard.config.WithTraceIO ++ + new shuttle.common.WithShuttleDebugROB ++ + new shuttle.common.WithNShuttleCores ++ + new chipyard.config.AbstractConfig) + +class dmiShuttleCosimConfig extends Config( + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl + new chipyard.harness.WithCospike ++ // attach spike-cosim + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new chipyard.config.WithTraceIO ++ + new shuttle.common.WithShuttleDebugROB ++ + new shuttle.common.WithNShuttleCores ++ + new chipyard.config.AbstractConfig) + +class GemminiShuttleConfig extends Config( + new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accel + new shuttle.common.WithNShuttleCores ++ + new chipyard.config.AbstractConfig) diff --git a/generators/shuttle b/generators/shuttle new file mode 160000 index 00000000..3c15591a --- /dev/null +++ b/generators/shuttle @@ -0,0 +1 @@ +Subproject commit 3c15591a9ee237bb1251e5362de22ad19f64ba07 From 4b7c1701043cf317fe677ef935ad91835c69fdcc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Jun 2023 11:00:35 -0700 Subject: [PATCH 05/27] Add shuttle core CI --- .github/scripts/check-commit.sh | 2 +- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 3 +++ .github/workflows/chipyard-run-tests.yml | 24 ++++++++++++++++++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index fe1de2bf..8103cc4e 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "shuttle") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 1c1b7def..4aee981b 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -28,7 +28,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" +grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-shuttle" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla" grouping["group-constellation"]="chipyard-constellation" @@ -61,6 +61,7 @@ mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" +mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig" mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig" mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig" mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 4a5a0802..a21434da 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -46,6 +46,9 @@ case $1 in chipyard-boom) run_bmark ${mapping[$1]} ;; + chipyard-shuttle) + run_bmark ${mapping[$1]} + ;; chipyard-dmiboom) $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000 make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 02de6935..5b9a2b0f 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -488,6 +488,29 @@ jobs: group-key: "group-cores" project-key: "chipyard-boom" + chipyard-shuttle-run-tests: + name: chipyard-shuttle-run-tests + needs: prepare-chipyard-cores + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-cores" + project-key: "chipyard-shuttle" + chipyard-cva6-run-tests: name: chipyard-cva6-run-tests needs: prepare-chipyard-cores @@ -1026,6 +1049,7 @@ jobs: chipyard-rocket-run-tests, chipyard-hetero-run-tests, chipyard-boom-run-tests, + chipyard-shuttle-run-tests, chipyard-cva6-run-tests, chipyard-ibex-run-tests, chipyard-sodor-run-tests, From 389f2dde9c9ba143ced55b565d17a40c199d77f9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Jun 2023 11:25:03 -0700 Subject: [PATCH 06/27] Add shuttle to build.sbt --- build.sbt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 6f72940a..a02caa8a 100644 --- a/build.sbt +++ b/build.sbt @@ -153,7 +153,7 @@ lazy val chipyard = (project in file("generators/chipyard")) sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, shuttle) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -198,6 +198,11 @@ lazy val boom = (project in file("generators/boom")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +lazy val shuttle = (project in file("generators/shuttle")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) From b0504e303a0ca0964ff26f46af58a0852094d492 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Jun 2023 17:15:17 -0700 Subject: [PATCH 07/27] Update tutorial-patches --- scripts/tutorial-patches/build.sbt.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index db81b052..67c86312 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -10,7 +10,7 @@ index ec36a85f..c0c2849a 100644 +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, shuttle) @@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) From bbcb8f40893e334fc852c67fb0a9a09339af3532 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Jun 2023 09:24:11 -0700 Subject: [PATCH 08/27] Improvements to cospike --- .../src/main/resources/csrc/cospike.cc | 122 ++++++++++++++---- 1 file changed, 99 insertions(+), 23 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index e1558ba1..bc30021a 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -2,6 +2,8 @@ #include #include #include +#include +#include #include #include #include @@ -27,7 +29,11 @@ extern std::map backing_mem_data; #endif #define CLINT_BASE (0x2000000) -#define CLINT_SIZE (0x1000) +#define CLINT_SIZE (0x10000) +#define UART_BASE (0x54000000) +#define UART_SIZE (0x1000) +#define PLIC_BASE (0xc000000) +#define PLIC_SIZE (0x4000000) typedef struct system_info_t { std::string isa; @@ -38,13 +44,33 @@ typedef struct system_info_t { std::vector bootrom; }; +class read_override_device_t : public abstract_device_t { +public: + read_override_device_t(std::string n, reg_t sz) : was_read_from(false), size(size), name(n) { }; + bool load(reg_t addr, size_t len, uint8_t* bytes) { + if (addr + len < addr || addr + len > size) return false; + printf("Read from device %s at %lx\n", name.c_str(), addr); + was_read_from = true; + return true; + } + bool store(reg_t addr, size_t len, const uint8_t* bytes) { + return (addr + len >= addr && addr + len <= size); + } + bool was_read_from; +private: + reg_t size; + std::string name; +}; + system_info_t* info = NULL; sim_t* sim = NULL; bool cospike_debug; reg_t tohost_addr = 0; reg_t fromhost_addr = 0; +reg_t cospike_timeout = 0; std::set magic_addrs; cfg_t* cfg; +std::vector read_override_devices; static std::vector> make_mems(const std::vector &layout) { @@ -90,6 +116,7 @@ extern "C" void cospike_cosim(long long int cycle, int priv) { assert(info); + if (unlikely(!sim)) { printf("Configuring spike cosim\n"); std::vector mem_cfg; @@ -114,19 +141,31 @@ extern "C" void cospike_cosim(long long int cycle, std::vector> mems = make_mems(cfg->mem_layout()); + size_t default_boot_rom_size = 0x10000; + size_t default_boot_rom_addr = 0x10000; + assert(info->bootrom.size() < default_boot_rom_size); + info->bootrom.resize(default_boot_rom_size); + rom_device_t *boot_rom = new rom_device_t(info->bootrom); mem_t *boot_addr_reg = new mem_t(0x1000); uint64_t default_boot_addr = 0x80000000; boot_addr_reg->store(0, 8, (const uint8_t*)(&default_boot_addr)); - // Don't actually build a clint - mem_t* clint_mem = new mem_t(CLINT_SIZE); + read_override_device_t* clint = new read_override_device_t("clint", CLINT_SIZE); + read_override_device_t* uart = new read_override_device_t("uart", UART_SIZE); + read_override_device_t* plic = new read_override_device_t("plic", PLIC_SIZE); + + read_override_devices.push_back(clint); + read_override_devices.push_back(uart); + read_override_devices.push_back(plic); std::vector> plugin_devices; // The device map is hardcoded here for now plugin_devices.push_back(std::pair(0x4000, boot_addr_reg)); - plugin_devices.push_back(std::pair(0x10000, boot_rom)); - plugin_devices.push_back(std::pair(CLINT_BASE, clint_mem)); + plugin_devices.push_back(std::pair(default_boot_rom_addr, boot_rom)); + plugin_devices.push_back(std::pair(CLINT_BASE, clint)); + plugin_devices.push_back(std::pair(UART_BASE, uart)); + plugin_devices.push_back(std::pair(PLIC_BASE, plic)); s_vpi_vlog_info vinfo; if (!vpi_get_vlog_info(&vinfo)) @@ -142,6 +181,8 @@ extern "C" void cospike_cosim(long long int cycle, in_permissive = false; } else if (arg == "+cospike_debug" || arg == "+cospike-debug") { cospike_debug = true; + } else if (arg.find("+cospike-timeout=") == 0) { + cospike_timeout = strtoull(arg.substr(17).c_str(), 0, 10); } else if (!in_permissive) { htif_args.push_back(arg); } @@ -159,17 +200,19 @@ extern "C" void cospike_cosim(long long int cycle, .support_impebreak = true }; - printf("isa string is %s\n", info->isa.c_str()); + printf("isa string: %s\n", info->isa.c_str()); + printf("htif args: "); for (int i = 0; i < htif_args.size(); i++) { - printf("%s\n", htif_args[i].c_str()); + printf("%s", htif_args[i].c_str()); } + printf("\n"); sim = new sim_t(cfg, false, mems, plugin_devices, htif_args, dm_config, - "cospike.log", + nullptr, false, nullptr, false, @@ -193,11 +236,19 @@ extern "C" void cospike_cosim(long long int cycle, #endif sim->configure_log(true, true); - // Use our own reset vector for (int i = 0; i < info->nharts; i++) { + // Use our own reset vector sim->get_core(hartid)->get_state()->pc = 0x10040; + // Set MMU to support up to sv39, as our normal hw configs do + sim->get_core(hartid)->set_impl(IMPL_MMU_SV48, false); + sim->get_core(hartid)->set_impl(IMPL_MMU_SV57, false); + + // HACKS: Our processor's don't implement zicntr fully, they don't provide time + sim->get_core(hartid)->get_state()->csrmap.erase(CSR_TIME); } sim->set_debug(cospike_debug); + sim->set_histogram(true); + sim->set_procs_debug(cospike_debug); printf("Setting up htif for spike cosim\n"); ((htif_t*)sim)->start(); printf("Spike cosim started\n"); @@ -205,14 +256,25 @@ extern "C" void cospike_cosim(long long int cycle, fromhost_addr = ((htif_t*)sim)->get_fromhost_addr(); printf("Tohost : %lx\n", tohost_addr); printf("Fromhost: %lx\n", fromhost_addr); - printf("Memory base : %lx\n", info->mem0_base); - printf("Memory Size : %lx\n", info->mem0_size); + printf("BootROM base : %lx\n", default_boot_rom_addr); + printf("BootROM size : %lx\n", boot_rom->contents().size()); + printf("Memory base : %lx\n", info->mem0_base); + printf("Memory size : %lx\n", info->mem0_size); } if (priv & 0x4) { // debug return; } + if (cospike_timeout && cycle > cospike_timeout) { + if (sim) { + printf("Cospike reached timeout cycles = %ld, terminating\n", cospike_timeout); + delete sim; + } + exit(0); + } + + processor_t* p = sim->get_core(hartid); state_t* s = p->get_state(); #ifdef COSPIKE_DTM @@ -269,14 +331,18 @@ extern "C" void cospike_cosim(long long int cycle, uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; bool ssip_interrupt = interrupt_cause == 0x1; bool msip_interrupt = interrupt_cause == 0x3; + bool stip_interrupt = interrupt_cause == 0x5; + bool mtip_interrupt = interrupt_cause == 0x7; bool debug_interrupt = interrupt_cause == 0xe; if (raise_interrupt) { printf("%d interrupt %lx\n", cycle, cause); - if (ssip_interrupt) { + if (ssip_interrupt || stip_interrupt) { // do nothing } else if (msip_interrupt) { s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP); + } else if (mtip_interrupt) { + s->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP); } else if (debug_interrupt) { return; } else { @@ -295,6 +361,8 @@ extern "C" void cospike_cosim(long long int cycle, printf("\n"); } if (valid || raise_interrupt || raise_exception) { + p->clear_waiting_for_interrupt(); + for (auto& e : read_override_devices) e->was_read_from = false; p->step(1); if (unlikely(cospike_debug)) { printf("spike pc is %lx\n", s->pc); @@ -328,10 +396,8 @@ extern "C" void cospike_cosim(long long int cycle, if ((waddr == CLINT_BASE + 4*hartid) && w_data == 0) { s->mip->backdoor_write_with_mask(MIP_MSIP, 0); } - // Try to remember magic_mem addrs, and ignore these in the future - if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { - printf("Probable magic mem %lx\n", w_data); - magic_addrs.insert(w_data); + if ((waddr == CLINT_BASE + 0x4000 + 4*hartid)) { + s->mip->backdoor_write_with_mask(MIP_MTIP, 0); } // Try to remember magic_mem addrs, and ignore these in the future if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { @@ -357,13 +423,18 @@ extern "C" void cospike_cosim(long long int cycle, // 2 => vec // 3 => vec hint // 4 => csr + bool device_read = false; + for (auto& e : read_override_devices) if (e->was_read_from) device_read = true; - bool ignore_read = (!mem_read.empty() && - ((magic_addrs.count(mem_read_addr) || + bool lr_read = ((insn & MASK_LR_D) == MATCH_LR_D) || ((insn & MASK_LR_W) == MATCH_LR_W); + bool sc_read = ((insn & MASK_SC_D) == MATCH_SC_D) || ((insn & MASK_SC_W) == MATCH_SC_W); + + bool ignore_read = sc_read || (!mem_read.empty() && + (magic_addrs.count(mem_read_addr) || + device_read || + lr_read || (tohost_addr && mem_read_addr == tohost_addr) || - (fromhost_addr && mem_read_addr == fromhost_addr) || - (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE))))); - + (fromhost_addr && mem_read_addr == fromhost_addr))); // check the type is compliant with writeback first if ((type == 0 || type == 1)) scalar_wb = true; @@ -379,11 +450,16 @@ extern "C" void cospike_cosim(long long int cycle, bool csr_read = (insn & 0x7f) == 0x73; if (csr_read) printf("CSR read %lx\n", csr_addr); - if (csr_read && ((csr_addr == 0xf13) || // mimpid + if (csr_read && ((csr_addr == 0x301) || // misa + (csr_addr == 0x306) || // mcounteren + (csr_addr == 0xf13) || // mimpid (csr_addr == 0xf12) || // marchid (csr_addr == 0xf11) || // mvendorid (csr_addr == 0xb00) || // mcycle (csr_addr == 0xb02) || // minstret + (csr_addr == 0xc00) || // cycle + (csr_addr == 0xc01) || // time + (csr_addr == 0xc02) || // instret (csr_addr >= 0x7a0 && csr_addr <= 0x7aa) || // debug trigger registers (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr )) { @@ -394,7 +470,7 @@ extern "C" void cospike_cosim(long long int cycle, // from clint Technically this could be buggy because log_mem_read // only reports vaddrs, but no software ever should access // tohost/fromhost/clint with vaddrs anyways - printf("Read override %lx\n", mem_read_addr); + printf("Read override %lx = %lx\n", mem_read_addr, wdata); s->XPR.write(rd, wdata); } else if (wdata != regwrite.second.v[0]) { printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, From 471f8879d799b9528ca0e02c4ba0c5861b5ea925 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 8 Apr 2023 16:38:36 -0700 Subject: [PATCH 09/27] Support banked/partitioned scratchpads --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 12 +++++++++--- generators/testchipip | 2 +- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 6711eac7..561af0d7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -16,7 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHaveTraceIO // Enables optionally adding trace IO - with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 21b630cc..a68ba55d 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -74,13 +74,19 @@ class L1ScratchpadRocketConfig extends Config( new chipyard.config.AbstractConfig) // DOC include start: mbusscratchpadrocket -class MbusScratchpadRocketConfig extends Config( - new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port +class MbusScratchpadOnlyRocketConfig extends Config( + new testchipip.WithMbusScratchpad(stripes=2, partitions=2) ++ // add 4 banks mbus backing scratchpad + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: mbusscratchpadrocket +class SbusScratchpadRocketConfig extends Config( + new testchipip.WithSbusScratchpad(base=0x70000000L, stripes=2, partitions=2) ++ // add 4 lanes sbus backing scratchpad + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + + class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/testchipip b/generators/testchipip index a3e9c1ff..8a1540ce 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit a3e9c1ffeae8af573831e4ac5fd00a76df0ca7f1 +Subproject commit 8a1540ce90405433ac377de5a6d331d34ff108df From 1e3d4aad460051c4fc030d10307097ea84766d33 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 10 Apr 2023 15:31:29 -0700 Subject: [PATCH 10/27] Update WithBackingScratchpad for firechip --- .../chipyard/src/main/scala/config/RocketConfigs.scala | 4 ++-- generators/firechip/src/main/scala/TargetConfigs.scala | 6 +++--- generators/testchipip | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index a68ba55d..a0fab881 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -75,14 +75,14 @@ class L1ScratchpadRocketConfig extends Config( // DOC include start: mbusscratchpadrocket class MbusScratchpadOnlyRocketConfig extends Config( - new testchipip.WithMbusScratchpad(stripes=2, partitions=2) ++ // add 4 banks mbus backing scratchpad + new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: mbusscratchpadrocket class SbusScratchpadRocketConfig extends Config( - new testchipip.WithSbusScratchpad(base=0x70000000L, stripes=2, partitions=2) ++ // add 4 lanes sbus backing scratchpad + new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus backing scratchpad new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index c27abd50..1c821294 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -138,7 +138,7 @@ class WithFireSimConfigTweaks extends Config( class WithMinimalFireSimHighPerfConfigTweaks extends Config( new WithFireSimHighPerfClocking ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ - new testchipip.WithBackingScratchpad ++ + new testchipip.WithMbusScratchpad ++ new WithMinimalFireSimDesignTweaks ) @@ -148,7 +148,7 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config( class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config( new WithFireSimHighPerfClocking ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against - new testchipip.WithBackingScratchpad ++ // adds backing scratchpad for memory to replace FASED model + new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model new testchipip.WithBlockDevice(true) ++ // add in block device new WithMinimalFireSimDesignTweaks ) @@ -329,7 +329,7 @@ class FireSim16LargeBoomConfig extends Config( class FireSimNoMemPortConfig extends Config( new WithDefaultFireSimBridges ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ - new testchipip.WithBackingScratchpad ++ + new testchipip.WithMbusScratchpad ++ new WithFireSimConfigTweaks ++ new chipyard.RocketConfig) diff --git a/generators/testchipip b/generators/testchipip index 8a1540ce..35d7e196 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8a1540ce90405433ac377de5a6d331d34ff108df +Subproject commit 35d7e1969d1d3e54d29a10901737d9b2ba2ab5a3 From a403736e6211bde806987e0f2855249424398040 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 9 Jun 2023 11:24:41 -0700 Subject: [PATCH 11/27] Disable NVDLA simulations in CI --- .github/scripts/defaults.sh | 2 +- .github/workflows/chipyard-run-tests.yml | 47 ++++++++++++------------ 2 files changed, 24 insertions(+), 25 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 1c1b7def..8d9e30c6 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -44,7 +44,7 @@ mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" -mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" +mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig" mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig" diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 02de6935..05fc617e 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -741,28 +741,28 @@ jobs: group-key: "group-accels" project-key: "chipyard-manymmioaccels" - chipyard-nvdla-run-tests: - name: chipyard-nvdla-run-tests - needs: prepare-chipyard-accels - runs-on: self-hosted - steps: - - name: Delete old checkout - run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . - - name: Checkout - uses: actions/checkout@v3 - - name: Git workaround - uses: ./.github/actions/git-workaround - - name: Create conda env - uses: ./.github/actions/create-conda-env - - name: Run tests - uses: ./.github/actions/run-tests - with: - group-key: "group-accels" - project-key: "chipyard-nvdla" + # chipyard-nvdla-run-tests: + # name: chipyard-nvdla-run-tests + # needs: prepare-chipyard-accels + # runs-on: self-hosted + # steps: + # - name: Delete old checkout + # run: | + # ls -alh . + # rm -rf ${{ github.workspace }}/* || true + # rm -rf ${{ github.workspace }}/.* || true + # ls -alh . + # - name: Checkout + # uses: actions/checkout@v3 + # - name: Git workaround + # uses: ./.github/actions/git-workaround + # - name: Create conda env + # uses: ./.github/actions/create-conda-env + # - name: Run tests + # uses: ./.github/actions/run-tests + # with: + # group-key: "group-accels" + # project-key: "chipyard-nvdla" chipyard-mempress-run-tests: name: chipyard-mempress-run-tests @@ -1035,8 +1035,7 @@ jobs: chipyard-manyperipherals-run-tests, chipyard-sha3-run-tests, chipyard-gemmini-run-tests, - chipyard-manymmioaccels-run-tests, - chipyard-nvdla-run-tests, + chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-mempress-run-tests, chipyard-constellation-run-tests, tracegen-boom-run-tests, From 486176999ef6711eca2cc08103c713196f1fed90 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 10 Jun 2023 22:32:03 -0700 Subject: [PATCH 12/27] Update NoC example config to match new PRCI organization --- generators/chipyard/src/main/scala/config/NoCConfigs.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 0036e988..0b6be558 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -68,9 +68,9 @@ class MultiNoCConfig extends Config( "serial-tl" -> 0), outNodeMapping = ListMap( "error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4, - "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "tileClockGater" -> 8, "tileResetSetter" -> 9)), + "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)), NoCParams( - topology = TerminalRouter(BidirectionalLine(10)), + topology = TerminalRouter(BidirectionalLine(9)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }), routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1)) )) ++ From 7995f1de643c94b0204a57c1229ca14b3cd32497 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 12 Jun 2023 10:10:37 -0700 Subject: [PATCH 13/27] Add doc page on shuttle core --- docs/Generators/Shuttle.rst | 8 ++++++++ docs/Generators/index.rst | 1 + 2 files changed, 9 insertions(+) create mode 100644 docs/Generators/Shuttle.rst diff --git a/docs/Generators/Shuttle.rst b/docs/Generators/Shuttle.rst new file mode 100644 index 00000000..87c8f78b --- /dev/null +++ b/docs/Generators/Shuttle.rst @@ -0,0 +1,8 @@ +Shuttle RISC-V Core +=================== + +Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base RV64IMAFDC instruction set with supervisor and user-mode. Shuttle is a 6-stage core that can be configured to be dual, three, or quad-issue, although dual-issue is the most sensible design point. Shuttle is not designed to meet any power, performance, or area targets. It exists purely as a demonstrative example of another RISC-V CPU design point. + +The superscalar microarchitecture presents the most advantages for 1) floating-point kernels and 2) RoCC accelerator kernels, as scalar control code can execute concurrently with floating point or RoCC instructions, maintaining high utilization of those units. + +Shuttle is tape-out proven, and has similar physical design complexity as Rocket. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index cb8cdc47..245314c9 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -33,4 +33,5 @@ so changes to the generators themselves will automatically be used when building fft NVDLA Sodor + Shuttle Mempress From 22889212db915e77a7b3ad3ba766b45d900b6e1a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 13:40:55 -0700 Subject: [PATCH 14/27] Add barf submodule --- .gitmodules | 3 +++ generators/bar-fetchers | 1 + 2 files changed, 4 insertions(+) create mode 160000 generators/bar-fetchers diff --git a/.gitmodules b/.gitmodules index 5a3eb6fc..2a4bbac3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -124,3 +124,6 @@ [submodule "software/embench/embench-iot"] path = software/embench/embench-iot url = https://github.com/embench/embench-iot.git +[submodule "generators/bar-fetchers"] + path = generators/bar-fetchers + url = https://github.com/ucb-bar/bar-fetchers.git diff --git a/generators/bar-fetchers b/generators/bar-fetchers new file mode 160000 index 00000000..e1a16ff9 --- /dev/null +++ b/generators/bar-fetchers @@ -0,0 +1 @@ +Subproject commit e1a16ff9834aafe805ec4a113b7dd5ce7ddd905b From 5e893ea77c3a6698b700d8e38d5eecf3d309d878 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:16:38 -0700 Subject: [PATCH 15/27] Add prefetching rocket example config --- build.sbt | 7 ++++++- .../src/main/scala/config/RocketConfigs.scala | 8 ++++++++ .../scala/config/fragments/TileFragments.scala | 17 +++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 6f72940a..0fbdd747 100644 --- a/build.sbt +++ b/build.sbt @@ -153,7 +153,7 @@ lazy val chipyard = (project in file("generators/chipyard")) sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, barf) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -168,6 +168,11 @@ lazy val mempress = (project in file("generators/mempress")) .settings(chiselTestSettings) .settings(commonSettings) +lazy val barf = (project in file("generators/bar-fetchers")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val constellation = (project in file("generators/constellation")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 21b630cc..f71b6ea7 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -126,3 +126,11 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.example.WithCustomIOCells ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) + +class PrefetchingRocketConfig extends Config( + new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher into L1D$ + new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher into L2 for L1I$ accesses + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher into L2 for L1D$ accesses + new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 56042c3d..17eaa3f0 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -9,7 +9,10 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import boom.common.{BoomTileAttachParams} import cva6.{CVA6TileAttachParams} +import sodor.common.{SodorTileAttachParams} +import ibex.{IbexTileAttachParams} import testchipip._ +import barf.{TilePrefetchingMasterPortParams} class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { @@ -79,3 +82,17 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) +class WithTilePrefetchers extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + } +}) From 7cbabaa18abbf65811b9a650a5f0dc904f8a4e76 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:21:26 -0700 Subject: [PATCH 16/27] Add CI on PrefetchingRocketConfig --- .github/scripts/check-commit.sh | 2 +- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 3 +++ .github/workflows/chipyard-run-tests.yml | 24 ++++++++++++++++++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index fe1de2bf..031c9c0a 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 8d9e30c6..dbcc1528 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -28,7 +28,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" +grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla" grouping["group-constellation"]="chipyard-constellation" @@ -42,6 +42,7 @@ mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" +mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 4a5a0802..a878eb36 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -56,6 +56,9 @@ case $1 in chipyard-hetero) run_bmark ${mapping[$1]} ;; + chipyard-prefetchers) + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv + ;; rocketchip) run_bmark ${mapping[$1]} ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 05fc617e..fdcbd51e 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -442,6 +442,29 @@ jobs: group-key: "group-cores" project-key: "chipyard-rocket" + chipyard-prefetchers-run-tests: + name: chipyard-prefetchers-run-tests + needs: prepare-chipyard-cores + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-cores" + project-key: "chipyard-prefetchers" + chipyard-hetero-run-tests: name: chipyard-hetero-run-tests needs: prepare-chipyard-cores @@ -1036,6 +1059,7 @@ jobs: chipyard-sha3-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, + chipyard-prefetchers-run-tests, chipyard-mempress-run-tests, chipyard-constellation-run-tests, tracegen-boom-run-tests, From 903971f32ff2eff3f5e9a83920b0bd1001ec5d66 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:24:34 -0700 Subject: [PATCH 17/27] Add documentation page indicating existence of prefetchers --- docs/Generators/Prefetchers.rst | 9 +++++++++ docs/Generators/index.rst | 1 + .../chipyard/src/main/scala/config/RocketConfigs.scala | 6 +++--- scripts/tutorial-patches/build.sbt.patch | 2 +- 4 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 docs/Generators/Prefetchers.rst diff --git a/docs/Generators/Prefetchers.rst b/docs/Generators/Prefetchers.rst new file mode 100644 index 00000000..550d22e7 --- /dev/null +++ b/docs/Generators/Prefetchers.rst @@ -0,0 +1,9 @@ +Prefetchers +==================================== + +The BAR-fetchers library is a collection of Chisel-implemented prefetchers, designed for compatibility with Chipyard and Rocket-Chip SoCs. +This package implements a generic prefetcher API, and example implementations of NextLine, Strided, and AMPM prefetchers. + +Prefetchers can be instantiated in front of a L1D HellaCache, or as TileLink nodes in front of some TileLink bus. + +An example configuration using prefetchers is found in the ``PrefetchingRocketConfig`` diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index cb8cdc47..b8f5df1b 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -34,3 +34,4 @@ so changes to the generators themselves will automatically be used when building NVDLA Sodor Mempress + Prefetchers diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f71b6ea7..1c3884bc 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -128,9 +128,9 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.config.AbstractConfig) class PrefetchingRocketConfig extends Config( - new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher into L1D$ - new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher into L2 for L1I$ accesses - new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher into L2 for L1D$ accesses + new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$ + new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2 + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2 new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index db81b052..dee7fcf5 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -10,7 +10,7 @@ index ec36a85f..c0c2849a 100644 +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, barf) @@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) From 7b05dd199d3e6ebdfacf4163d0823a1eea019e0b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 12 Jun 2023 16:26:00 -0700 Subject: [PATCH 18/27] Prefetching config should use non-blocking L1D$ --- generators/bar-fetchers | 2 +- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/bar-fetchers b/generators/bar-fetchers index e1a16ff9..3a33d818 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit e1a16ff9834aafe805ec4a113b7dd5ce7ddd905b +Subproject commit 3a33d818aefe5444aa27fc1557008f747538d2cc diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 1c3884bc..95c2cbae 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -130,7 +130,8 @@ class CustomIOChipTopRocketConfig extends Config( class PrefetchingRocketConfig extends Config( new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$ new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2 - new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2 + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2 new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus + new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) From e4eaa5035458fbaf08de037d9382945b7c1f3aba Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Jun 2023 00:57:56 -0700 Subject: [PATCH 19/27] docs: Fix comment on rocc tag bits --- docs/Customization/RoCC-Accelerators.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/Customization/RoCC-Accelerators.rst b/docs/Customization/RoCC-Accelerators.rst index a2d98589..ad3bfa54 100644 --- a/docs/Customization/RoCC-Accelerators.rst +++ b/docs/Customization/RoCC-Accelerators.rst @@ -88,7 +88,8 @@ In your ``LazyRoCCModuleImp``, the signal ``io.mem`` is a ``HellaCacheIO``, whic At a high level, you must tag requests that you send across this interface using the ``io.mem.req.tag``, and the tag will be returned to you when the data is ready. Responses may come back out of order if you issue multiple requests, so you can use these tags to tell what data came back. -Note that the top two bits of the tag are reserved, and MUST be set to zero, or the interface will exhibit undefined behavior. +Note that the number of tag bits is controled by ``dcacheReqTagBits``, which is usually set to 6. +Using more than 6 bits will cause errors or hangs. Adding RoCC accelerator to Config From 309bfde21e98b12e6ca5d07cdec6c0dc6082829d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Jun 2023 15:27:59 -0700 Subject: [PATCH 20/27] [ci skip] add more comments to ShuttleConfigs --- .../src/main/scala/config/ShuttleConfigs.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala index 6e86e020..10220bdb 100644 --- a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala @@ -7,13 +7,13 @@ import org.chipsalliance.cde.config.{Config} //----------------- class ShuttleConfig extends Config( - new shuttle.common.WithNShuttleCores ++ + new shuttle.common.WithNShuttleCores ++ // 1x dual-issue shuttle core new chipyard.config.AbstractConfig) class ShuttleCosimConfig extends Config( new chipyard.harness.WithCospike ++ // attach spike-cosim - new chipyard.config.WithTraceIO ++ - new shuttle.common.WithShuttleDebugROB ++ + new chipyard.config.WithTraceIO ++ // enable trace-io for cosim + new shuttle.common.WithShuttleDebugROB ++ // enable shuttle debug ROB for cosim new shuttle.common.WithNShuttleCores ++ new chipyard.config.AbstractConfig) @@ -21,8 +21,8 @@ class dmiShuttleCosimConfig extends Config( new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl new chipyard.harness.WithCospike ++ // attach spike-cosim new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port - new chipyard.config.WithTraceIO ++ - new shuttle.common.WithShuttleDebugROB ++ + new chipyard.config.WithTraceIO ++ // enable traceio for cosim + new shuttle.common.WithShuttleDebugROB ++ // enable shuttle debug ROB for cosim new shuttle.common.WithNShuttleCores ++ new chipyard.config.AbstractConfig) From 40833f559dc94367265290787f91e085af5f770a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Jun 2023 16:34:03 -0700 Subject: [PATCH 21/27] Bump constellation to fix interconnect FIFO-fixers Constellation NoCs by-default do not preserve FIFO-ness. This bump makes the NoCs correctly report the lack of FIFO-ness, so the NoC buswrapper will correctly insert FIFOFixers to domains that should be FIFO --- generators/constellation | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/constellation b/generators/constellation index e9f1c828..8184e0e7 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit e9f1c828ca5adb4fa46a242cd1798391fc9e6f62 +Subproject commit 8184e0e7e32ff11dce344c449158aa7551e164e0 From 4e5bb9c781e4c23d346337ee82b7b1ec6106c8ce Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 18:19:01 -0700 Subject: [PATCH 22/27] ADD: add ignore rule to vscode files --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index ac8e84d0..5dd75bec 100644 --- a/.gitignore +++ b/.gitignore @@ -27,3 +27,4 @@ project/project/ .ivy2 .sbt .classpath_cache/ +.vscode/ From 485dbcc4820e8cb7a7c0285cc7d653f809a28b15 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 18:19:34 -0700 Subject: [PATCH 23/27] ADD: add support for multiple peripherals of same kind --- .../fragments/PeripheralFragments.scala | 56 ++++++++++++++----- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 3b607ae0..3c9cc670 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -6,7 +6,8 @@ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey} -import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} +import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} @@ -14,6 +15,7 @@ import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ import testchipip._ @@ -22,41 +24,65 @@ import chipyard.{ExtTLMem} // Set the bootrom to the Chipyard bootrom class WithBootROM extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) - .map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) + .map(_.copy( + address = 0x10000, + size = 0x10000, + hang = 0x10040, + contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" + )) }) // DOC include start: gpio config fragment -class WithGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Seq( - GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) +class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((site, here, up) => { + case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( + GPIOParams(address = address, width = width, includeIOF = false)) }) // DOC include end: gpio config fragment -class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { - case PeripheryUARTKey => Seq( - UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) -}) - class WithNoUART extends Config((site, here, up) => { case PeripheryUARTKey => Nil }) +class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => { + case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( + UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) +}) + class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) -class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { +class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below - case PeripherySPIFlashKey => Seq( - SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) + case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( + SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) +}) + +class WithSPI(address: BigInt = 0x10031000) extends Config((site, here, up) => { + case PeripherySPIKey => up(PeripherySPIKey) ++ Seq( + SPIParams(rAddress = address)) +}) + +class WithI2C(address: BigInt = 0x10040000) extends Config((site, here, up) => { + case PeripheryI2CKey => up(PeripheryI2CKey) ++ Seq( + I2CParams(address = address, controlXType = AsynchronousCrossing(), intXType = AsynchronousCrossing()) + ) +}) + +class WithNoDebug extends Config((site, here, up) => { + case DebugModuleKey => None }) class WithDMIDTM extends Config((site, here, up) => { case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) }) -class WithNoDebug extends Config((site, here, up) => { - case DebugModuleKey => None +class WithJTAGDTMKey(idcodeVersion: Int = 2, partNum: Int = 0x000, manufId: Int = 0x489, debugIdleCycles: Int = 5) extends Config((site, here, up) => { + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = idcodeVersion, + idcodePartNum = partNum, + idcodeManufId = manufId, + debugIdleCycles = debugIdleCycles) }) class WithTLBackingMemory extends Config((site, here, up) => { From c478d056e7532e00190b6eff49029749cac360ba Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 18:40:14 -0700 Subject: [PATCH 24/27] ADD: add documentation --- .../fragments/PeripheralFragments.scala | 61 ++++++++++++++++--- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 3c9cc670..6cfb49ce 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -21,28 +21,48 @@ import testchipip._ import chipyard.{ExtTLMem} -// Set the bootrom to the Chipyard bootrom -class WithBootROM extends Config((site, here, up) => { +/** + * Config fragment for adding a BootROM to the SoC + * + * @param address the address of the BootROM device + * @param size the size of the BootROM + * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset + * @param contentFileName the path to the BootROM image + */ +class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040, contentFileName: String = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img") extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) .map(_.copy( - address = 0x10000, - size = 0x10000, - hang = 0x10040, - contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" + address = address, + size = size, + hang = hand, + contentFileName = contentFileName )) }) -// DOC include start: gpio config fragment +/** + * Config fragment for adding a GPIO peripheral device to the SoC + * + * @param address the address of the GPIO device + * @param width the number of pins of the GPIO device + */ class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((site, here, up) => { case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( GPIOParams(address = address, width = width, includeIOF = false)) }) -// DOC include end: gpio config fragment +/** + * Config fragment for removing all UART peripheral devices from the SoC + */ class WithNoUART extends Config((site, here, up) => { case PeripheryUARTKey => Nil }) +/** + * Config fragment for adding a UART peripheral device to the SoC + * + * @param address the address of the UART device + * @param baudrate the baudrate of the UART device + */ class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) @@ -52,17 +72,34 @@ class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) +/** + * Config fragment for adding a SPI peripheral device with Execute-in-Place capability to the SoC + * + * @param address the address of the SPI controller + * @param fAddress the address of the Execute-in-Place (XIP) region of the SPI flash memory + * @param size the size of the Execute-in-Place (XIP) region of the SPI flash memory + */ class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) }) +/** + * Config fragment for adding a SPI peripheral device to the SoC + * + * @param address the address of the SPI controller + */ class WithSPI(address: BigInt = 0x10031000) extends Config((site, here, up) => { case PeripherySPIKey => up(PeripherySPIKey) ++ Seq( SPIParams(rAddress = address)) }) +/** + * Config fragment for adding a I2C peripheral device to the SoC + * + * @param address the address of the I2C controller + */ class WithI2C(address: BigInt = 0x10040000) extends Config((site, here, up) => { case PeripheryI2CKey => up(PeripheryI2CKey) ++ Seq( I2CParams(address = address, controlXType = AsynchronousCrossing(), intXType = AsynchronousCrossing()) @@ -77,6 +114,14 @@ class WithDMIDTM extends Config((site, here, up) => { case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) }) +/** + * Config fragment for adding a JTAG Debug Module to the SoC + * + * @param idcodeVersion the version of the JTAG protocol the Debug Module supports + * @param partNum the part number of the Debug Module + * @param manufId the 11-bit JEDEC Designer ID of the chip manufacturer + * @param debugIdleCycles the number of cycles the Debug Module waits before responding to a request + */ class WithJTAGDTMKey(idcodeVersion: Int = 2, partNum: Int = 0x000, manufId: Int = 0x489, debugIdleCycles: Int = 5) extends Config((site, here, up) => { case JtagDTMKey => new JtagDTMConfig ( idcodeVersion = idcodeVersion, From 8ddd8f6184b479719e5d0987da7397539cd27f06 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 19:13:19 -0700 Subject: [PATCH 25/27] FIX: fix typo --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 6cfb49ce..27f52c4d 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -34,7 +34,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = .map(_.copy( address = address, size = size, - hang = hand, + hang = hang, contentFileName = contentFileName )) }) From 62825df3b9e6bc60f905becbacd2cf606b1e7283 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 19:14:15 -0700 Subject: [PATCH 26/27] FIX: fix typo --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 27f52c4d..290e3dfe 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -29,13 +29,13 @@ import chipyard.{ExtTLMem} * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset * @param contentFileName the path to the BootROM image */ -class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040, contentFileName: String = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img") extends Config((site, here, up) => { +class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) .map(_.copy( address = address, size = size, hang = hang, - contentFileName = contentFileName + contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" )) }) From 8e39fe1fa1d8ae69e8b6be850220ac0c8472c15b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 14 Jun 2023 18:37:37 -0700 Subject: [PATCH 27/27] [ci skip] Fix broken docs link --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 290e3dfe..09636c49 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -39,6 +39,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = )) }) +// DOC include start: gpio config fragment /** * Config fragment for adding a GPIO peripheral device to the SoC * @@ -49,6 +50,7 @@ class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((si case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( GPIOParams(address = address, width = width, includeIOF = false)) }) +// DOC include end: gpio config fragment /** * Config fragment for removing all UART peripheral devices from the SoC