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Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

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This commit is contained in:
Jerry Zhao
2023-01-04 01:46:45 -08:00
parent 749f84418e
commit 7780ed23bf
33 changed files with 86 additions and 70 deletions
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2
.github/scripts/remote-run-firesim-scala-tests.sh vendored
View File

@@ -16,4 +16,4 @@ cd $REMOTE_CHIPYARD_DIR
# Run Firesim Scala Tests # Run Firesim Scala Tests
export FIRESIM_ENV_SOURCED=1; export FIRESIM_ENV_SOURCED=1;
export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
make -C $REMOTE_FIRESIM_DIR JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" testOnly ${mapping[$1]} make -C $REMOTE_FIRESIM_DIR JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]}

25
build.sbt
View File

@@ -7,13 +7,12 @@ lazy val chipyardRoot = Project("chipyardRoot", file("."))
lazy val commonSettings = Seq( lazy val commonSettings = Seq(
organization := "edu.berkeley.cs", organization := "edu.berkeley.cs",
version := "1.6", version := "1.6",
scalaVersion := "2.12.10", scalaVersion := "2.13.10",
assembly / test := {}, assembly / test := {},
assembly / assemblyMergeStrategy := { _ match { assembly / assemblyMergeStrategy := { _ match {
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
case _ => MergeStrategy.first}}, case _ => MergeStrategy.first}},
scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), scalacOptions ++= Seq("-deprecation","-unchecked"),
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full),
unmanagedBase := (chipyardRoot / unmanagedBase).value, unmanagedBase := (chipyardRoot / unmanagedBase).value,
allDependencies := { allDependencies := {
// drop specific maven dependencies in subprojects in favor of Chipyard's version // drop specific maven dependencies in subprojects in favor of Chipyard's version
@@ -60,7 +59,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
new Group(test.name, Seq(test), SubProcess(options)) new Group(test.name, Seq(test), SubProcess(options))
} toSeq } toSeq
val chiselVersion = "3.5.2" val chiselVersion = "3.5.5"
lazy val chiselSettings = Seq( lazy val chiselSettings = Seq(
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion, libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
@@ -68,9 +67,6 @@ lazy val chiselSettings = Seq(
"org.apache.commons" % "commons-text" % "1.9"), "org.apache.commons" % "commons-text" % "1.9"),
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full))
val firrtlVersion = "1.5.1"
lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion))
val chiselTestVersion = "2.5.1" val chiselTestVersion = "2.5.1"
@@ -88,7 +84,7 @@ lazy val hardfloat = (project in rocketChipDir / "hardfloat")
.settings( .settings(
libraryDependencies ++= Seq( libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value, "org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.1", "org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test" "org.scalatest" %% "scalatest" % "3.2.0" % "test"
) )
) )
@@ -98,7 +94,7 @@ lazy val rocketMacros = (project in rocketChipDir / "macros")
.settings( .settings(
libraryDependencies ++= Seq( libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value, "org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.1", "org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test" "org.scalatest" %% "scalatest" % "3.2.0" % "test"
) )
) )
@@ -108,7 +104,7 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu
.settings( .settings(
libraryDependencies ++= Seq( libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value, "org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.1", "org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test" "org.scalatest" %% "scalatest" % "3.2.0" % "test"
) )
) )
@@ -120,15 +116,14 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
.settings( .settings(
libraryDependencies ++= Seq( libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value, "org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.1", "org.json4s" %% "json4s-jackson" % "3.6.6",
"org.apache.commons" % "commons-lang3" % "3.12.0",
"org.scalatest" %% "scalatest" % "3.2.0" % "test" "org.scalatest" %% "scalatest" % "3.2.0" % "test"
) )
) )
.settings( // Settings for scalafix .settings( // Settings for scalafix
semanticdbEnabled := true, semanticdbEnabled := true,
semanticdbVersion := scalafixSemanticdb.revision, semanticdbVersion := scalafixSemanticdb.revision,
scalacOptions += "-Ywarn-unused-import" scalacOptions += "-Ywarn-unused"
) )
lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
@@ -185,7 +180,7 @@ lazy val hwacha = (project in file("generators/hwacha"))
.settings(commonSettings) .settings(commonSettings)
lazy val boom = (project in file("generators/boom")) lazy val boom = (project in file("generators/boom"))
.dependsOn(testchipip, rocketchip) .dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value) .settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings) .settings(commonSettings)
@@ -242,7 +237,7 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
commonSettings, commonSettings,
libraryDependencies ++= Seq( libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.2.+" % "test", "org.scalatest" %% "scalatest" % "3.2.+" % "test",
"org.typelevel" %% "spire" % "0.16.2", "org.typelevel" %% "spire" % "0.17.0",
"org.scalanlp" %% "breeze" % "1.1", "org.scalanlp" %% "breeze" % "1.1",
"junit" % "junit" % "4.13" % "test", "junit" % "junit" % "4.13" % "test",
"org.scalacheck" %% "scalacheck" % "1.14.3" % "test", "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",

2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: f1187f21a0...6a496d7463

2
generators/boom

Submodule generators/boom updated: 9e4269088e...0a887434ab

14
generators/chipyard/src/main/scala/HarnessBinders.scala
View File

@@ -234,7 +234,14 @@ class WithTieOffInterrupts extends OverrideHarnessBinder({
class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ class WithTieOffL2FBusAXI extends OverrideHarnessBinder({
(system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {
ports.foreach({ p => p := DontCare; p.bits.tieoff() }) ports.foreach({ p =>
p.bits := DontCare
p.bits.aw.valid := false.B
p.bits.w.valid := false.B
p.bits.b.ready := false.B
p.bits.ar.valid := false.B
p.bits.r.ready := false.B
})
} }
}) })
@@ -274,7 +281,10 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
d.dmiClock := false.B.asClock d.dmiClock := false.B.asClock
d.dmiReset := true.B d.dmiReset := true.B
case a: ClockedAPBBundle => case a: ClockedAPBBundle =>
a.tieoff() a.pready := false.B
a.pslverr := false.B
a.prdata := 0.U
a.pduser := DontCare
a.clock := false.B.asClock a.clock := false.B.asClock
a.reset := true.B.asAsyncReset a.reset := true.B.asAsyncReset
a.psel := false.B a.psel := false.B

6
generators/chipyard/src/main/scala/IOBinders.scala
View File

@@ -287,7 +287,7 @@ class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
p.clock := clockBundle.clock p.clock := clockBundle.clock
p.reset := clockBundle.reset p.reset := clockBundle.reset
p p
}) }).toSeq
(ports, Nil) (ports, Nil)
} }
} }
@@ -307,7 +307,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
p.clock := clockBundle.clock p.clock := clockBundle.clock
p.reset := clockBundle.reset p.reset := clockBundle.reset
p p
}) }).toSeq
(ports, Nil) (ports, Nil)
} }
} }
@@ -326,7 +326,7 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
m <> p.bits m <> p.bits
p.clock := clockBundle.clock p.clock := clockBundle.clock
p p
}) }).toSeq
(ports, Nil) (ports, Nil)
} }
} }

4
generators/chipyard/src/main/scala/TestSuites.scala
View File

@@ -74,11 +74,15 @@ class TestSuiteHelper
addSuites(env.map(rv32uf)) addSuites(env.map(rv32uf))
if (cfg.fLen >= 64) if (cfg.fLen >= 64)
addSuites(env.map(rv32ud)) addSuites(env.map(rv32ud))
if (cfg.minFLen <= 16)
addSuites(env.map(rv32uzfh))
} else { } else {
addSuite(rv32udBenchmarks) addSuite(rv32udBenchmarks)
addSuites(env.map(rv64uf)) addSuites(env.map(rv64uf))
if (cfg.fLen >= 64) if (cfg.fLen >= 64)
addSuites(env.map(rv64ud)) addSuites(env.map(rv64ud))
if (cfg.minFLen <= 16)
addSuites(env.map(rv64uzfh))
} }
} }
if (coreParams.useAtomics) { if (coreParams.useAtomics) {

3
generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
View File

@@ -119,7 +119,8 @@ case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValN
class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {
val node = DividerOnlyClockGeneratorNode(pllName) val node = DividerOnlyClockGeneratorNode(pllName)
lazy val module = new LazyRawModuleImp(this) { lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator") require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator")
val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head
val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head

2
generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
View File

@@ -34,7 +34,7 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
} }
}) })
tlNode.regmap((0 until nTiles).map({ i => tlNode.regmap((0 until nTiles).map({ i =>
i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)), i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
}): _*) }): _*)
val tileMap = tileNames.zipWithIndex.map({ case (n, i) => val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>

4
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -25,7 +25,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
class WithTraceIO extends Config((site, here, up) => { class WithTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true)) core = tp.tileParams.core.copy(trace = true)))
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true)) trace = true))
case other => other case other => other
@@ -36,7 +36,7 @@ class WithTraceIO extends Config((site, here, up) => {
class WithNoTraceIO extends Config((site, here, up) => { class WithNoTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = false)) core = tp.tileParams.core.copy(trace = false)))
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = false)) trace = false))
case other => other case other => other

5
generators/chipyard/src/main/scala/example/TutorialTile.scala
View File

@@ -62,6 +62,11 @@ case class MyCoreParams(
val decodeWidth: Int = 1 // TODO: Check val decodeWidth: Int = 1 // TODO: Check
val fetchWidth: Int = 1 // TODO: Check val fetchWidth: Int = 1 // TODO: Check
val retireWidth: Int = 2 val retireWidth: Int = 2
val useBitManip: Boolean = false
val useBitManipCrypto: Boolean = false
val useCryptoNIST: Boolean = false
val useCryptoSM: Boolean = false
val traceHasWdata: Boolean = false
} }
// DOC include start: CanAttachTile // DOC include start: CanAttachTile

2
generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
View File

@@ -40,7 +40,7 @@ class AddDefaultTests extends Phase with HasRocketChipStageUtils {
// If a custom test suite is set up, use the custom test suite // If a custom test suite is set up, use the custom test suite
annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p)) annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq
} }

2
generators/constellation

Submodule generators/constellation updated: b93fde3e28...55b1899a3b

2
generators/cva6

Submodule generators/cva6 updated: 31fd9cdf80...737fd83b82

2
generators/fft-generator

Submodule generators/fft-generator updated: 40357f00a8...a31bd038dd

6
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -76,7 +76,7 @@ class WithSerialBridge extends OverrideHarnessBinder({
val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) { val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) {
SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
} }
SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool)
} }
Nil Nil
} }
@@ -97,7 +97,7 @@ class WithUARTBridge extends OverrideHarnessBinder({
val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
val pbusClock = pbusClockNode.in.head._1.clock val pbusClock = pbusClockNode.in.head._1.clock
BoringUtils.bore(pbusClock, Seq(uartSyncClock)) BoringUtils.bore(pbusClock, Seq(uartSyncClock))
ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil ports.map { p => UARTBridge(uartSyncClock, p, th.buildtopReset.asBool)(system.p) }; Nil
}) })
class WithBlockDeviceBridge extends OverrideHarnessBinder({ class WithBlockDeviceBridge extends OverrideHarnessBinder({
@@ -134,7 +134,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
axiClockBundle, axiClockBundle,
th.buildtopReset) th.buildtopReset)
} }
SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName)) SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool)
// connect SimAxiMem // connect SimAxiMem
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) => (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) =>

2
generators/gemmini

Submodule generators/gemmini updated: 6f57972db9...49494fcfce

2
generators/hwacha

Submodule generators/hwacha updated: b0795a3aaf...e1be8e2a41

2
generators/ibex

Submodule generators/ibex updated: a5214d0a0a...5a512227d8

2
generators/icenet

Submodule generators/icenet updated: e14c1e8c54...fb23840eab

2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: 510dea7407...9265d02d3c

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 44b0b82492...53adf18d88

2
generators/sha3

Submodule generators/sha3 updated: 88ada85a84...98089ba372

2
generators/sifive-blocks

Submodule generators/sifive-blocks updated: e8adf0e3ef...1943f289a5

2
generators/sifive-cache

Submodule generators/sifive-cache updated: 2e47c707e0...2dfeb818fb

2
generators/testchipip

Submodule generators/testchipip updated: 70cdc3f020...791853c3ba

2
project/plugins.sbt
View File

@@ -1,3 +1,3 @@
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0")
addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4")
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.3") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.3")

41
scripts/build-setup.sh
View File

@@ -4,10 +4,10 @@
set -e set -e
set -o pipefail set -o pipefail
RDIR=$(git rev-parse --show-toplevel) CYDIR=$(git rev-parse --show-toplevel)
# get helpful utilities # get helpful utilities
source $RDIR/scripts/utils.sh source $CYDIR/scripts/utils.sh
common_setup common_setup
@@ -90,7 +90,7 @@ run_step() {
# setup and install conda environment # setup and install conda environment
if run_step "1"; then if run_step "1"; then
# note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
CONDA_REQS=$RDIR/conda-reqs CONDA_REQS=$CYDIR/conda-reqs
CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs
LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml
@@ -100,10 +100,10 @@ if run_step "1"; then
fi fi
# use conda-lock to create env # use conda-lock to create env
conda-lock install -p $RDIR/.conda-env $LOCKFILE conda-lock install -p $CYDIR/.conda-env $LOCKFILE
source $RDIR/.conda-env/etc/profile.d/conda.sh source $CYDIR/.conda-env/etc/profile.d/conda.sh
conda activate $RDIR/.conda-env conda activate $CYDIR/.conda-env
fi fi
if [ -z "$FORCE_FLAG" ]; then if [ -z "$FORCE_FLAG" ]; then
@@ -115,8 +115,8 @@ fi
# initialize all submodules (without the toolchain submodules) # initialize all submodules (without the toolchain submodules)
if run_step "2"; then if run_step "2"; then
$RDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG $CYDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG
$RDIR/scripts/init-fpga.sh $FORCE_FLAG $CYDIR/scripts/init-fpga.sh $FORCE_FLAG
fi fi
# build extra toolchain collateral (i.e. spike, pk, riscv-tests, libgloss) # build extra toolchain collateral (i.e. spike, pk, riscv-tests, libgloss)
@@ -130,17 +130,17 @@ if run_step "3"; then
fi fi
PREFIX=$RISCV PREFIX=$RISCV
fi fi
$RDIR/scripts/build-toolchain-extra.sh $TOOLCHAIN_TYPE -p $PREFIX $CYDIR/scripts/build-toolchain-extra.sh $TOOLCHAIN_TYPE -p $PREFIX
fi fi
# run ctags for code navigation # run ctags for code navigation
if run_step "4"; then if run_step "4"; then
$RDIR/scripts/gen-tags.sh $CYDIR/scripts/gen-tags.sh
fi fi
# precompile chipyard scala sources # precompile chipyard scala sources
if run_step "5"; then if run_step "5"; then
pushd $RDIR/sims/verilator pushd $CYDIR/sims/verilator
make launch-sbt SBT_COMMAND=";project chipyard; compile" make launch-sbt SBT_COMMAND=";project chipyard; compile"
make launch-sbt SBT_COMMAND=";project tapeout; compile" make launch-sbt SBT_COMMAND=";project tapeout; compile"
popd popd
@@ -148,16 +148,17 @@ fi
# setup firesim # setup firesim
if run_step "6"; then if run_step "6"; then
$RDIR/scripts/firesim-setup.sh $CYDIR/scripts/firesim-setup.sh
$RDIR/sims/firesim/gen-tags.sh $CYDIR/sims/firesim/gen-tags.sh
# precompile firesim scala sources # precompile firesim scala sources
if run_step "7"; then if run_step "7"; then
pushd $RDIR/sims/firesim pushd $CYDIR/sims/firesim
( (
echo $CYDIR
source sourceme-f1-manager.sh --skip-ssh-setup source sourceme-f1-manager.sh --skip-ssh-setup
pushd sim pushd sim
make sbt SBT_COMMAND="project firechip; compile" TARGET_PROJECT=firesim make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim
popd popd
) )
popd popd
@@ -166,12 +167,12 @@ fi
# setup firemarshal # setup firemarshal
if run_step "8"; then if run_step "8"; then
pushd $RDIR/software/firemarshal pushd $CYDIR/software/firemarshal
./init-submodules.sh ./init-submodules.sh
# precompile firemarshal buildroot sources # precompile firemarshal buildroot sources
if run_step "9"; then if run_step "9"; then
source $RDIR/scripts/fix-open-files.sh source $CYDIR/scripts/fix-open-files.sh
./marshal $VERBOSE_FLAG build br-base.json ./marshal $VERBOSE_FLAG build br-base.json
./marshal $VERBOSE_FLAG clean br-base.json ./marshal $VERBOSE_FLAG clean br-base.json
fi fi
@@ -180,13 +181,13 @@ fi
# do misc. cleanup for a "clean" git status # do misc. cleanup for a "clean" git status
if run_step "10"; then if run_step "10"; then
$RDIR/scripts/repo-clean.sh $CYDIR/scripts/repo-clean.sh
fi fi
cat <<EOT >> env.sh cat <<EOT >> env.sh
# line auto-generated by $0 # line auto-generated by $0
conda activate $RDIR/.conda-env conda activate $CYDIR/.conda-env
source $RDIR/scripts/fix-open-files.sh source $CYDIR/scripts/fix-open-files.sh
EOT EOT
echo "Setup complete!" echo "Setup complete!"

2
sims/firesim

Submodule sims/firesim updated: 8176b657ee...792d878a6f

2
toolchains/riscv-tools/riscv-tests

Submodule toolchains/riscv-tools/riscv-tests updated: c84daca882...a6ab6ae600

2
tools/barstools

Submodule tools/barstools updated: 06db605902...b71c31e66e

2
tools/dsptools

Submodule tools/dsptools updated: a1809fbae9...5b1e733596

2
tools/rocket-dsp-utils

Submodule tools/rocket-dsp-utils updated: 4448e06138...46d6ed7798