From 77c3b65fc93b23fd6336858b55b3b20297eaefd7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 26 Dec 2023 09:39:08 -0800 Subject: [PATCH] Don't punch out uart2tsi debug io --- fpga/src/main/scala/arty100t/HarnessBinders.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 64676584..bbb966bb 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -25,11 +25,11 @@ import testchipip._ class WithArty100TUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTTSIPort) => { val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] - val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi") - harnessIO <> port.io + val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi") + harnessIO <> port.io.uart val packagePinsWithPackageIOs = Seq( - ("A9" , IOPin(harnessIO.uart.rxd)), - ("D10", IOPin(harnessIO.uart.txd))) + ("A9" , IOPin(harnessIO.rxd)), + ("D10", IOPin(harnessIO.txd))) packagePinsWithPackageIOs foreach { case (pin, io) => { ath.xdc.addPackagePin(io, pin) ath.xdc.addIOStandard(io, "LVCMOS33")