From 7bfeef6459d084e5f666aef3583a0e99084e0d49 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 31 Mar 2023 18:07:36 -0700
Subject: [PATCH] Bump rocketchip | fix tracegen intnode

---
 generators/rocket-chip                          | 2 +-
 generators/tracegen/src/main/scala/System.scala | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/generators/rocket-chip b/generators/rocket-chip
index c49644ec..02dba8e3 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit c49644ecdd2ebbeed8604011670bcc996322f65e
+Subproject commit 02dba8e3401e435f16cedbc07c0f27ab9604bc4f
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index 53d88c6d..2a0ba3d5 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -3,7 +3,7 @@ package tracegen
 import chisel3._
 import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
-import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource}
+import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
 import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
 import freechips.rocketchip.subsystem._
 import boom.lsu.BoomTraceGenTile
@@ -17,7 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
     case t: GroundTestTile => t.statusNode.makeSink()
     case t: BoomTraceGenTile => t.statusNode.makeSink()
   }
-  val debugNode = NullIntSyncSource()
+  lazy val debugNode = IntSyncXbar() := NullIntSyncSource()
   override lazy val module = new TraceGenSystemModuleImp(this)
 }