From 7c2ec8fb4c0c8a173fa207ebde29956b6c7360c6 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 9 Mar 2023 01:48:25 +0000 Subject: [PATCH] more fixes --- generators/testchipip | 2 +- sims/xcelium/Makefile | 41 +++++++++++++-------------- sims/xcelium/arg-reshuffle | 21 ++++++++++++++ toolchains/riscv-tools/riscv-isa-sim | 2 +- xcelium.mk | 42 ++++++++++------------------ 5 files changed, 57 insertions(+), 51 deletions(-) create mode 100755 sims/xcelium/arg-reshuffle diff --git a/generators/testchipip b/generators/testchipip index 2d78a045..dead693f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 2d78a045386137de3bfd10d6d970db761a92213a +Subproject commit dead693f8f317bfeeb4eb777c4d58c4427fbba31 diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile index 6604b114..ec8b8437 100644 --- a/sims/xcelium/Makefile +++ b/sims/xcelium/Makefile @@ -30,7 +30,7 @@ include $(base_dir)/variables.mk sim_name = xrun ######################################################################################### -# vcs simulator types and rules +# xcelium simulator types and rules ######################################################################################### sim_prefix = simx sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) @@ -66,26 +66,25 @@ $(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR) include $(base_dir)/common.mk ######################################################################################### -# vcs binary and arguments +# xcelium binary and arguments ######################################################################################### -VCS = xrun -64bit -elaborate -#vcs -full64 - -VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) +XCELIUM = xrun +XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES) ######################################################################################### -# vcs build paths +# xcelium build paths ######################################################################################### model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug + ######################################################################################### -# vcs simulator rules +# xcelium simulator rules ######################################################################################### $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf $(model_dir) - $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -xmlibdirname $@ + $(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS) $(sim_run_tcl): $(sim_workdir) echo "$$CAD_INFO_HEADER" > $(sim_run_tcl) @@ -95,12 +94,13 @@ $(sim_run_tcl): $(sim_workdir) $(sim): $(sim_workdir) $(sim_run_tcl) echo "#!/usr/bin/env bash" > $(sim) echo "$$CAD_INFO_HEADER" >> $(sim) - echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_run_tcl)" >> $(sim) + cat arg-reshuffle >> $(sim) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim) chmod +x $(sim) $(sim_debug_run_tcl): $(sim_workdir) echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl) - echo "database -open default_vcd_dump -vcd -into $(sim_out_name).vcd" >> $(sim_debug_run_tcl) + echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl) echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl) echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl) echo "run" >> $(sim_debug_run_tcl) @@ -111,22 +111,19 @@ $(sim_debug_run_tcl): $(sim_workdir) $(sim_debug): $(sim_workdir) $(sim_debug_run_tcl) echo "#!/usr/bin/env bash" > $(sim_debug) echo "$$CAD_INFO_HEADER" >> $(sim_debug) - echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_debug_run_tcl)" >> $(sim_debug) + cat arg-reshuffle >> $(sim_debug) + echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug) chmod +x $(sim_debug) ######################################################################################### -# create vcs vpd/fsdb rules +# create vcd rules ######################################################################################### -.PRECIOUS: $(output_dir)/%.vpd %.vpd -$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) +.PRECIOUS: $(output_dir)/%.vcd %.vcd +$(output_dir)/%.vcd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) -.PRECIOUS: $(output_dir)/%.fsdb %.fsdb -$(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +fsdbfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) - - ######################################################################################### # general cleanup rules ######################################################################################### @@ -135,7 +132,7 @@ clean: rm -rf $(gen_dir) $(sim_prefix)-* ucli.key clean-sim: - rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key + rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log clean-sim-debug: - rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key + rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_workdir) $(sim_debug_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log diff --git a/sims/xcelium/arg-reshuffle b/sims/xcelium/arg-reshuffle new file mode 100755 index 00000000..7ccca217 --- /dev/null +++ b/sims/xcelium/arg-reshuffle @@ -0,0 +1,21 @@ + +regular_args="" +target_args="+permissive" +for var in "$@" +do + if [[ $var = -* ]] || [[ $var = +* ]] + then + if [[ $var = +vcdfile=* ]] + then + XCELIUM_WAVEFORM_FLAG=${var/+vcdfile=/""} + else + regular_args="$regular_args $var" + fi + else + target_args="$target_args +target-argument=$var" + fi +done +target_args="$target_args +permissive-off" + +INPUT_ARGS="$regular_args $target_args" + diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index cd0a5dc5..34bebfe3 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit cd0a5dc55090ca8c4be4c7fb2a7937629c0eccb9 +Subproject commit 34bebfe31183289b5428b9a363a4596750030d3f diff --git a/xcelium.mk b/xcelium.mk index 92ff34cf..3d9ed5ab 100644 --- a/xcelium.mk +++ b/xcelium.mk @@ -1,16 +1,7 @@ -HELP_COMPILATION_VARIABLES += \ -" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB." -HELP_SIMULATION_VARIABLES += \ -" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB." +WAVEFORM_FLAG=+vcdfile=$(sim_out_name).vcd -ifndef USE_VPD -WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb -else -WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd -endif - -# If ntb_random_seed unspecified, vcs uses 1 as constant seed. +# If ntb_random_seed unspecified, xcelium uses 1 as constant seed. # Set ntb_random_seed_automatic to actually get a random seed ifdef RANDOM_SEED SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) @@ -32,19 +23,21 @@ XC_LD_PREFIX=-Wld, REMOVE_RPATH=-Wl,-rpath% -VCS_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS)) -VCS_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS))) +XCELIUM_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS)) +XCELIUM_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS))) -# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate) -VCS_CC_OPTS = \ - $(VCS_CXXFLAGS) \ - $(VCS_LDFLAGS) \ +XCELIUM_COMMON_ARGS = \ + -64bit \ + -xmlibdirname $(sim_workdir) \ + -l /dev/null \ + -log_xmsc_run /dev/null + +XCELIUM_CC_OPTS = \ + $(XCELIUM_CXXFLAGS) \ + $(XCELIUM_LDFLAGS) \ -enable_rpath -#-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \ -# $(filter -l%,$(VCS_LDFLAGS)) - -VCS_NONCC_OPTS = \ +XCELIUM_NONCC_OPTS = \ -fast_recompilation \ -top $(TB) \ -sv \ @@ -54,14 +47,12 @@ VCS_NONCC_OPTS = \ -define INTC_NO_PWR_PINS \ -define INTC_EMULATION \ -f $(sim_common_files) \ - -logfile xrun_elab.log \ -glsperf \ - -genafile access.txt \ -notimingchecks \ -delay_mode zero PREPROC_DEFINES = \ - -define VCS \ + -define XCELIUM \ -define CLOCK_PERIOD=$(CLOCK_PERIOD) \ -define RESET_DELAY=$(RESET_DELAY) \ -define PRINTF_COND=$(TB).printf_cond \ @@ -72,6 +63,3 @@ PREPROC_DEFINES = \ -define RANDOMIZE_GARBAGE_ASSIGN \ -define RANDOMIZE_INVALID_ASSIGN -ifndef USE_VPD -PREPROC_DEFINES += +define+FSDB -endif