diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 879ede57..3a0e2fa9 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter + with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 70770491..ec3c685e 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -23,6 +23,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present + new chipyard.harness.WithChipIdPinFromHarness ++ // drive chip id pin with a plusarg, if chip id pin is present new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness @@ -36,6 +37,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithGPIOCells ++ new chipyard.iobinders.WithSPIFlashIOCells ++ new chipyard.iobinders.WithExtInterruptIOCells ++ + new chipyard.iobinders.WithChipIdPin ++ new chipyard.iobinders.WithCustomBootPin ++ // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop @@ -63,6 +65,7 @@ class AbstractConfig extends Config( new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus + new testchipip.soc.WithChipIdPin ++ // add a chip id pin for setting chip id in multi-chip configs new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index d70519b3..5549d9c4 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -252,6 +252,13 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ } }) +//TODO: Allow setting from harness with chipId argument, hardcoding is temporary hack +class WithChipIdPinFromHarness extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: ChipIdPort) => { + port.io := 0.U + } +}) + class WithSimUARTToUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => { UARTAdapter.connect(Seq(port.io), diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 309ec004..de7f2867 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -27,6 +27,7 @@ import barstools.iocell.chisel._ import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} import testchipip.spi.{SPIChipIO} import testchipip.boot.{CanHavePeripheryCustomBootPin} +import testchipip.soc.{CanHavePeripheryChipIdPin} import testchipip.util.{ClockedIO} import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO} import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig} @@ -355,6 +356,14 @@ class WithSerialTLIOCells extends OverrideIOBinder({ } }) +class WithChipIdPin extends OverrideIOBinder({ + (system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p => + val sys = system.asInstanceOf[BaseSubsystem] + val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true) + (Seq(ChipIdPort(() => port)), cells) + }).getOrElse(Nil, Nil) +}) + class WithSerialTLPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala index 627693aa..6b327a18 100644 --- a/generators/chipyard/src/main/scala/iobinders/Ports.scala +++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala @@ -76,6 +76,9 @@ case class JTAGPort (val getIO: () => JTAGChipIO) case class SerialTLPort (val getIO: () => Data, val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int) extends Port[Data] +case class ChipIdPort (val getIO: () => UInt) + extends Port[UInt] + case class UARTTSIPort (val getIO: () => UARTTSIIO) extends Port[UARTTSIIO]