diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
similarity index 92%
rename from fpga/src/main/scala/arty/e300/Configs.scala
rename to fpga/src/main/scala/arty/Configs.scala
index ee90848e..e074dd03 100644
--- a/fpga/src/main/scala/arty/e300/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -1,5 +1,5 @@
 // See LICENSE for license details.
-package chipyard.fpga.arty.e300
+package chipyard.fpga.arty
 
 import freechips.rocketchip.config._
 import freechips.rocketchip.subsystem._
@@ -16,6 +16,7 @@ import sifive.blocks.devices.uart._
 import sifive.blocks.devices.i2c._
 
 import chipyard.{BuildSystem}
+import chipyard.iobinders
 
 class E300DevKitExtra extends Config((site, here, up) => {
   case PeripheryGPIOKey => List(
@@ -51,7 +52,10 @@ class WithE300System extends Config((site, here, up) => {
 
 class E300ArtyDevKitConfig extends Config(
   new WithE300System ++
-  new WithE300Connections ++
+  new chipyard.iobinders.WithDebugIOCells ++
+  new chipyard.iobinders.WithUARTIOCells ++
+  new WithArtyJTAGHarnessBinder ++
+  new WithArtyUARTHarnessBinder ++
   new E300DevKitExtra ++
   new chipyard.config.WithBootROM ++
   new chipyard.config.WithL2TLBs(1024) ++
diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/DigitalTop.scala
similarity index 94%
rename from fpga/src/main/scala/arty/e300/DigitalTop.scala
rename to fpga/src/main/scala/arty/DigitalTop.scala
index f7d4d8e7..858b6215 100644
--- a/fpga/src/main/scala/arty/e300/DigitalTop.scala
+++ b/fpga/src/main/scala/arty/DigitalTop.scala
@@ -1,4 +1,4 @@
-package chipyard.fpga.arty.e300
+package chipyard.fpga.arty
 
 import chisel3._
 
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
new file mode 100644
index 00000000..0d9a8399
--- /dev/null
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -0,0 +1,73 @@
+package chipyard.fpga.arty
+
+import chisel3._
+import chisel3.experimental.{Analog}
+
+import freechips.rocketchip.config.{Field, Config, Parameters}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
+import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.jtag.{JTAGIO}
+import freechips.rocketchip.system.{SimAXIMem}
+import freechips.rocketchip.subsystem._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.spi._
+
+import barstools.iocell.chisel._
+
+import testchipip._
+
+import chipyard.harness.OverrideHarnessBinder
+import chipyard.HasHarnessSignalReferences
+import chipyard.iobinders.GetSystemParameters
+
+import tracegen.{TraceGenSystemModuleImp}
+import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
+
+import scala.reflect.{ClassTag}
+
+import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
+
+
+
+class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
+  (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
+    ports.map {
+      case d: ClockedDMIIO =>
+        // Want to error here.
+      case j: JTAGIO =>
+        //val dtm_success = WireInit(false.B)
+        //when (dtm_success) { th.success := true.B }
+        //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
+
+        j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt
+
+        IOBUF(th.jd_5, j.TMS)
+        PULLUP(th.jd_5)
+
+        IOBUF(th.jd_4, j.TDI)
+        PULLUP(th.jd_4)
+
+        IOBUF(th.jd_0, j.TDO)
+
+        // mimic putting a pullup on this line (part of reset vote)
+        th.SRST_n := IOBUF(th.jd_6)
+        PULLUP(th.jd_6)
+
+        IOBUF(th.jd_1, j.TRSTn)
+        PULLUP(th.jd_1)
+    }
+    Nil
+  }
+})
+
+class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
+  (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
+    //UARTAdapter.connect(ports)(system.p)
+    IOBUF(th.ck_io(2),  ports.txd)
+    IOBUF(th.ck_io(3),  ports.rxd)
+    Nil
+  }
+})
\ No newline at end of file
diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala
similarity index 99%
rename from fpga/src/main/scala/arty/e300/IOBinders.scala
rename to fpga/src/main/scala/arty/IOBinders.scala
index 6675c325..2b4b332b 100644
--- a/fpga/src/main/scala/arty/e300/IOBinders.scala
+++ b/fpga/src/main/scala/arty/IOBinders.scala
@@ -1,4 +1,4 @@
-package chipyard.fpga.arty.e300
+package chipyard.fpga.arty
 
 import chisel3._
 import chisel3.experimental.{attach, IO}