diff --git a/common.mk b/common.mk
index 2f99a048..0f9e176e 100644
--- a/common.mk
+++ b/common.mk
@@ -22,32 +22,12 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class
 #########################################################################################
 FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
 
-# this should match whatever the commonSettings version is in build.sbt
-BARSTOOLS_VER=1.0
-TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar
-MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar
-
 $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
 	$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
 	mkdir -p $(dir $@)
 	cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
 	touch $@
 
-$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala)
-	cd $(base_dir) && $(SBT) "tapeout/assembly"
-
-$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala)
-	cd $(base_dir) && $(SBT) "barstools-macros/assembly"
-
-.PHONY: jars
-jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
-
-#########################################################################################
-# tapeout and macrocompiler commands
-#########################################################################################
-TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR)
-MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR)
-
 #########################################################################################
 # create simulation args file rule
 #########################################################################################
@@ -68,15 +48,18 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
 #########################################################################################
 REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
 
-$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
-	$(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir)
+$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
+	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
+	cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
 
-$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
-	$(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir)
+$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
+	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
+	grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
-$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR)
-	$(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops
+MACROCOMPILER_MODE ?= --mode synflops
+$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
+	cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
 
 #########################################################################################
 # helper rule to just make verilog files
@@ -139,11 +122,3 @@ regression-tests = \
 run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
 run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
 run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
-
-#########################################################################################
-# general jar cleanup rule
-#########################################################################################
-.PHONY: clean-scala
-clean-scala:
-	rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
-
diff --git a/project/plugins.sbt b/project/plugins.sbt
index 15a88b09..df29eabe 100644
--- a/project/plugins.sbt
+++ b/project/plugins.sbt
@@ -1 +1,3 @@
 addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5")
+addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2")
+
diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile
index 8049bab9..ee04e656 100644
--- a/sims/verisim/Makefile
+++ b/sims/verisim/Makefile
@@ -56,7 +56,7 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-	-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
+	-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
 	touch $@
 
@@ -64,7 +64,7 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name).debug
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-	-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
+	-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
 	touch $@
 
diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile
index 022e8079..3742a895 100644
--- a/sims/vsim/Makefile
+++ b/sims/vsim/Makefile
@@ -55,7 +55,8 @@ VCS_NONCC_OPTS = \
 	+v2k \
 	+vcs+lic+wait \
 	+vc+list \
-	-f $(sim_blackboxes) \
+	-f $(sim_top_blackboxes) \
+	-f $(sim_harness_blackboxes) \
 	-f $(sim_dotf) \
 	-sverilog \
 	+incdir+$(build_dir) \
diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala
index 0f142fd7..240f930f 100644
--- a/src/main/scala/example/Simulator.scala
+++ b/src/main/scala/example/Simulator.scala
@@ -82,6 +82,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     out.close()
   }
   def resources(sim: Simulator): Seq[String] = Seq(
+    "/testchipip/csrc/SimSerial.cc",
     "/csrc/SimDTM.cc",
     "/csrc/SimJTAG.cc",
     "/csrc/remote_bitbang.h",
diff --git a/tools/barstools b/tools/barstools
index 0b9d74ad..e548210e 160000
--- a/tools/barstools
+++ b/tools/barstools
@@ -1 +1 @@
-Subproject commit 0b9d74ada7e3271e82d665b09b3b9ff087c70f91
+Subproject commit e548210ef42e634e75cf283292685728114694c6
diff --git a/variables.mk b/variables.mk
index f44286c5..29a48c6c 100644
--- a/variables.mk
+++ b/variables.mk
@@ -33,10 +33,17 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
 FIRRTL_FILE  ?= $(build_dir)/$(long_name).fir
 ANNO_FILE    ?= $(build_dir)/$(long_name).anno.json
 VERILOG_FILE ?= $(build_dir)/$(long_name).top.v
+TOP_FIR      ?= $(build_dir)/$(long_name).top.fir
+TOP_ANNO     ?= $(build_dir)/$(long_name).top.anno.json
 HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
+HARNESS_FIR  ?= $(build_dir)/$(long_name).harness.fir
+HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json
 SMEMS_FILE   ?= $(build_dir)/$(long_name).mems.v
 SMEMS_CONF   ?= $(build_dir)/$(long_name).mems.conf
+SMEMS_FIR    ?= $(build_dir)/$(long_name).mems.fir
 sim_dotf     ?= $(build_dir)/sim_files.f
+sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
+sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
 
 #########################################################################################
 # default sbt launch command
@@ -64,9 +71,6 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
 #########################################################################################
 # sources needed to run simulators
 #########################################################################################
-sim_blackboxes = \
-  $(build_dir)/firrtl_black_box_resource_files.f
-
 sim_vsrcs = \
 	$(VERILOG_FILE) \
 	$(HARNESS_FILE) \