more docs skeleton

docs/Generators/BOOM.rst

@@ -0,0 +1,10 @@
+Berkeley Out-of-Order Machine (BOOM)
+==============================================
+
+The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. 
+
+BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”).
+
+Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”).
+
+Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages <https://docs.boom-core.org/en/latest/index.html>__`.

docs/Generators/Rocket.rst

@@ -0,0 +1,3 @@
+Rocket
+====================================
+TODO: Basic rocket introduction

docs/Generators/index.rst

@@ -0,0 +1,13 @@
+Generators
+============================
+Generator can be thought of as generalized RTL designs, written using a mix of meta-programming and standard RTL.
+This type of meta-programming is enabled by the Chisel hardware description framework embedded in Scala. 
+A standard RTL design is esentially a degenerate form of a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the ReBAR framework.
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Generators:
+
+   Rocket
+   BOOM
+

docs/Getting-Started/Running-A-Simulation.rst

@@ -43,7 +43,7 @@ Once the simulator has been constructed, we would like to run RISC-V programs on
 
 .. code-block:: shell
 
-  TODO
+  ./simulator-<my_sbt_package_name>-<my_config_name> my_program_binary
 
 Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example
 
@@ -95,7 +95,7 @@ Once the simulator has been constructed, we would like to run RISC-V programs on
 
 .. code-block:: shell
 
-  TODO
+  ./simulator-<my_sbt_package_name>-<my_config_name> my_program_binary
 
 Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example
 

docs/Simulation/Commercial-Simulators.rst

@@ -1,4 +1,4 @@
-Commericial Simulators
+Commericial Software RTL Simulators
 ==============================
 The ReBAR framework currently supports only the VCS commerical simulator
 

docs/Simulation/FPGA-Based-Simulators.rst

@@ -4,10 +4,10 @@ FPGA-Based Simulators
 FireSim
 -----------------------
 FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1).
-FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provide additional device models to allow full-system simulation, including memory models and network models.
+FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provides additional device models to allow full-system simulation, including memory models and network models.
 
 FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. In order to simulate your ReBAR design using FireSim, you should follow the following steps:
 
-Follow the initial EC2 setup instructions as detailed in the FireSim documentatino <link>. Then clone your full ReBAR repository onto your Amazon EC2 FireSim manager instance.
+Follow the initial EC2 setup instructions as detailed in the `FireSim documentation  <http://docs.fires.im/en/latest/Initial-Setup/index.html>`__ .. Then clone your full ReBAR repository onto your Amazon EC2 FireSim manager instance.
 
-Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for running a simulation <link>
+Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation <http://docs.fires.im/en/latest/Running-Simulations-Tutorial/index.html>`__.

docs/Simulation/Open-Source-Simulators.rst

@@ -1,4 +1,4 @@
-Open Source Simulators
+Open Source Software RTL Simulators
 ==============================
 
 Verilator

docs/Simulation/index.rst

@@ -0,0 +1,13 @@
+Simulators
+=======================
+
+ReBAR provides support and intergration for multiple simulation flows, for various user levels and requirments.
+In the majority of cases during a digital design development process, simple software RTL. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. The following pages provide detailed information about the simulation possibilities within the ReBAR framework.
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Simulators:
+
+   Open-Source-Simulators
+   Commercial-Simulators
+   FPGA-Based-Simulators

docs/Tools/Barstools.rst

@@ -0,0 +1,3 @@
+Barstools
+===============================
+Barstools is a collection of useful FIRRTL transformations

docs/Tools/Chisel.rst

@@ -0,0 +1,3 @@
+Chisel
+===========================
+TODO: Chisel intro and pointer to chisel bootcamp

docs/Tools/FIRRTL.rst

@@ -0,0 +1,3 @@
+FIRRTL
+================================
+

docs/Tools/index.rst

@@ -0,0 +1,13 @@
+Tools
+==============================
+The ReBAR framework relays heavily on a set of scala-based tools. While the framework attempts to hide the complexities of these tools, the following pages will introduce them, and how we can use them in order to generate flexible designs
+
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Tools:
+
+   Chisel
+   FIRRTL
+   Barstools
+

docs/VLSI/index.rst

@@ -0,0 +1,8 @@
+VLSI Production
+================================
+The ReBAR framework aim to provide wrappers to a general VLSI flow.
+In particular, we aim to support the HAMMER flow.
+
+.. toctree::
+   :maxdepth: 2
+   :caption: VLSI Production:

docs/conf.py

@@ -181,4 +181,6 @@ texinfo_documents = [
 
 
 # Example configuration for intersphinx: refer to the Python standard library.
-intersphinx_mapping = {'https://docs.python.org/': None}
+intersphinx_mapping = {'python' : ('https://docs.python.org/', None),
+                       'boom' : ('https://docs.boom-core.org/en/latest/', None),
+                        'firesim' : ('http://docs.fires.im/en/latest/', None) }

docs/index.rst

@@ -28,7 +28,6 @@ The documentation outline should look like this
 
 
    Simulation:
-
    Simulation/Open-Source-Simulators/index
    Simulation/Commercial-Simulators/index
    Simulation/FPGA-Based-Simulation/index
@@ -47,6 +46,26 @@ The documentation outline should look like this
 
    Getting-Started/index
 
+   :maxdepth: 3
+   :caption: Simulation:
+   :numbered:
+   Simulation/index
+
+   :maxdepth: 3
+   :caption: Generators:
+   :numbered:
+   Generators/index
+
+   :maxdepth: 3
+   :caption: Tools:
+   :numbered:
+   Tools/index
+
+   :maxdepth: 3
+   :caption: VLSI Production:
+   :numbered:
+   VLSI/index
+
 
 Indices and tables
 ==================