diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala
index e2d7974f..b27a5e65 100644
--- a/macros/src/main/scala/MacroCompiler.scala
+++ b/macros/src/main/scala/MacroCompiler.scala
@@ -839,6 +839,19 @@ object MacroCompiler extends App {
           }
           case None =>
         }
+      } else {
+        // Warn user
+        System.err println "WARNING: Empty *.mems.conf file. No memories generated."
+
+        // Emit empty verilog file if no macros found
+        params.get(Verilog) match {
+          case Some(verilogFile: String) => {
+            // Create an empty verilog file
+            val verilogWriter = new FileWriter(new File(verilogFile))
+            verilogWriter.close()
+          }
+          case None =>
+        }
       }
     } catch {
       case e: java.util.NoSuchElementException =>
diff --git a/macros/src/main/scala/MemConf.scala b/macros/src/main/scala/MemConf.scala
index ded4a889..72342a17 100644
--- a/macros/src/main/scala/MemConf.scala
+++ b/macros/src/main/scala/MemConf.scala
@@ -47,9 +47,13 @@ object MemConf {
   val regex = raw"\s*name\s+(\w+)\s+depth\s+(\d+)\s+width\s+(\d+)\s+ports\s+([^\s]+)\s+(?:mask_gran\s+(\d+))?\s*".r
 
   def fromString(s: String): Seq[MemConf] = {
-    s.split("\n").toSeq.map(_ match {
-      case MemConf.regex(name, depth, width, ports, maskGran) => MemConf(name, depth.toInt, width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt))
-      case _ => throw new Exception(s"Error parsing MemConf string : ${s}")
-    })
+    if (s.isEmpty) {
+      Seq[MemConf]()
+    } else {
+      s.split("\n").toSeq.map(_ match {
+        case MemConf.regex(name, depth, width, ports, maskGran) => MemConf(name, depth.toInt, width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt))
+        case _ => throw new Exception(s"Error parsing MemConf string : ${s}")
+      })
+    }
   }
 }