From e78756704bcd2d2605bd845df6d37b41301a6dac Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 18:14:50 -0800 Subject: [PATCH 1/4] FIX: fix vcu118 sd card frequency --- fpga/src/main/resources/vcu118/sdboot/sd.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index f1bdb61e..60bebbd8 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -22,7 +22,7 @@ #error Must define TL_CLK #endif -#define F_CLK TL_CLK +#define F_CLK (TL_CLK) static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); @@ -79,7 +79,9 @@ static inline void sd_cmd_end(void) static void sd_poweron(void) { long i; - REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); + // HACK: frequency change + // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); + REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2.5); REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; for (i = 10; i > 0; i--) { sd_dummy(); @@ -176,7 +178,9 @@ static int copy(void) // TODO: Speed up SPI freq. (breaks between these two values) //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); - REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); + // HACK: frequency change + // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); + REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2); // / 0.5 if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { sd_cmd_end(); return 1; From 069a9d2999d53b26550387506097c38fc420c4a3 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 5 Dec 2023 15:07:25 -0800 Subject: [PATCH 2/4] ADD: add equation for setting certain SPI clock speed --- fpga/src/main/resources/vcu118/sdboot/sd.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index 60bebbd8..e8d45ba7 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -22,7 +22,14 @@ #error Must define TL_CLK #endif -#define F_CLK (TL_CLK) +#define F_CLK (TL_CLK) + +// SPI SCLK frequency, in kHz +#define SPI_CLK 1250 + +// SPI clock divisor value +// @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi +#define SPI_DIV (((F_CLK * 1000) / SPI_CLK) / 2 - 1) static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); @@ -80,8 +87,8 @@ static void sd_poweron(void) { long i; // HACK: frequency change - // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); - REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2.5); + + REG32(spi, SPI_REG_SCKDIV) = SPI_DIV; REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; for (i = 10; i > 0; i--) { sd_dummy(); @@ -173,14 +180,10 @@ static int copy(void) dputs("CMD18"); - kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B); + kprintf("LOADING 0x%x B PAYLOAD\r\n", PAYLOAD_SIZE_B); kprintf("LOADING "); - // TODO: Speed up SPI freq. (breaks between these two values) - //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); - // HACK: frequency change - // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); - REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2); // / 0.5 + REG32(spi, SPI_REG_SCKDIV) = SPI_DIV; if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { sd_cmd_end(); return 1; From 516ecf9d9e61fd3ee2cedb1681947bd0bcf6a12c Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 20 Dec 2023 22:16:15 -0800 Subject: [PATCH 3/4] ADD: increase frequency to maximum --- fpga/src/main/resources/vcu118/sdboot/sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index e8d45ba7..c89f1556 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -25,7 +25,7 @@ #define F_CLK (TL_CLK) // SPI SCLK frequency, in kHz -#define SPI_CLK 1250 +#define SPI_CLK 25000 // 1250 // SPI clock divisor value // @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi From c32de04b5d0535df406cccc25109311fb08c49ff Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 20 Dec 2023 22:25:05 -0800 Subject: [PATCH 4/4] ADD: add inline docs --- fpga/src/main/resources/vcu118/sdboot/sd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index c89f1556..bc1a68e8 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -25,7 +25,9 @@ #define F_CLK (TL_CLK) // SPI SCLK frequency, in kHz -#define SPI_CLK 25000 // 1250 +// We are using the 25MHz High Speed mode. If this speed is not supported by the +// SD card, consider changing to the Default Speed mode (12.5 MHz). +#define SPI_CLK 25000 // SPI clock divisor value // @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi