[skip ci] add power-rtl and power-syn targets

docs/VLSI/Advanced-Usage.rst

@@ -47,37 +47,51 @@ For more information about all the options that can be passed to the Hammer comm
 
 Manual Step Execution & Dependency Tracking
 -------------------------------------------
-It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
+It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--stop_after_step``, ``--start_before_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
 
 Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par`` to run certain actions without typing out the entire Hammer command.
 
-Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
+Say you need to update some power straps settings in ``new_power_straps.yml`` and want to try out the new settings:
 
 .. code-block:: shell
 
-   make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
+   make redo-par HAMMER_REDO_ARGS='-p new_power_straps.yml --only_step power_straps'
+
+The command that is executed will be:
+
+.. code-block:: shell
+
+    ./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json -p new_power_straps.yml --only_step power_straps --obj_dir /path/to/build par
 
 Hierarchical RTL/Gate-level Simulation, Power Estimation
 --------------------------------------------------------
-With the Synopsys plugin, hierarchical RTL and gate-level simulation is supported using VCS at the chip-level. Also, post-par power estimation with Voltus in the Cadence plugin is also supported. Special Make targets are provided in the ``vlsi/`` directory in ``sims.mk`` and ``power.mk``. Here is a brief description:
+With the Synopsys plugin, hierarchical RTL and gate-level simulation is supported using VCS at the chip-level. Also, rtl-level/post-syn power estimation with Joules and post-par power estimation with Voltus in the Cadence plugin is also supported. Special Make targets are provided in the ``vlsi/`` directory in ``sims.mk`` and ``power.mk``. Here is a brief description:
 
 * ``sim-rtl``: RTL-level simulation
 
-  * ``sim-rtl-debug``: Also write a VPD waveform
+  * ``sim-rtl-debug``: Also write a FSDB waveform
 
 * ``sim-syn``: Post-synthesis gate-level simulation
 
-  * ``sim-syn-debug``: Also write a VPD waveform
-  * ``sim-syn-timing-debug``: Timing-annotated with VPD waveform
+  * ``sim-syn-debug``: Also write a FSDB waveform
+  * ``sim-syn-timing-debug``: Timing-annotated with FSDB waveform
 
 * ``sim-par``: Post-par gate-level simulation
 
-  * ``sim-par-debug``: Also write a VPD waveform
-  * ``sim-par-timing-debug``: Timing-annotated with VPD waveform
+  * ``sim-par-debug``: Also write a FSDB waveform
+  * ``sim-par-timing-debug``: Timing-annotated with FSDB waveform
+
+* ``power-rtl``: RTL-level power estimation
+
+  * Note: this will run ``sim-rtl-debug`` first
+
+* ``power-syn``: Post-synthesis power estimation
+
+  * Note: this will run ``sim-syn-debug`` first
 
 * ``power-par``: Post-par power estimation
 
-  * Note: this will run ``sim-par`` first
+  * Note: this will run ``sim-par-debug`` first
 
 * ``redo-`` can be appended to all above targets to break dependency tracking, like described above.