diff --git a/generators/boom b/generators/boom index 8d3162cb..ff8c25af 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 8d3162cbbe6f0db19a39a2f22226ab9eb6edea31 +Subproject commit ff8c25af0b14c7eba67451f574e1ddacaaf8a5b6 diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala deleted file mode 100644 index 275414ff..00000000 --- a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala +++ /dev/null @@ -1,94 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -trait HasBoomAndRocketTiles extends HasTiles - with CanHavePeripheryPLIC - with CanHavePeripheryCLINT - with HasPeripheryDebug -{ this: BaseSubsystem => - - val module: HasBoomAndRocketTilesModuleImp - - protected val rocketTileParams = p(RocketTilesKey) - protected val boomTileParams = p(BoomTilesKey) - private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) - private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) - - // Make a tile and wire its nodes into the system, - // according to the specified type of clock crossing. - // Note that we also inject new nodes into the tile itself, - // also based on the crossing type. - val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => - val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(rocket, crossing) - connectSlavePortsToCBus(rocket, crossing) - connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) - - rocket - } - - println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") - - val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => - val boomCore = LazyModule( - new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(boomCore, crossing) - connectSlavePortsToCBus(boomCore, crossing) - connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) - - boomCore - } - - println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") - - val boomAndRocketTiles = rocketTiles ++ boomTiles - println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") - - def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ - (boomTiles map { t => t.module.core.coreMonitorBundle}).toList - - def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) - - def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) -} - -trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp - with HasPeripheryDebugModuleImp { - val outer: HasBoomAndRocketTiles -} - -class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem - with HasBoomAndRocketTiles { - val tiles = boomAndRocketTiles - override lazy val module = new BoomAndRocketSubsystemModuleImp(this) -} - -class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasBoomAndRocketTilesModuleImp { - tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => - wire.clock := clock - wire.reset := reset - wire.hartid := i.U - wire.reset_vector := global_reset_vector - } -} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 2816352d..363f0895 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -109,72 +109,6 @@ class WithGPIORocketTop extends Config((site, here, up) => { } }) -// -------------------------------------- -// BOOM Top Level System Parameter Mixins -// -------------------------------------- - -/** - * Class to specify a "plain" top level BOOM system - */ -class WithNormalBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomTop()(p)).module) - } -}) - -/** - * Class to specify a top level BOOM system with PWM - */ -class WithPWMBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a PWM AXI4 - */ -class WithPWMAXI4BoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a block device - */ -class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level BOOM system with a simulator block device - */ -class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level BOOM system with GPIO - */ -class WithGPIOBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // -------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins // -------------------------------------- @@ -240,19 +174,3 @@ class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { top } }) - -/** - * Class to renumber BOOM + Rocket harts so that there are no overlapped harts - * This mixin assumes Rocket tiles are numbered before BOOM tiles - * Also makes support for multiple harts depend on Rocket + BOOM - * Note: Must come after all harts are assigned for it to apply - */ -class WithRenumberHarts extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => - r.copy(hartId = i) - } - case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => - b.copy(hartId = i + up(RocketTilesKey, site).length) - } - case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) -}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 74e9a131..ee17916f 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -75,11 +75,11 @@ class SmallBaseBoomConfig extends Config( new boom.system.SmallBoomConfig) class DefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new BaseBoomConfig) class SmallDefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new SmallBaseBoomConfig) class HwachaBoomConfig extends Config( @@ -91,26 +91,26 @@ class RoccBoomConfig extends Config( new DefaultBoomConfig) class PWMBoomConfig extends Config( - new WithPWMBoomTop ++ + new WithPWMBoomAndRocketTop ++ new BaseBoomConfig) class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomTop ++ + new WithPWMAXI4BoomAndRocketTop ++ new BaseBoomConfig) class SimBlockDeviceBoomConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomTop ++ + new WithSimBlockDeviceBoomAndRocketTop ++ new BaseBoomConfig) class BlockDeviceModelBoomConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomTop ++ + new WithBlockDeviceModelBoomAndRocketTop ++ new BaseBoomConfig) class GPIOBoomConfig extends Config( new WithGPIO ++ - new WithGPIOBoomTop ++ + new WithGPIOBoomAndRocketTop ++ new BaseBoomConfig) /** @@ -118,7 +118,7 @@ class GPIOBoomConfig extends Config( * the `WithNBoomCores` with the DefaultBoomConfig params */ class DualCoreBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ @@ -127,7 +127,7 @@ class DualCoreBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ @@ -137,7 +137,7 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) @@ -147,7 +147,7 @@ class RV32UnifiedBoomConfig extends Config( class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(1) ++ @@ -157,7 +157,7 @@ class BaseBoomAndRocketConfig extends Config( class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.DefaultBoomConfig ++ @@ -208,7 +208,7 @@ class GPIOBoomAndRocketConfig extends Config( class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ @@ -219,7 +219,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( class RV32BoomAndRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala deleted file mode 100644 index cc7fd3db..00000000 --- a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala +++ /dev/null @@ -1,62 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -/** - * Example top with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem - with HasAsyncExtInterrupts - with boom.system.CanHaveMisalignedMasterAXI4MemPort - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port - with HasPeripheryBootROM -{ - override lazy val module = new ExampleBoomAndRocketSystemModule(this) - - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - -/** - * Example top module with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) - with HasRTCModuleImp - with HasExtInterruptsModuleImp - with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp - with CanHaveMasterAXI4MMIOPortModuleImp - with CanHaveSlaveAXI4PortModuleImp - with HasPeripheryBootROMModuleImp - with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index a517b6b8..3d488c1c 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -43,41 +43,6 @@ class RocketTestHarness(implicit val p: Parameters) extends Module { io.success := dut.connectSimSerial() } -// ----------------- -// BOOM Test Harness -// ----------------- - -case object BuildBoomTop extends Field[(Clock, Bool, Parameters) => BoomTopModule[BoomTop]] - -class BoomTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - // force Chisel to rename module - override def desiredName = "TestHarness" - - val dut = p(BuildBoomTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - io.success := dut.connectSimSerial() -} - // -------------------------- // BOOM + Rocket Test Harness // -------------------------- diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 50e5d0c6..a481deef 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -71,74 +71,17 @@ class RocketTopWithGPIOModule(l: RocketTopWithGPIO) extends RocketTopModule(l) with HasPeripheryGPIOModuleImp -// ---------------------- -// BOOM Top Level Systems -// ---------------------- - -class BoomTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new BoomTopModule(this) -} - -class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.ExampleBoomSystemModule(l) - with HasRTCModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMTL(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMTL { - override lazy val module = new BoomTopWithPWMTLModule(this) -} - -class BoomTopWithPWMTLModule(l: BoomTopWithPWMTL) extends BoomTopModule(l) - with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMAXI4(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMAXI4 { - override lazy val module = new BoomTopWithPWMAXI4Module(this) -} - -class BoomTopWithPWMAXI4Module(l: BoomTopWithPWMAXI4) extends BoomTopModule(l) - with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop - with HasPeripheryBlockDevice { - override lazy val module = new BoomTopWithBlockDeviceModule(this) -} - -class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l) - with HasPeripheryBlockDeviceModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop - with HasPeripheryGPIO { - override lazy val module = new BoomTopWithGPIOModule(this) -} - -class BoomTopWithGPIOModule(l: BoomTopWithGPIO) - extends BoomTopModule(l) - with HasPeripheryGPIOModuleImp - // ------------------------------- // BOOM + Rocket Top Level Systems // ------------------------------- -class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem +class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem with HasNoDebug with HasPeripherySerial { override lazy val module = new BoomAndRocketTopModule(this) } -class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp diff --git a/variables.mk b/variables.mk index 62cd35ce..fb4f3632 100644 --- a/variables.mk +++ b/variables.mk @@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),boomexample) CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomTop + TOP ?= BoomAndRocketTop endif # for a BOOM + Rocket based example system ifeq ($(SUB_PROJECT),boomrocketexample) @@ -72,7 +72,7 @@ ifeq ($(SUB_PROJECT),boom) CONFIG_PACKAGE ?= boom.system GENERATOR_PACKAGE ?= boom.system TB ?= TestDriver - TOP ?= ExampleBoomSystem + TOP ?= ExampleBoomAndRocketSystem endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) @@ -186,4 +186,3 @@ sim_vsrcs = \ # assembly/benchmark variables ######################################################################################### timeout_cycles = 10000000 -bmark_timeout_cycles = 100000000