Remove hwacha/esp-tools

.github/scripts/check-commit.sh

@@ -45,21 +45,11 @@ search () {
     done
 }
 
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
 dir="generators"
 branches=("master" "main" "dev")
 search
 
-submodules=("esp-tools-feedstock")
-dir="toolchains/esp-tools"
-branches=("main")
-search
-
-submodules=("riscv-isa-sim" "riscv-pk" "riscv-tests")
-dir="toolchains/esp-tools"
-branches=("master")
-search
-
 submodules=("riscv-tools-feedstock")
 dir="toolchains/riscv-tools"
 branches=("main")

.github/scripts/defaults.sh

@@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
-grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
+grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
@@ -52,7 +52,6 @@ mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
 mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
 mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
 mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
-mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
 mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"

.github/scripts/run-tests.sh

@@ -77,9 +77,6 @@ case $1 in
     rocketchip)
         run_bmark
         ;;
-    chipyard-hwacha)
-        make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS
-        ;;
     chipyard-gemmini)
         GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
         rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests

.gitmodules

@@ -28,9 +28,6 @@
 [submodule "generators/hardfloat"]
 	path = generators/hardfloat
 	url = https://github.com/ucb-bar/berkeley-hardfloat.git
-[submodule "generators/hwacha"]
-	path = generators/hwacha
-	url = https://github.com/ucb-bar/hwacha.git
 [submodule "generators/ibex"]
 	path = generators/ibex
 	url = https://github.com/ucb-bar/ibex-wrapper.git
@@ -88,18 +85,6 @@
 [submodule "software/spec2017"]
 	path = software/spec2017
 	url = https://github.com/ucb-bar/spec2017-workload.git
-[submodule "toolchains/esp-tools/esp-tools-feedstock"]
-	path = toolchains/esp-tools/esp-tools-feedstock
-	url = https://github.com/ucb-bar/esp-tools-feedstock.git
-[submodule "toolchains/esp-tools/riscv-isa-sim"]
-	path = toolchains/esp-tools/riscv-isa-sim
-	url = https://github.com/ucb-bar/esp-isa-sim.git
-[submodule "toolchains/esp-tools/riscv-pk"]
-	path = toolchains/esp-tools/riscv-pk
-	url = https://github.com/riscv-software-src/riscv-pk.git
-[submodule "toolchains/esp-tools/riscv-tests"]
-	path = toolchains/esp-tools/riscv-tests
-	url = https://github.com/ucb-bar/esp-tests.git
 [submodule "toolchains/libgloss"]
 	path = toolchains/libgloss
 	url = https://github.com/ucb-bar/libgloss-htif.git

README.md

@@ -16,7 +16,7 @@ To get started using Chipyard, see the stable documentation on the Chipyard docu
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
@@ -65,7 +65,6 @@ These additional publications cover many of the internal components used in Chip
     * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://old.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf).
       * **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf).
       * **COBRA (BOOM Branch Prediction)**: J. Zhao, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408173).
-    * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf).
     * **Gemmini**: H. Genc, et al., *DAC'21*. [PDF](https://arxiv.org/pdf/1911.09925).
 * **Sims**
     * **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf).
@@ -87,7 +86,6 @@ These additional publications cover many of the internal components used in Chip
 
 This work is supported by the NSF CCRI ENS Chipyard Award #2016662.
 
-[hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf
 [hammer]:https://github.com/ucb-bar/hammer
 [firesim]:https://fires.im
 [ucb-bar]: http://bar.eecs.berkeley.edu

build.sbt

@@ -156,7 +156,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
   .settings(commonSettings)
 
 lazy val chipyard = (project in file("generators/chipyard"))
-  .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
+  .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
@@ -199,11 +199,6 @@ lazy val icenet = (project in file("generators/icenet"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val hwacha = (project in file("generators/hwacha"))
-  .dependsOn(rocketchip)
-  .settings(libraryDependencies ++= rocketLibDeps.value)
-  .settings(commonSettings)
-
 lazy val boom = freshProject("boom", file("generators/boom"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)

conda-reqs/esp-tools.yaml

@@ -1,18 +0,0 @@
-channels:
-    - ucb-bar
-    - conda-forge
-    - litex-hub
-    - nodefaults
-
-platforms:
-    - linux-64
-
-dependencies:
-    # https://conda-forge.org/feedstock-outputs/
-    #   filterable list of all conda-forge packages
-    # https://conda-forge.org/#contribute
-    #   instructions on adding a recipe
-    # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
-    #   documentation on package_spec syntax for constraining versions
-
-    - esp-tools==1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/esp-tools-feedstock

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -31,12 +31,6 @@ Processor Cores
 Accelerators
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-**Hwacha**
-  A decoupled vector architecture co-processor.
-  Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model.
-  Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface.
-  See :ref:`Generators/Hwacha:Hwacha` for more information.
-
 **Gemmini**
   A matrix-multiply accelerator targeting neural-networks
 
@@ -95,10 +89,6 @@ Toolchains
   The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.).
   Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework.
 
-**esp-tools**
-  A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension.
-  This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.)
-
 Software
 -------------------------------------------
 

docs/Chipyard-Basics/Initial-Repo-Setup.rst

@@ -63,11 +63,7 @@ Start by checking out the proper Chipyard version. Run:
     # note: this may not be the latest release if the documentation version != "stable"
     git checkout |version|
 
-Next run the following script to fully setup Chipyard with a specific toolchain.
-There are two toolchains, one for normal RISC-V programs called ``riscv-tools`` which is the one needed for most Chipyard use-cases, and another for Hwacha called ``esp-tools``.
-Run the following script based off which compiler you would like to use.
-
-.. Note:: Prior versions of Chipyard recommended ``esp-tools`` for Gemmini development. Gemmini should now be used with the standard ``riscv-tools``.
+Next run the following script to fully setup Chipyard with the ``riscv-tools`` toolchain.
 
 .. Warning:: The following script will complete a "full" installation of Chipyard which may take a long time depending on the system.
     Ensure that this script completes fully (no interruptions) before continuing on. User can use the ``--skip`` or ``-s`` flag to skip steps:
@@ -96,7 +92,7 @@ Run the following script based off which compiler you would like to use.
 
 .. code-block:: shell
 
-    ./build-setup.sh riscv-tools # or esp-tools
+    ./build-setup.sh riscv-tools
 
 This script wraps around the conda environment initialization process, initializes all submodules (with the ``init-submodules-no-riscv-tools.sh`` script), installs a toolchain, and runs other setups.
 See ``./build-setup.sh --help`` for more details on what this does and how to disable parts of the setup.
@@ -107,7 +103,7 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di
 
 .. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc).
 
-.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock and https://github.com/ucb-bar/esp-tools-feedstock repositories (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
+.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
 
 By running the following command you should see a environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``.
 

docs/Customization/Custom-Chisel.rst

@@ -59,7 +59,7 @@ should look something like this:
 .. code-block:: scala
 
     lazy val chipyard = (project in file("generators/chipyard"))
-        .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
+        .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
             sha3, dsptools, `rocket-dsp-utils`,
             gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
             yourproject, // <- added to the middle of the list for simplicity

docs/Customization/Heterogeneous-SoCs.rst

@@ -4,7 +4,7 @@ Heterogeneous SoCs
 ===============================
 
 The Chipyard framework involves multiple cores and accelerators that can be composed in arbitrary ways.
-This discussion will focus on how you combine Rocket, BOOM and Hwacha in particular ways to create a unique SoC.
+This discussion will focus on how you combine Rocket and BOOM in particular ways to create a unique SoC.
 
 Creating a Rocket and BOOM System
 -------------------------------------------
@@ -21,40 +21,6 @@ The following example shows a dual core BOOM with a single core Rocket.
     :end-before: DOC include end: DualBoomAndSingleRocket
 
 
-Adding Hwachas
--------------------------------------------
-
-Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter.
-An example of adding a Hwacha to all tiles in the system is below.
-
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala
-    :language: scala
-    :start-after: DOC include start: BoomAndRocketWithHwacha
-    :end-before: DOC include end: BoomAndRocketWithHwacha
-
-In this example, Hwachas are added to both BOOM tiles and to the Rocket tile.
-All with the same Hwacha parameters.
-
-Assigning Accelerators to Specific Tiles with MultiRoCC
--------------------------------------------------------
-
-Located in ``generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC.
-Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile.
-For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles.
-An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached.
-
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala
-    :language: scala
-    :start-after: DOC include start: DualBoomAndRocketOneHwacha
-    :end-before: DOC include end: DualBoomAndRocketOneHwacha
-
-The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``0`` corresponds to the Rocket core).
-Finally, the ``WithMultiRoCC`` config fragment is called.
-This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default.
-This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter.
-If this is used earlier in the configuration sequence, then MultiRoCC does not work.
-
-This config fragment can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``).
 
 Since config fragments are applied from right-to-left (or bottom-to-top as they are formatted here), the right-most config fragment specifying a core (which is ``freechips.rocketchip.subsystem.WithNBigCores`` in the example above) gets the first hart ID.
 Consider this config:

docs/Generators/Hwacha.rst

@@ -1,15 +0,0 @@
-Hwacha
-====================================
-
-The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.
-The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven
-The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal.
-
-For more information on the Hwacha project, please visit the `Hwacha website <https://bar.eecs.berkeley.edu/projects/hwacha.html>`__ or search for "Krste Asanovic Hwacha" on Google Scholar for publications.
-
-To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache).
-
-To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala <https://github.com/ucb-bar/hwacha/blob/master/src/main/scala/configs.scala>`__ to see the possible configuration parameters.
-
-Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions.
-To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it.

docs/Generators/index.rst

@@ -22,7 +22,6 @@ so changes to the generators themselves will automatically be used when building
    Rocket
    BOOM
    Constellation
-   Hwacha
    Gemmini
    IceNet
    TestChipIP

docs/Simulation/Software-RTL-Simulation.rst

@@ -155,13 +155,6 @@ Therefore, in order to simulate a simple Rocket-based example system we can use:
     ./simulator-<yourproject>-<yourconfig> ...
 
 
-All ``make`` targets that can be applied to the default example, can also be applied to custom project using the custom environment variables. For example, the following code example will run the RISC-V assembly benchmark suite on the Hwacha subproject:
-
-.. code-block:: shell
-
-    make SUB_PROJECT=hwacha run-asm-tests
-
-
 Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral while the generated Verilog source files resides in ``generated-src/<...>-<package>-<config>/gen-collateral`` for the build/simulation.
 Specifically, for ``CONFIG=RocketConfig`` the SoC top-level (``TOP``) Verilog file is ``ChipTop.sv`` while the (``Model``) file is ``TestHarness.sv``.
 

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -12,36 +12,6 @@ class LargeBoomAndRocketConfig extends Config(
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-// DOC include start: BoomAndRocketWithHwacha
-class HwachaLargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
-  new boom.v3.common.WithNLargeBooms(1) ++                      // add 1 boom core
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: BoomAndRocketWithHwacha
-
-class LargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
-  new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
-  new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.v3.common.WithNLargeBooms(1) ++                                 // add 1 boom core
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
-// DOC include start: DualBoomAndRocketOneHwacha
-class DualLargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
-  new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
-  new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.v3.common.WithNLargeBooms(2) ++                                 // add 2 boom cores
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: DualBoomAndRocketOneHwacha
-
 class DualLargeBoomAndDualRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(2) ++  // add 2 rocket cores

generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala

@@ -33,13 +33,6 @@ class LeanGemminiPrintfRocketConfig extends Config(
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class HwachaRocketConfig extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
 class MempressRocketConfig extends Config(
   new mempress.WithMemPress ++                                    // use Mempress (memory traffic generation) accelerator
   new chipyard.config.WithExtMemIdBits(7) ++                      // use 7 bits for tl like request id
@@ -50,13 +43,6 @@ class MempressRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class HwachaLargeBoomV3Config extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new boom.v3.common.WithNLargeBooms(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
 class AES256ECBRocketConfig extends Config(
   new aes.WithAES256ECBAccel ++                                   // use Caliptra AES 256 ECB accelerator
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++

generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala

@@ -6,7 +6,6 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.diplomacy._
 
-import hwacha.{Hwacha}
 import gemmini._
 
 import chipyard.{TestSuitesKey, TestSuiteHelper}
@@ -34,47 +33,6 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) =>
   }
 })
 
-/**
- * Config fragment to add Hwachas to cores based on hart
- *
- * For ex:
- *   Core 0, 1, 2, 3 have been defined earlier
- *     with tileIds of 0, 1, 2, 3 respectively
- *   And you call WithMultiRoCCHwacha(0,1)
- *   Then Core 0 and 1 will get a Hwacha
- *
- * @param harts harts to specify which will get a Hwacha
- */
-class WithMultiRoCCHwacha(harts: Int*) extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new Config((site, here, up) => {
-    case MultiRoCCKey => {
-      up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
-        (i -> Seq((p: Parameters) => {
-          val hwacha = LazyModule(new Hwacha()(p))
-          hwacha
-        }))
-      }
-    }
-  })
-)
-
-class WithHwachaTest extends Config((site, here, up) => {
-  case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
-    up(TestSuitesKey).apply(tileParams, suiteHelper, p)
-    import hwacha.HwachaTestSuites._
-    suiteHelper.addSuites(rv64uv.map(_("p")))
-    suiteHelper.addSuites(rv64uv.map(_("vp")))
-    suiteHelper.addSuite(rv64sv("p"))
-    suiteHelper.addSuite(hwachaBmarks)
-    "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
-  }
-})
-
-/**
-  * The MultiRoCCGemmini fragment functions similarly to the
-  * WithMultiRoCCHwacha fragment defined above
-  */
 class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data](
   harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => {
   case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i =>

scripts/build-setup.sh

@@ -12,11 +12,10 @@ source $CYDIR/scripts/utils.sh
 common_setup
 
 usage() {
-    echo "Usage: ${0} [OPTIONS] [riscv-tools | esp-tools]"
+    echo "Usage: ${0} [OPTIONS] [riscv-tools]"
     echo ""
     echo "Installation Types"
     echo "  riscv-tools: if set, builds the riscv toolchain (this is also the default)"
-    echo "  esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator"
     echo ""
     echo "Helper script to fully initialize repository that wraps other scripts."
     echo "By default it initializes/installs things in the following order:"
@@ -69,7 +68,7 @@ do
     case $1 in
         -h | --help )
             usage 3 ;;
-        riscv-tools | esp-tools)
+        riscv-tools )
             TOOLCHAIN_TYPE=$1 ;;
         --verbose | -v)
             VERBOSE_FLAG=$1
@@ -119,29 +118,6 @@ run_step() {
 
 {
 
-# esp-tools should ONLY be used for hwacha.
-# Check for this, since many users will be attempting to use this with gemmini
-if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then
-    while true; do
-        printf '\033[2J'
-        read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
-        case "$validate" in
-            y | Y)
-                echo "Installing esp-tools."
-                break
-                ;;
-            n | N)
-                error "Rerun with riscv-tools"
-                exit 3
-                ;;
-            *)
-                error "Invalid response. Please type \"y\" or \"n\""
-                ;;
-        esac
-    done
-fi
-
-
 #######################################
 ###### BEGIN STEP-BY-STEP SETUP #######
 #######################################

scripts/build-toolchain-extra.sh

@@ -16,11 +16,10 @@ common_setup
 readonly MAKE
 
 usage() {
-    echo "usage: ${0} [OPTIONS] [riscv-tools | esp-tools]"
+    echo "usage: ${0} [OPTIONS] [riscv-tools]"
     echo ""
     echo "Installation Types"
     echo "   riscv-tools: if set, builds the riscv toolchain (this is also the default)"
-    echo "   esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator"
     echo ""
     echo "Options"
     echo "   --prefix -p PREFIX    : Install destination."
@@ -45,7 +44,7 @@ do
             RISCV=$(realpath $1) ;;
         --clean-after-install )
             CLEANAFTERINSTALL="true" ;;
-        riscv-tools | esp-tools)
+        riscv-tools )
             TOOLCHAIN=$1 ;;
         * )
             error "invalid option $1"

scripts/generate-conda-lockfiles.sh

@@ -10,7 +10,7 @@ if [ ! -d "$REQS_DIR" ]; then
   exit 1
 fi
 
-for TOOLCHAIN_TYPE in riscv-tools esp-tools; do
+for TOOLCHAIN_TYPE in riscv-tools; do
     # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
     LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml
     rm -rf $LOCKFILE

scripts/repo-clean.sh

@@ -9,9 +9,6 @@ rm -rf $RDIR/toolchains/libgloss/build.log
 rm -rf $RDIR/toolchains/riscv-tools/riscv-isa-sim/build.log
 rm -rf $RDIR/toolchains/riscv-tools/riscv-pk/build.log
 rm -rf $RDIR/toolchains/riscv-tools/riscv-tests/build.log
-rm -rf $RDIR/toolchains/esp-tools/riscv-isa-sim/build.log
-rm -rf $RDIR/toolchains/esp-tools/riscv-pk/build.log
-rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log
 (
     pushd $RDIR/generators/constellation
     if [ -d espresso ]

scripts/tutorial-patches/build.sbt.patch

@@ -5,7 +5,7 @@ index c3be6161..2a6d7160 100644
 @@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
  
  lazy val chipyard = (project in file("generators/chipyard"))
-   .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
+   .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +    //sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, rocket_dsp_utils,

sims/common-sim-flags.mk

@@ -2,17 +2,8 @@
 # common gcc configuration/optimization
 #----------------------------------------------------------------------------------------
 SIM_OPT_CXXFLAGS := -O3
-
-# Workaround: esp-isa-sim doesn't install libriscv,
-# so don't link with libriscv if it doesn't exist
-# potentially breaks some configs
-
-ifeq (,$(wildcard $(RISCV)/lib/libriscv.so))
-$(warning libriscv not found)
-LRISCV=
-else
 LRISCV=-lriscv
-endif
+
 
 SIM_CXXFLAGS = \
 	$(CXXFLAGS) \

variables.mk

@@ -78,18 +78,6 @@ ifeq ($(SUB_PROJECT),chipyard)
 	TB                ?= TestDriver
 	TOP               ?= ChipTop
 endif
-# for Hwacha developers
-ifeq ($(SUB_PROJECT),hwacha)
-	SBT_PROJECT       ?= chipyard
-	MODEL             ?= TestHarness
-	VLOG_MODEL        ?= $(MODEL)
-	MODEL_PACKAGE     ?= freechips.rocketchip.system
-	CONFIG            ?= HwachaConfig
-	CONFIG_PACKAGE    ?= hwacha
-	GENERATOR_PACKAGE ?= chipyard
-	TB                ?= TestDriver
-	TOP               ?= ExampleRocketSystem
-endif
 # For TestChipIP developers running unit-tests
 ifeq ($(SUB_PROJECT),testchipip)
 	SBT_PROJECT       ?= chipyard
@@ -154,9 +142,6 @@ CHIPYARD_RSRCS_DIR   = $(base_dir)/generators/chipyard/src/main/resources
 # names of various files needed to compile and run things
 #########################################################################################
 long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG)
-ifeq ($(GENERATOR_PACKAGE),hwacha)
-	long_name=$(MODEL_PACKAGE).$(CONFIG)
-endif
 
 # classpaths
 CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache