From 85d18b736edae53ebcbedc3bd1f41cca2ef4bde3 Mon Sep 17 00:00:00 2001 From: Edward Wang Date: Mon, 31 Jul 2017 15:53:46 -0700 Subject: [PATCH] Document --- macros/src/main/scala/MacroCompiler.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala index 129d86a1..a96043f2 100644 --- a/macros/src/main/scala/MacroCompiler.scala +++ b/macros/src/main/scala/MacroCompiler.scala @@ -448,6 +448,8 @@ object MacroCompiler extends App { val verilogWriter = new FileWriter(new File(params.get(Verilog).get)) if (macros.nonEmpty) { + // Note: the last macro in the input list is (seemingly arbitrarily) + // determined as the firrtl "top-level module". val circuit = Circuit(NoInfo, macros, macros.last.name) val annotations = AnnotationMap(Seq(MacroCompilerAnnotation( circuit.main, params.get(Macros).get, params.get(Library), synflops)))