add blkdev ci | cleanup simfiles to remove duplicates

This commit is contained in:
abejgonzalez
2019-07-12 13:24:08 -07:00
parent 26a67fdbad
commit 85d904f108
6 changed files with 56 additions and 21 deletions

View File

@@ -233,6 +233,35 @@ jobs:
key: rocketchip-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-blockdevrocketchip:
docker:
- image: riscvboom/riscvboom-images:0.0.10
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
- add_ssh_keys:
fingerprints:
- "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Building the blockdevrocketchip subproject using Verilator
command: .circleci/do-rtl-build.sh blockdevrocketchip
no_output_timeout: 120m
- save_cache:
key: blockdevrocketchip-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-hwacha:
docker:
- image: riscvboom/riscvboom-images:0.0.10
@@ -449,6 +478,11 @@ workflows:
- install-riscv-toolchain
- install-verilator
- prepare-blockdevrocketchip:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-hwacha:
requires:
- install-esp-toolchain

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@@ -40,4 +40,5 @@ mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig"
mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig"
mapping["boom"]="SUB_PROJECT=boom"
mapping["rocketchip"]="SUB_PROJECT=rocketchip"
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice"
mapping["hwacha"]="SUB_PROJECT=hwacha"

View File

@@ -53,9 +53,10 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
# note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time
$(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
grep -v ".*\.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_harness_blackboxes)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
MACROCOMPILER_MODE ?= --mode synflops
@@ -66,6 +67,14 @@ HARNESS_MACROCOMPILER_MODE = --mode synflops
$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"
########################################################################################
# remove duplicate/*.h files in blackbox/simfiles
########################################################################################
sim_files ?= $(build_dir)/sim_files.common.f
$(sim_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_dotf)
awk '{print $1;}' $^ | sort -u | grep -v ".*\.h" > $@
#########################################################################################
# helper rule to just make verilog files
#########################################################################################

View File

@@ -57,19 +57,19 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
#########################################################################################
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
$(model_mk): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-o $(sim) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@
$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
$(model_mk_debug): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@
@@ -95,4 +95,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean
clean:
rm -rf $(gen_dir)/* $(sim_prefix)-*
rm -rf $(gen_dir) $(sim_prefix)-*

View File

@@ -60,8 +60,7 @@ VCS_NONCC_OPTS = \
+v2k \
+vcs+lic+wait \
+vc+list \
-f $(sim_vcs_blackboxes) \
-f $(sim_dotf) \
-f $(sim_files) \
-sverilog \
+incdir+$(build_dir) \
+define+CLOCK_PERIOD=1.0 \
@@ -76,22 +75,14 @@ VCS_NONCC_OPTS = \
VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
########################################################################################
# remove duplicate blackboxes
########################################################################################
sim_vcs_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.vcs.f
$(sim_vcs_blackboxes): $(sim_top_blackboxes) $(sim_harness_blackboxes)
awk '{print $1;}' $^ | sort -u > $@
#########################################################################################
# vcs simulator rules
#########################################################################################
$(sim): $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes)
$(sim): $(sim_vsrcs) $(sim_files)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-debug_pp
$(sim_debug) : $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes)
$(sim_debug) : $(sim_vsrcs) $(sim_files)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+define+DEBUG -debug_pp
@@ -106,4 +97,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean
clean:
rm -rf $(gen_dir)/* csrc $(sim_prefix)-* ucli.key vc_hdrs.h
rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h