Add ARTY100t bringup + TSI-over-UART

2023-02-12 21:31:29 -08:00
parent 3dc4fff29b
commit 85fa9d1120
18 changed files with 240 additions and 33 deletions
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -47,7 +47,6 @@ class WithVCU118Tweaks extends Config(
  // io binders
  new WithUARTIOPassthrough ++
  new WithSPIIOPassthrough ++
-  new WithTLIOPassthrough ++
  // other configuration
  new WithDefaultPeripherals ++
  new chipyard.config.WithTLBackingMemory ++ // use TL backing memory