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Bump verilator to v5.018

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This commit is contained in:
Jerry Zhao
2023-12-28 07:36:53 -08:00
parent cce5122fd2
commit 8600640a40
4 changed files with 680 additions and 657 deletions
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6
conda-reqs/chipyard.yaml
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@@ -23,8 +23,8 @@ dependencies:
# bundle FireSim driver with deps into installer shell-script
- constructor
- gcc<13
- gxx<13
- gcc<12
- gxx<12
- sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
- conda-gcc-specs
- binutils
@@ -88,7 +88,7 @@ dependencies:
- graphviz
- expect
- dtc
- verilator==5.008
- verilator==5.018
- screen
- elfutils
- libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock

664
conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml generated
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660
conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml generated
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File diff suppressed because it is too large Load Diff

7
sims/verilator/Makefile
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@@ -162,8 +162,7 @@ VERILATOR_NONCC_OPTS = \
VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \
-DVERILATOR \
-include $(build_dir)/$(long_name).plusArgs
-DVERILATOR
VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
@@ -194,13 +193,13 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
$(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir)
mkdir -p $(model_dir)
$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
touch $@
$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir_debug)
mkdir -p $(model_dir_debug)
$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
touch $@
#########################################################################################