diff --git a/build.sbt b/build.sbt
index 633ff032..55a28adf 100644
--- a/build.sbt
+++ b/build.sbt
@@ -24,10 +24,14 @@ lazy val rebarFirrtl = (project in file("tools/firrtl"))
 
 lazy val rocketchip = RootProject(file("generators/rocket-chip"))
 
-lazy val testchipip = (project in file("generators/testchipip"))
+lazy val rebarrocketchip = project
   .dependsOn(rocketchip)
   .settings(commonSettings)
 
+lazy val testchipip = (project in file("generators/testchipip"))
+  .dependsOn(rebarrocketchip)
+  .settings(commonSettings)
+
 // Checks for -DROCKET_USE_MAVEN.
 // If it's there, use a maven dependency.
 // Else, depend on subprojects in git submodules.
@@ -46,7 +50,7 @@ lazy val example = conditionalDependsOn(project in file("."))
   .settings(commonSettings)
 
 lazy val boom = (project in file("generators/boom"))
-  .dependsOn(rocketchip)
+  .dependsOn(rebarrocketchip)
   .settings(commonSettings)
 
 lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
@@ -57,10 +61,10 @@ lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
   .settings(commonSettings)
 
 lazy val `barstools-macros` = (project in file("./tools/barstools/macros/"))
-  .dependsOn(mdf, rocketchip, rebarFirrtl)
+  .dependsOn(mdf, rebarrocketchip, rebarFirrtl)
   .enablePlugins(sbtassembly.AssemblyPlugin)
   .settings(commonSettings)
 
 lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
-  .dependsOn(rocketchip)
+  .dependsOn(rebarrocketchip)
   .settings(commonSettings)
diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala
index 09c2cd77..98d69c8a 100644
--- a/src/main/scala/example/Simulator.scala
+++ b/src/main/scala/example/Simulator.scala
@@ -102,6 +102,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     firrtl.FileUtils.makeDirectory("./bootrom/")
     writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
     writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
+    writeResource("/project-template/bootrom/bootrom.img", "./bootrom/")
   }
 
   def writeFiles(cfg: GenerateSimConfig): Unit = {
diff --git a/variables.mk b/variables.mk
index 34d829fe..9b52c45c 100644
--- a/variables.mk
+++ b/variables.mk
@@ -42,6 +42,15 @@ ifeq ($(SUB_PROJECT),boom)
 	SBT_PROJECT=boom
 	TOP=ExampleBoomSystem
 endif
+ifeq ($(SUB_PROJECT),rocketchip)
+	# for Rocket-chip developers
+	PROJECT=freechips.rocketchip.system
+	MODEL=TestHarness
+	CONFIG=DefaultConfig
+	CFG_PROJECT=freechips.rocketchip.system
+	SBT_PROJECT=rebarrocketchip
+	TOP=ExampleRocketSystem
+endif
 
 #########################################################################################
 # path to rocket-chip and testchipip
@@ -55,6 +64,11 @@ REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl
 #########################################################################################
 long_name = $(PROJECT).$(MODEL).$(CONFIG)
 
+# if building from rocketchip, override the long_name to match what they expect
+ifeq ($(SBT_PROJECT),rebarrocketchip)
+	long_name=$(PROJECT).$(CONFIG)
+endif
+
 FIRRTL_FILE  ?= $(build_dir)/$(long_name).fir
 ANNO_FILE    ?= $(build_dir)/$(long_name).anno.json
 VERILOG_FILE ?= $(build_dir)/$(long_name).top.v