Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge

generators/example/src/main/scala/Generator.scala

@@ -31,7 +31,7 @@ object Generator extends GeneratorApp {
   }
 
   // specify the name that the generator outputs files as
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
 
   // generate files
   generateFirrtl

generators/example/src/main/scala/TestHarness.scala

@@ -30,7 +30,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
 
   val dut = p(BuildTop)(clock, reset.toBool, p)
 
-  dut.debug := DontCare
+  dut.debug.foreach(_ := DontCare)
   dut.connectSimAXIMem()
   dut.connectSimAXIMMIO()
   dut.dontTouchPorts()
@@ -65,7 +65,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
 
   val dut = p(BuildTopWithDTM)(clock, reset.toBool, p)
 
-  dut.reset := reset.asBool | dut.debug.ndreset
+  dut.reset := reset.asBool | dut.debug.get.ndreset
   dut.connectSimAXIMem()
   dut.connectSimAXIMMIO()
   dut.dontTouchPorts()
@@ -83,5 +83,5 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
     }
   })
 
-  Debug.connectDebug(dut.debug, clock, reset.asBool, io.success)
+  Debug.connectDebug(dut.debug, dut.psd, clock, reset.asBool, io.success)
 }

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -21,13 +21,13 @@ import firesim.util.RegisterBridgeBinder
 import tracegen.HasTraceGenTilesModuleImp
 
 class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
-  target.debug.clockeddmi.foreach({ cdmi =>
+  target.debug.foreach(_.clockeddmi.foreach({ cdmi =>
     cdmi.dmi.req.valid := false.B
     cdmi.dmi.req.bits := DontCare
     cdmi.dmi.resp.ready := false.B
     cdmi.dmiClock := false.B.asClock
     cdmi.dmiReset := false.B
-  })
+  }))
   Seq()
 })
 

generators/firechip/src/main/scala/Generator.scala

@@ -4,7 +4,7 @@ package firesim.firesim
 
 import java.io.{File, FileWriter}
 
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.internal.firrtl.{Circuit, Port}
 
 import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
@@ -58,7 +58,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
 }
 
 object FireSimGenerator extends App with IsFireSimGeneratorLike {
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
   // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
@@ -70,7 +70,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
 
 // For now, provide a separate generator app when not specifically building for FireSim
 object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites {
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   generateFirrtl
   generateAnno
   generateTestSuiteMakefrags

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -10,7 +10,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
-import freechips.rocketchip.devices.debug.DebugModuleParams
+import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import boom.common.BoomTilesKey
 import testchipip.{BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -77,7 +77,7 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
 
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
-  case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false)
+  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
 })
 
 // Testing configurations

generators/tracegen/src/main/scala/TestHarness.scala

@@ -17,7 +17,7 @@ class TestHarness(implicit p: Parameters) extends Module {
 
 object Generator extends GeneratorApp {
   // specify the name that the generator outputs files as
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
 
   // generate files
   generateFirrtl

generators/utilities/src/main/scala/Subsystem.scala

@@ -66,7 +66,7 @@ trait HasBoomAndRocketTiles extends HasTiles
       def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets)
       LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree)
 
-      connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
+      connectInterrupts(tile, debugOpt, clintOpt, plicOpt)
 
       tile
     }